CN116939134A - HDMI system based on MIPIDPHY output - Google Patents
HDMI system based on MIPIDPHY output Download PDFInfo
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- CN116939134A CN116939134A CN202310719569.2A CN202310719569A CN116939134A CN 116939134 A CN116939134 A CN 116939134A CN 202310719569 A CN202310719569 A CN 202310719569A CN 116939134 A CN116939134 A CN 116939134A
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- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical compound C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 claims description 6
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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Abstract
The application relates to the technical field of video data processing and discloses an HDMI system based on MIPIDPHY output, which comprises HDMI and MIPI, wherein the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, the MIPI output end is connected with the DPHY module, the DPHY module output end is connected with hardware AC coupling, the hardware AC coupling is connected with hardware DC bias, the coding module comprises DC balance, the DC balance is connected with AUX management, the AUX management is connected with DDC control, the DDC control is connected with Audio coding, the data stream conversion module comprises a displacement Buffer, and the displacement Buffer is connected with time slot management. Through the mobile device platform main chip of current mainstream generally all does not have the HDMI interface, when the user wants to access the large screen expansion and display, all adopt the mode of WIFI with the screen basically, this scheme can bring high delay and loaded down with trivial details installation pairing link.
Description
Technical Field
The application relates to the technical field of video data processing, in particular to an HDMI system based on MIPIDPHY output.
Background
Along with the continuous improvement of the social informatization degree, the requirements of people on video processing are higher and higher, the data volume processed by a video processing system is also larger and larger, and in an embedded video processing system, the main current schemes are mainly 3: ARM-based, DSP-based, and FPGA-based. The FPGA is different from other two chips, is a semi-custom circuit, has a large number of logic units, can construct corresponding circuits to realize required functions by configuring the logic units, is widely applied to high-speed video processing systems because of the characteristics of hardware acceleration, is a full-digital video and audio transmission interface in an interface of a video processing system, can transmit uncompressed audio and video signals, has the advantages of high bandwidth, small volume, high intelligence, content protection and the like, and is widely applied to high-definition displays and high-definition televisions.
The scheme has the defects that the LVDS differential pin of the FPGA or the Serdes pin is utilized to simulate the TMDS level of the HDMI to directly output the HDMI, the LVDS pin rate of the low-cost and small-volume FPGA can only support 1Gbps, the resolution of the HD (720 p) can be realized at maximum, the FPGA with the high-rate LVDS or the Serdes pin is very expensive in general price and correspondingly high in volume power consumption, the HDMI output is realized by utilizing the FPGA+ADV-Convert mode, the scheme has the defects of a double-chip scheme, high cost/volume/high power consumption and almost no value on the current mainstream wearing, moving and handheld equipment. With the rapid development of mobile devices, MIPI has been widely used as a physical layer interface for smart phone cameras and displays due to its cost-effective flexibility, high speed and low power consumption, and the specification has also been applied to various other applications such as unmanned aerial vehicles, artificial intelligence, ultra-large tablet computers, surveillance cameras and industrial robots, and automotive applications including camera sensing systems, anti-collision radar, car infotainment and dashboard display, so MIPI interfaces have been used as armors of FPGA industry in recent years, from the very beginning soft core to the very beginning hard core MIPI interfaces supporting 2.5Gbps, which have gradually become standard interfaces for FPGA/CPLD, so we have attempted to implement HDMI output using MIPI interfaces, i.e., to perfectly solve the above HDMI interface problem in mobile devices.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides an HDMI system based on MIPIDPHY output, which solves the problem that large cost is required to be consumed to ensure the display effect when HDMI is output.
In order to achieve the above purpose, the application is realized by the following technical scheme: the HDMI system based on MIPIDPHY output comprises HDMI and MIPI, wherein the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, the MIPI output end is connected with the DPHY module, the DPHY module output end is connected with hardware AC coupling, and the hardware AC coupling is connected with hardware DC bias.
Preferably, the encoding module comprises direct current equalization, wherein the direct current equalization is connected with AUX management, the AUX management is connected with DDC control, and the DDC control is connected with Audio encoding.
Preferably, the data stream conversion module comprises a displacement Buffer, the displacement Buffer is connected with time slot management, the time slot management is connected with a BitFlip, the BitFlip is connected with Fifo control, the Fifo control is connected with link initialization locking, and the link initialization locking is connected with rate matching.
Preferably, the HDMI includes a PLL module connected with an LP control module connected with a TMDS moderate packet.
Working principle: the HDMI coding mode TMDS-Encoder outputs data Bit width is 10Bit, and MIPI physical layer interface is 8Bit mode, therefore we can not simply call HDMI-IP integrated by chip, but we need to finish HDMI coding module realization independently, in TMDS-Transmitter module example, we take out 3x10Bit data stream after finishing basic coding function, transfer to next stage module to convert, data stream conversion is first according to different rate, accomplish clock matching and shift buffer of input data through PLL module, because clock frequency difference, data need write FIFO module to carry on cross-domain conversion, then read link layer state wait Ready, time slot read FIFO data out package recombination transmit MIPI-DPHY module, MIPI electrical characteristic signal swing is 200mv, HDMI signal swing is 400mv, therefore HDMI (HDMI base) is regulated in HDMI DeviceConstraint Editor (HDMI tool option) to increase HDMI pin attribute and enhance driving current, HDMI physical layer high-speed signal is added in HDMI hardware at the same time, MIPI physical layer is not added with direct current component, direct current coupling is removed by DC component is not required by DC component, but direct current coupling is not required by DC component is removed by DC component 1, but direct current coupling is realized by DC component is not required by DC coupling of DC channel 1, direct current coupling is realized by DC channel 1, direct current coupling is not required by DC coupling, direct current coupling is realized by DC component is realized by DC channel 1, and DC coupling is not directly coupled with DC component, because 1 and DC component is used, we add a clock packet module of TMDS and then transmit with the remaining Data-Lane on MIPI.
The application provides an HDMI system based on MIPIDPHY output. The beneficial effects are as follows:
the main chip of the mobile equipment platform of the current main stream is generally not provided with the HDMI interface, and when a user wants to access a large screen for expansion display, the WIFI mode is basically adopted, and the scheme can bring high delay and complicated installation pairing links, and the key point is that the frequency of the low-cost/small-volume FPGA or CPLD is generally low at present, the HDMI output of high resolution (1080 p) is almost impossible, but the MIPI-DPHY hard core is basically mature and quick in frequency.
Drawings
FIG. 1 is a schematic diagram of a TMDS-Transmitter module of the present application;
FIG. 2 is a diagram of a hardware DC bias circuit of the present application;
fig. 3 is a circuit diagram of the hardware conversion of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Examples:
referring to fig. 1, an embodiment of the application provides an HDMI system based on mipidhy output, which includes HDMI and MIPI, wherein the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, an MIPI output end is connected with the DPHY module, an output end of the DPHY module is connected with a hardware ac coupling, and the hardware ac coupling is connected with a hardware dc bias.
The data Bit width of the TMDS-Encoder output in the HDMI coding mode is 10Bit, the physical layer interface of MIPI is 8Bit mode, the HDMI coding module is required to be realized autonomously, and 3x10Bit data stream is extracted after the basic coding function is finished and transmitted to the next-stage module for conversion; according to different rates, clock matching is completed through a PLL module and input data is shifted by the buffer, the electric characteristic signal swing of MIPI is 200mv, but the signal swing of HDMI is 400mv, so IO pin attribute is adjusted in a DeviceConstraintEditor of a compiling tool to increase swing and enhance driving current, direct current bias is added in hardware, a MIPI physical layer is formed by overlapping a high-speed signal and a low-speed LP signal, HDMI does not have a low-speed signal, an LP control module (LP and the high-speed signal are overlapped and transmitted), and when the high-speed signal is in different states, the low-speed signal needs to be matched with corresponding 0, 1 and high-resistance states, so that high-speed transmission can not be influenced at all); the HDMI uses AC coupling (DC component is removed by DC blocking capacitive coupling) and MIPI uses DC coupling (DCCUUpling is that DC and AC are passed together and AC components are not removed), so that a hardware conversion circuit is added, the following clock of HDMI is 1/10 of data frequency, the following clock of MIPI is 1/2 of data, so that the clock channel of MIPI-DPHY cannot be directly used, but MIPI protocol data is 4Lane, HDMI data is only 3Lane, and TMDS clock packet module is added.
The coding module comprises direct current balance, wherein the direct current balance is connected with AUX management, the AUX management is connected with DDC control, and the DDC control is connected with Audio coding.
The direct current equalization is that the 8-bit character is encoded by minimum change of exclusive OR or exclusive OR with the first 1 bit of the remaining 7 bits under the condition that the lowest bit is unchanged, and then the encoding instruction bit is added to generate 9-bit characters (the actual exclusive OR or exclusive OR is determined by the number of 1 contained in 8-bit data, the 9-bit mark adopts which conversion mode, and 0 represents exclusive OR and 1 represents exclusive OR). Then, according to the number of data 0 and 1 already transmitted and the number of data 0 and 1 currently transmitted, determining whether to invert 8 data bits in the 9-bit information generated in the first step (if more 1 is already transmitted and 1 of the current data is more than 0, then invert), and converting the data into a 10-bit direct current balance code (whether a 10-bit flag is inverted, wherein 1 indicates inversion and 0 indicates no inversion); AUX management: insert encoding of auxiliary information in the video stream, such as pixel format, color depth, resolution information, boundary characters, ECC check codes; DDC control: DDC (DisplayDataChannel) is a specification of a terminal display for informing a personal computer of display information (such as resolution, scanning frequency, etc.), that is, a communication method between the display and a host system, and is mainly aimed at realizing Plug & Play (Plug & Play) functions; audio coding: the audio signal adopts a data packet structure, and a check bit is added to ensure the reliability of the audio signal, and 4-bit data is converted into 10 bits by TERC4 encoding. Since the video sampling clock and the audio sampling clock are different in frequency and the audio and video transmission frequencies are the same, synchronization of the audio and video clocks is maintained, that is, the relation between the transmission frequency of HDMI and the audio sampling clock frequency is to be determined, 128 xfs=video rate xN/CTS (fs is the audio sampling frequency, N and CTS are parameters to be transmitted by the audio clock reconstruction data packet), N and CTS are calculated by the signal source, and the audio and video synchronization is achieved by transmitting the audio reconstruction data packet to the receiver.
The data stream conversion module comprises a displacement Buffer, wherein the displacement Buffer is connected with time slot management, the time slot management is connected with BitFlip, bitFlip, the Fifo control is connected with link initialization locking, and the link initialization locking is connected with rate matching.
Because of the difference of clock frequency, data is required to be written into the FIFO module to carry out cross-domain conversion, and then after the read link layer state waits for Ready, the data of the FIFO is read out in a time slot, packed and recombined and transmitted to the MIPI-DPHY module; buffer is a data Buffer, and the least common multiple of the input 10Bit data stream and the output 8Bit data stream is 40, so that the input data is required to be shifted into 40 bits and buffered for subsequent processing; FIFO is an abbreviation for FirstIn/FirstOut, meaning first-in first-out. The FIFO memory is divided into a writing special area and a reading special area, and the reading operation and the writing operation can be performed asynchronously, so that the FIFO memory can be controlled to be converted by a clock domain; the time slot management is that the input and output data bit width and the clock frequency are different, and the time slot interval needs to be calculated and the state of the FiFo counter is inquired to make timely adjustment under the condition that the data stream is not interrupted and the FiFo is not empty and full; link initialization locking: before data output, the link layer is required to be completely stable, otherwise abnormal initialization occurs, so that the situations such as black screen, splash screen and the like occur, the state of the link layer is required to be queried in real time, and once the lost locking is found, the whole system is required to be reset in time, so that the situation that errors cannot be recovered is prevented; bitFlip is bit exchange, because the front end has a series of operations such as shifting, buffering, splitting and the like, the bit position has been changed, and the bit position needs to be adapted according to the bottom driving mode of the chip due to the different size end modes;
HDMI includes the PLL module, and the PLL module is connected with the LP control module, and the LP control module is connected with the moderate package of TMDS.
Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. The HDMI system based on MIPIDPHY output comprises HDMI and MIPI, and is characterized in that the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, an MIPI output end is connected with the DPHY module, an output end of the DPHY module is connected with hardware AC coupling, and the hardware AC coupling is connected with hardware DC bias.
2. The HDMI system of claim 1, wherein the encoding module comprises dc equalization, wherein the dc equalization is connected with AUX management, wherein the AUX management is connected with DDC control, and wherein the DDC control is connected with Audio encoding.
3. The HDMI system of claim 1, wherein said data stream conversion module comprises a shift Buffer, said shift Buffer is connected with a time slot manager, said time slot manager is connected with a BitFlip, said BitFlip is connected with a Fifo control, said Fifo control is connected with a link initialization lock, said link initialization lock is connected with a rate matching.
4. The HDMI system of claim 1, wherein said HDMI comprises a PLL module, said PLL module being connected to an LP control module, said LP control module being connected to a TMDS moderate packet.
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| CN202310719569.2A CN116939134A (en) | 2023-06-16 | 2023-06-16 | HDMI system based on MIPIDPHY output |
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| CN202310719569.2A CN116939134A (en) | 2023-06-16 | 2023-06-16 | HDMI system based on MIPIDPHY output |
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