CN116132823A - MIPI D-PHY drive-based image generator - Google Patents
MIPI D-PHY drive-based image generator Download PDFInfo
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- CN116132823A CN116132823A CN202310142837.9A CN202310142837A CN116132823A CN 116132823 A CN116132823 A CN 116132823A CN 202310142837 A CN202310142837 A CN 202310142837A CN 116132823 A CN116132823 A CN 116132823A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses an image generator based on MIPID-PHY drive, which comprises an MCU module and an FPGA module electrically connected with the MCU module; the MCU module is configured to output a control instruction and control the FPGA module to call the image data signals; the FPGA module is electrically connected with at least one signal conversion module, and the signal conversion module is electrically connected with an output module; the FPGA module is configured to receive the control instruction of the MCU module and transmit the image data signal to the signal conversion module, and the signal conversion module performs image data signal conversion and then performs image data signal output through the output module; the invention adopts the FPGA+MCU frame to build the signal conversion chip, can directly drive the display product, generates the integrated power supply and the image data signal to drive the image generator into a whole, and has small realization volume and low cost.
Description
Technical Field
The invention relates to the field of image generation, in particular to an image generator based on MIPI D-PHY drive.
Background
MIPI D-PHY based driver development is mainly applied to medium-low end products in the prior art, and each driver uses a driver scheme customized by a screen manufacturer. The general architecture is: the computer host, the screen power supply and the switching module are matched for use; the DP interface or HDMI interface of the host computer is used, the interface is converted into the image required by the screen through the switching module, the prior art can not generate the image with any resolution, the refresh rate is low, and the whole volume is large.
Mi cro LED & OLED belongs to the front technology, and is widely applied to the AR/VR field in the future, higher resolution and screen refresh rate are needed, the prior art is difficult to meet the requirements, and the driving of micro-display medium-high-speed Mi cro LED & OLED becomes a key technology for testing AR/VR; the MIPI DSI D-PHY protocol standard needs to be grasped, based on which higher rate transmissions are achieved.
The existing image generator is large in size, single in function, low in efficiency and high in price, all parts need to be replaced after the product is replaced, and the existing image generator cannot be suitable for mass production of the product.
Disclosure of Invention
In order to solve at least one technical problem, the invention provides an image generator based on MIPID-PHY driving.
A first aspect of the present invention provides an MIPI D-PHY driven based image generator, comprising: the MCU module is electrically connected with the FPGA module;
the MCU module is configured to output a control instruction and control the FPGA module to call the image data signals;
the FPGA module is electrically connected with at least one signal conversion module, and the signal conversion module is electrically connected with an output module;
the FPGA module is configured to receive a control instruction of the MCU module and transmit the image data signals to the signal conversion module, and the signal conversion module performs image data signal conversion and then performs image data signal output through the output module.
In a preferred embodiment of the present invention, the present invention further includes an upper computer, and the upper computer is electrically connected to the MCU module through an ethernet module.
In a preferred embodiment of the present invention, the FPGA module includes an FPGA platform and a memory module, and the MCU module is electrically connected to the memory module.
In a preferred embodiment of the present invention, a first buffer module is disposed between the MCU module and the storage module.
In a preferred embodiment of the present invention, a second buffer module is disposed between the FPGA platform and the storage module.
In a preferred embodiment of the present invention, the signal conversion module includes a D-PHY signal conversion module and a C-PHY signal conversion module.
In a preferred embodiment of the present invention, the D-PHY signal conversion module and the C-PHY signal conversion module are electrically connected to the output module.
In a preferred embodiment of the present invention, the output module is electrically connected to a display screen, and the display screen includes Micro LEDs or OLEDs.
In a preferred embodiment of the present invention, the display screen is electrically connected to a power input module, the power input module includes a first programmable power source and a second programmable power source, the first programmable power source and the second programmable power source are electrically connected to a power output interface, and an output end of the first programmable power source is provided with a positive-negative output conversion module.
In a preferred embodiment of the present invention, the power output interface is electrically connected to a voltage detection module, a current detection module, an overvoltage protection module and an overcurrent protection module.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the FPGA+MCU frame is adopted to build the signal conversion chip, so that a display product can be directly driven, an 8-channel programmable power supply is matched, an integrated power supply and an image data signal are generated to drive the image generator into a whole, the size is small, the cost is low, the general driving micro-display medium-high-speed mi cro LED and OLED products are realized, the line replacement is not needed, the production test efficiency of the display product is improved, and in addition, the invention realizes the image display with arbitrary resolution and higher screen refresh rate based on the characteristic of high-speed transmission of the FPGA, and the integration level is high.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that some drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of an image generator system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a power input module according to an embodiment of the invention.
Detailed Description
In order that the above-recited objects, features and advantages of the invention will be more clearly understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
Example 1
Referring to fig. 1-2, the present invention proposes an image generator based on MIPI D-PHY driving, comprising: the MCU module is electrically connected with the FPGA module;
the MCU module is configured to output a control instruction and control the FPGA module to call the image data signals;
the FPGA module is electrically connected with at least one signal conversion module, and the signal conversion module is electrically connected with an output module;
the FPGA module is configured to receive the control instruction of the MCU module and transmit the image data signal to the signal conversion module, and the signal conversion module performs image data signal conversion and then performs image data signal output through the output module.
In a specific example of the present invention, the system further includes an upper computer, and the upper computer is electrically connected to the MCU module through the ethernet module.
In a specific example of the present invention, the FPGA module includes an FPGA platform and a memory module, and the MCU module is electrically connected to the memory module.
Further, a first buffer module is arranged between the MCU module and the storage module, and a second buffer module is arranged between the FPGA platform and the storage module.
Specifically, the first buffer module and the second buffer module are used for buffering data, so that data calling can be conveniently carried out when the data is used next time, and the image data can be transmitted to the MCU by the upper computer through the Ethernet module; the MCU uses the first buffer module to put the data into the storage module; after the data storage is completed, the MCU sends out an output instruction to the FPGA; after receiving the instruction, the FPGA uses a second buffer module to take out the data from the storage module; the FPGA starts to receive the image data; after the FPGA receives data, the FPGA starts to output data signals to the signal conversion module; the signal conversion module outputs the received data in MIPI D-PHY/C-PHY form.
In one specific example of the present invention, the signal conversion module includes a D-PHY signal conversion module and a C-PHY signal conversion module.
In one embodiment of the present invention, the D-PHY signal conversion module and the C-PHY signal conversion module are both electrically connected to the output module.
In a specific example of the present invention, the output module is electrically connected to a display screen, and the display screen includes a Mi cro LED or an OLED.
Further, the display screen electric connection has power input module, and power input module includes first programmable power supply and second programmable power supply, and first programmable power supply and second programmable power supply electric connection have power output interface, and first programmable power supply's output is provided with positive negative output conversion module.
In a specific example of the present invention, the power output interface is electrically connected to a voltage detection module, a current detection module, an overvoltage protection module, and an overcurrent protection module.
Furthermore, the power output module for driving the Micro LED and OLED screen adopts two programmable power modules, each module supports 4-channel 0-11V/2A adjustable output, and can be used in parallel to output large current. The Micro LED and the OLED need negative voltage output, a positive-negative output conversion module is added in the scheme, positive voltage can be converted into negative voltage, programmable bipolar power supply output is realized, and the voltage and current output condition can be monitored in real time due to the fact that the Micro LED and the OLED are driven to have strict requirements on power supply.
Specifically, the voltage of the power output interface is monitored in real time through the voltage detection module, when the voltage value exceeds a preset voltage value, the overvoltage protection module controls the power output interface to be disconnected, so that the fault is prevented from expanding, the current detection module is used for monitoring the current of the power output interface in real time, and when the current value is larger than the preset current value, the overcurrent protection module controls the power output interface to be disconnected.
The working principle of the invention is as follows:
a power input module is used for supplying power to the MIPI image data output module and the power output module at the same time;
the MIPI image data output module performs data interaction with the communication module in the power output module through the MCU control communication module;
the MCU controls the power-on time sequence and voltage output of the power output module;
the MCU receives each voltage and current detection condition of the power supply output module and judges whether the output result meets the requirement;
the upper computer outputs image data to the MCU;
the MCU stores the image data in a memory to wait for sending to the FPGA;
the FPGA receives the image data and then sends the image data to the signal conversion module;
the signal conversion module outputs to Micro LED or OLED in MIPI D-PHY/C-PHY protocol format, and the screen is lighted.
In summary, the FPGA+MCU frame is adopted to build the signal conversion chip, so that the display product can be directly driven, the 8 paths of programmable power supplies are matched to generate the integrated power supply and the image data signal to drive the image generator into a whole, the size is small, the cost is low, the micro-display medium-high speed mi cro LED and OLED products are generally driven, the line replacement is not needed, the production test efficiency of the display product is improved, and in addition, the invention can realize the image display with any resolution and higher screen refresh rate based on the characteristic of high-speed transmission of the FPGA, and the integration level is high.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the embodiments described above will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An MIPID-PHY driven based image generator, comprising: the MCU module is electrically connected with the FPGA module;
the MCU module is configured to output a control instruction and control the FPGA module to call the image data signals;
the FPGA module is electrically connected with at least one signal conversion module, and the signal conversion module is electrically connected with an output module;
the FPGA module is configured to receive a control instruction of the MCU module and transmit the image data signals to the signal conversion module, and the signal conversion module performs image data signal conversion and then performs image data signal output through the output module.
2. The MIPID-PHY driven image generator of claim 1 further comprising a host computer, wherein the host computer is electrically coupled to the MCU module via an ethernet module.
3. The MIPID-PHY driven image generator of claim 1 wherein the FPGA module comprises an FPGA platform and a memory module, the MCU module being electrically connected to the memory module.
4. A MIPID-PHY driven image generator as defined in claim 3, wherein a first cache module is provided between the MCU module and the memory module.
5. A MIPID-PHY driven image generator as defined in claim 3, wherein a second cache module is provided between the FPGA platform and the memory module.
6. The MIPID-PHY driven image generator of claim 1, wherein the signal conversion module comprises a D-PHY signal conversion module and a C-PHY signal conversion module.
7. The MIPID-PHY driven image generator of claim 6 wherein the D-PHY signal conversion block and the C-PHY signal conversion block are electrically coupled to the output block.
8. The MIPID-PHY driven image generator of claim 1 wherein the output module is electrically connected to a display screen comprising Micro LEDs or OLEDs.
9. The image generator based on the MIPID-PHY drive of claim 8, wherein the display screen is electrically connected with a power input module, the power input module comprises a first programmable power supply and a second programmable power supply, the first programmable power supply and the second programmable power supply are electrically connected with a power output interface, and an output end of the first programmable power supply is provided with a positive-negative output conversion module.
10. The MIPID-PHY driven image generator of claim 9 wherein the power output interface is electrically connected to a voltage detection module, a current detection module, an overvoltage protection module, and an overcurrent protection module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310142837.9A CN116132823A (en) | 2023-02-21 | 2023-02-21 | MIPI D-PHY drive-based image generator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310142837.9A CN116132823A (en) | 2023-02-21 | 2023-02-21 | MIPI D-PHY drive-based image generator |
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| CN116132823A true CN116132823A (en) | 2023-05-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116939134A (en) * | 2023-06-16 | 2023-10-24 | 深圳市驰晶科技有限公司 | HDMI system based on MIPIDPHY output |
| CN117524029A (en) * | 2024-01-05 | 2024-02-06 | 武汉精立电子技术有限公司 | Test signal generation system and panel detection equipment |
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2023
- 2023-02-21 CN CN202310142837.9A patent/CN116132823A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116939134A (en) * | 2023-06-16 | 2023-10-24 | 深圳市驰晶科技有限公司 | HDMI system based on MIPIDPHY output |
| CN117524029A (en) * | 2024-01-05 | 2024-02-06 | 武汉精立电子技术有限公司 | Test signal generation system and panel detection equipment |
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