CN116938245B - Analog-to-digital converter calibration method and analog-to-digital converter - Google Patents

Analog-to-digital converter calibration method and analog-to-digital converter Download PDF

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CN116938245B
CN116938245B CN202311198948.8A CN202311198948A CN116938245B CN 116938245 B CN116938245 B CN 116938245B CN 202311198948 A CN202311198948 A CN 202311198948A CN 116938245 B CN116938245 B CN 116938245B
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voltage
comparator
analog
digital converter
input end
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CN116938245A (en
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刘尧
刘筱伟
杨超
尹杰
周小雯
刘森
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Micro Niche Guangzhou Semiconductor Co ltd
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Micro Niche Guangzhou Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides an analog-to-digital converter calibration method and an analog-to-digital converter, comprising the following steps: and respectively measuring a first error voltage and a second error voltage of a forward input end and a reverse input end of the comparator, performing difference calculation based on the first error voltage and the second error voltage to obtain a capacitor array error voltage of the analog-to-digital converter and the polarity of the capacitor array error voltage, and providing a calibration voltage with the same magnitude as the capacitor array error voltage for the input end of the comparator with opposite polarity so as to calibrate the voltage error of the analog-to-digital converter. According to the application, capacitors at two input ends of the comparator are respectively switched, so that errors of all side capacitors are counted in single-side error voltages, and then difference is directly made based on the error voltages at two sides, so that common offset voltage of the comparator is eliminated, and the calibration of the analog-to-digital converter is realized.

Description

Analog-to-digital converter calibration method and analog-to-digital converter
Technical Field
The present application relates to the field of analog-to-digital conversion, and in particular, to a calibration method of an analog-to-digital converter and an analog-to-digital converter.
Background
With the rapid development of computer processing technology, analog-to-digital converters (ADCs) play an increasingly important role as bridges for analog and digital signals. Among many ADC structures, successive approximation ADC (SAR ADC) is widely used due to its simple structure, small area, low cost, and ability to meet the speed, precision and power consumption requirements of most scenarios. However, as ADC fabrication processes continue to shrink, device mismatch, system noise, etc., continue to deteriorate such that the design of high-precision SAR ADCs becomes increasingly difficult. Therefore, to achieve a high-precision SAR ADC, additional capacitive error correction algorithms and noise cancellation methods need to be used.
The accuracy of the capacitor DAC array is the most important factor in determining SAR ADC accuracy, and bit capacitor mismatch can cause shift in the conversion output curve. The non-idealities that lead to capacitive DAC array mismatch are mainly two: firstly, limited matching precision; and secondly, due to parasitic capacitance effects in the capacitor array. The existing capacitance error correction algorithm is complex and can not solve the problem of parasitic capacitance existing in the whole capacitive array, for example: in the patent application of the patent number CN109728815, error measurement is carried out on the values of each capacitor bank through a comparator, and a record meter is used for conveniently searching error values later; and, as in patent application CN108462492, by adjusting the capacitors at the forward and reverse input ends respectively, the output signal of the differential input unit is turned twice to indicate that the calibration reaches the intermediate value, so as to complete the voltage calibration. These capacitance error correction algorithms are all used for calibrating the single capacitor, and the steps required for calibration are complex.
In order to solve the above problems, the application provides an analog-to-digital converter calibration method and an analog-to-digital converter, which are used for counteracting the mismatch value of a capacitor through a switching input end so as to realize the integral calibration of a capacitor array.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present application is to provide an analog-to-digital converter calibration method and an analog-to-digital converter for solving the problem of complicated steps of the calibration method in the prior art.
To achieve the above and other related objects, the present application provides a calibration method for an analog-to-digital converter, which is implemented based on a comparator, a first DAC capacitor array, a second DAC capacitor array, and a logic control module; the first DAC capacitor array and the second DAC capacitor array are respectively provided with n-bit capacitors and n switches, and the capacitors and the switches are arranged in a one-to-one correspondence manner; n is an integer greater than or equal to 1; the first polar plates of all the capacitors in the first DAC capacitor array are connected with the first input end of the comparator, and the second polar plates are respectively connected with the corresponding switches; the first polar plates of all the bit capacitors of the second DAC capacitor array are connected with the second input end of the comparator, and the second polar plates are respectively connected with the corresponding switches; the output end of the logic control module is respectively connected with each switch in the first DAC capacitor array and the second DAC capacitor array, and is used for switching each switch, so as to control the second pole plate of each capacitor to be connected with a reference voltage or a reference ground, and the analog-to-digital converter calibration method comprises the following steps:
s1, connecting second polar plates of n-bit capacitors of a first input end of a comparator with the reference voltage, connecting a second polar plate of i-bit capacitors of a second input end with the reference voltage, and connecting a second polar plate of (n-i) bit capacitors with the reference ground, and measuring the output voltage of the comparator as a first measurement voltage; all the bit capacitance level states of the second input end are overturned, and the output voltage of the comparator is measured again to be used as a second measurement voltage; calculating a first error voltage of the second input end based on the difference between the first measurement voltage and the second measurement voltage; i is an integer of 0 or more and n or less;
s2, connecting second polar plates of n-bit capacitors of a second input end of the comparator with the reference voltage, connecting a second polar plate of i-bit capacitors of a first input end with the reference voltage, and connecting a second polar plate of (n-i) bit capacitors with the reference ground, and measuring the output voltage of the comparator as a third measurement voltage; all the bit capacitance level states of the first input end are turned over, and the output voltage of the comparator is measured again to be used as a fourth measurement voltage; calculating a second error voltage of the first input end based on the difference between the third measurement voltage and the fourth measurement voltage;
s3, calculating a capacitance array error voltage of the analog-to-digital converter and the polarity of the capacitance array error voltage based on the difference between the first error voltage and the second error voltage;
and S4, providing a calibration voltage with the same magnitude as the capacitor array error voltage to the input end of the comparator with opposite polarity based on the polarity of the capacitor array error voltage, so as to calibrate the voltage error of the analog-to-digital converter.
Optionally, step S4 includes:
s41, providing a voltage with the same size as the capacitor array error voltage to a first polarity input end of the comparator based on the polarity of the capacitor array error voltage;
s42, sequentially determining potential states of all the capacitors at the second polarity input end of the comparator according to the sequence from the highest capacitor to the lowest capacitor based on a binary search algorithm until the output voltage of the comparator is smaller than a set value, and judging that the first polarity input end of the comparator is equal to the second polarity input end;
s43, removing the voltage of the first polarity input end of the comparator, and further obtaining a calibrated analog-digital converter;
the polarity of the first polarity input end is the same as the polarity of the capacitor array error voltage; the polarity of the second polarity input is opposite to the polarity of the capacitor array error voltage.
Optionally, the analog-to-digital converter calibration method further includes:
providing an error voltage to be calibrated for the logic control module based on a table look-up mode;
the logic control module switches the level state of each bit capacitor at the input end of the opposite polarity of the comparator based on the polarity and the magnitude of the error voltage until the voltage equal to the error voltage is obtained, so as to calibrate the voltage error of the analog-to-digital converter;
wherein the error voltage is set as a temperature error voltage or an input error voltage.
Optionally, based on the polarity of the error voltage to be calibrated, providing a voltage equal to the error voltage to the input terminal of the same polarity of the comparator;
sequentially determining potential states of all bit capacitors of the input ends of the comparator with opposite polarities according to the sequence from the highest bit capacitor to the lowest bit capacitor based on a binary search algorithm until the output voltage of the comparator is smaller than a set value, and judging that the input voltages of the two input ends of the comparator are equal;
and removing the input terminal voltages with the same polarity of the comparator, thereby obtaining the calibrated analog-to-digital converter.
To achieve the above and other related objects, the present application provides an analog-to-digital converter for implementing the above calibration method of the analog-to-digital converter, comprising:
the analog-to-digital converter comprises a comparator, a first DAC capacitor array, a second DAC capacitor array, a logic control module and a sampling and holding module;
the first DAC capacitor array and the second DAC capacitor array are respectively provided with n-bit capacitors and n switches, and the capacitors and the switches are arranged in a one-to-one correspondence manner; n is an integer greater than or equal to 1;
the first polar plates of all the capacitors in the first DAC capacitor array are connected with the first input end of the comparator, and the second polar plates are respectively connected with the corresponding switches; the first polar plates of all the bit capacitors of the second DAC capacitor array are connected with the second input end of the comparator, and the second polar plates are respectively connected with the corresponding switches;
the output end of the logic control module is respectively connected with each switch in the first DAC capacitor array and the second DAC capacitor array and is used for switching each switch so as to control the second pole plate of each capacitor to be connected with reference voltage or reference ground;
and the input end of the sampling and holding module is connected with the input voltage, and the output end of the sampling and holding module is connected with the comparator and is used for sampling voltage data and inputting the voltage data into the comparator.
Optionally, the sample-and-hold module is configured as two sample-and-hold units; each sample hold unit is connected with two input ends of the comparator respectively.
Optionally, the sample-and-hold module is configured as a sample-and-hold unit; and the positive input end of the comparator is connected with the sampling and holding unit, and the negative input end of the comparator is grounded.
Optionally, the sample-and-hold unit is configured as a sampling switch.
Optionally, the analog-to-digital converter further comprises a calibration module; the input end of the calibration module is connected with the output end of the comparator, and the output end of the calibration module is connected with the logic control module and is used for storing error voltage and providing the error voltage to be calibrated to the logic control module so as to calibrate the analog-to-digital converter.
As described above, the analog-to-digital converter calibration method and the analog-to-digital converter of the application have the following beneficial effects:
1. according to the analog-to-digital converter calibration method and the analog-to-digital converter, the capacitors at the two input ends of the comparator are respectively switched, so that errors of all side capacitors are counted in single-side error voltages, and then the difference is directly made based on the error voltages at the two sides, so that the offset voltage of the common comparator is eliminated, and the calibration of the DAC capacitor array is realized.
2. The analog-to-digital converter has a simple structure, and the calibration method is simple and convenient, can be effectively applied to the field of analog-to-digital conversion, and effectively improves the precision of the analog-to-digital converter and the digital-to-analog converter.
Drawings
Fig. 1 is a schematic diagram of an analog-to-digital converter according to the present application.
Fig. 2 is a schematic diagram of an analog-to-digital converter calibration method according to the present application.
Fig. 3 is a schematic diagram of step S4 of the analog-to-digital converter calibration method according to the present application.
Fig. 4 shows a schematic measurement of a first DAC capacitive array according to the application.
Description of element reference numerals
1-an analog-to-digital converter; 11-a comparator; 12-a first DAC capacitive array; 13-a second DAC capacitive array; 14-a logic control module; 15-a sample-and-hold module; 16-calibration module.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 1-4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, 2 and 4, the present application provides an analog-to-digital converter calibration method, which is implemented based on the comparator 11, the first DAC capacitor array 12, the second DAC capacitor array 13 and the logic control module 14 shown in fig. 1.
As shown in fig. 1, a first input terminal of the comparator 11 is provided with a first DAC capacitive array 12, and a second input terminal of the comparator 11 is provided with a second DAC capacitive array 13. In this embodiment, the first input terminal is set as the forward input terminal, and the second input terminal is set as the reverse input terminal. In actual measurement, the first input terminal may be set as a reverse input terminal, and the second input terminal may be set as a forward input terminal.
As shown in fig. 1, the first DAC capacitor array 12 and the second DAC capacitor array 13 are respectively provided with n-bit capacitors and n switches, and each capacitor and each switch are respectively provided in a one-to-one correspondence manner; n is an integer of 1 or more. In this embodiment, setting n to 256 corresponds to 256-bit capacitors.
Specifically, first polar plates of each bit capacitor of the first DAC capacitor array 12 are connected to the first input terminal of the comparator 11, and second polar plates are connected to corresponding switches respectively; the first polar plates of the capacitors of each bit of the second DAC capacitor array 13 are connected to the second input terminal of the comparator 11, and the second polar plates are connected to the corresponding switches respectively.
As shown in fig. 1, the output end of the logic control module 14 is connected to each switch in the first DAC capacitor array 12 and the second DAC capacitor array 13, respectively, and is used for switching each switch, so as to control the second plate of each capacitor to be connected to the reference voltage or the reference ground.
Specifically, the logic control module 14 generates a level state control signal and outputs the level state control signal to the control end of each capacitor, so as to control the level state of each capacitor; the logic control module 14 generates a level state control signal to control each capacitor to be connected with the reference voltage V REF Or ground GND. In the present embodiment, based on the reference voltage V REF Setting the logic value of the bit capacitor to be 1, and representing the logic value as a high level state; the logic value of the bit capacitance is set to "0" based on the ground GND, indicating a low state. That is, as shown in fig. 4, setting each capacitor in the capacitor array to "1" or "0" indicates that it is connected to the reference voltage or the reference ground, respectively.
It should be noted that, the circuit structure required by the calibration method of the analog-to-digital converter is not limited by the above structure, and the structure that the positive input end and the negative input end of the comparator are respectively provided with the corresponding bit capacitors can be calibrated by adopting the calibration method of the analog-to-digital converter provided by the application, which is not limited by the embodiment.
The calibration method for the analog-to-digital converter at least comprises the following steps:
s1, connecting second polar plates of n-bit capacitors of the first input end of the comparator 11 with a reference voltage V REF (i.e. set to "1") the second plate of the i bit capacitor at the second input terminal is connected to the reference voltage V REF And (n-i) the second plate of the bit capacitor is connected to the ground GND (i.e., set to "0"), and the output voltage of the comparator 11 is measured as a first measurement voltage V1; all the bit capacitance level states of the second input end are turned over, and the output voltage of the comparator 11 is measured again to be used as a second measurement voltage V2; based on the first measured voltageV1 and the second measurement voltage V2 are subjected to difference calculation to obtain a first error voltage of the second input end; i is an integer of 0 or more and n or less.
Specifically, the positive input terminal and the negative input terminal of the comparator 11 are respectively connected to n-bit capacitors, and capacitors of the same order of the positive input terminal and the negative input terminal are set to the same bit. For example, in the present embodiment, the reverse input terminal of the comparator 11 is first used as the switching terminal to respectively measure the first measurement voltage V1 and the second measurement voltage V2, so that it is necessary to keep the forward input terminal of the comparator connected to "1", that is: each bit capacitor at the positive input end of the comparator 11 is maintained in a high level state, and the negative input end of the comparator 11 is respectively measured twice to obtain a first measurement voltage V1 and a second measurement voltage V2. The first measurement voltage V1 and the second measurement voltage V2 are set to be voltage values measured before and after the bit capacitor is completely flipped, and the complete flipped state of the bit capacitor level at the second input end indicates that the state of each bit capacitor when the first measurement voltage V1 is measured is completely opposite to the state of the bit capacitor level when the second measurement voltage V2 is measured, for example: the positive input terminal of the test comparator 11 has only 5-bit capacitors, so the test "11000" indicates that the first two-bit capacitor is set to a high level, the last three-bit capacitor is set to a low level, the output value of the comparator 11 at this time is measured to obtain the first measurement voltage V1, and the second measurement voltage V2 needs to be measured in a state that the capacitance level states of the respective bits are completely opposite, namely: again, the corresponding second measurement voltage V2 at this time is tested "00111". Under the condition that the high level of the forward input end of the comparator 11 is kept unchanged, voltage values corresponding to two conditions (namely 11000 and 00111 after overturning) of the bit capacitor of the reverse input end are respectively measured, and error values among the capacitors participate in measurement and calculation of error voltages because all the capacitors are overturned at the moment. Therefore, the error voltage of the inverting input capacitor satisfies:
（1）
Δvn is the error voltage of the inverting input capacitor, V1 is the first measurement voltage, and V2 is the second measurement voltage.
S2, connecting the second polar plates of the n-bit capacitors of the second input end of the comparator 11 with the reference voltage V REF The second plate of the i bit capacitor of the first input end is connected with the reference voltage V REF And (n-i) a second plate of the bit capacitor is connected to the ground GND, and the output voltage of the comparator 11 is measured as a third measurement voltage V3; all the bit capacitance level states of the first input end are turned over, and the output voltage of the comparator 11 is measured again to be used as a fourth measurement voltage V4; and calculating a second error voltage of the first input end based on the difference between the third measurement voltage V3 and the fourth measurement voltage V4.
Specifically, if the input terminal measured by the comparator 11 is set to "1" in step S1 and the reverse input terminal is set to "1" in step S2, the forward input terminal is set to "1" in step S2. Meanwhile, in step S2, the bit capacitance corresponding to step S1 is selected for measurement. Such as: if the bit capacitances at the inverting input terminal are measured in step S1 as "11000" and "00111", respectively, then the voltage values of "11000" and "00111" are also measured in step S2, respectively, to obtain the third measurement voltage V3 and the fourth measurement voltage V4, respectively. Therefore, the error voltage of the positive input capacitance satisfies:
（2）
Δvp is the error voltage of the positive input capacitance, V3 is the third measurement voltage, and V4 is the fourth measurement voltage.
And S3, calculating a capacitor array error voltage and the polarity of the capacitor array error voltage based on the difference between the first error voltage and the second error voltage.
Specifically, in this embodiment, the error voltage of the capacitor at the reverse input end is measured as the first error voltage Δvn, the error voltage of the capacitor at the forward input end is measured as the second error voltage Δvp, and the capacitor array error voltage of the analog-to-digital converter 1 is obtained by performing a difference calculation based on the first error voltage Δvn and the second error voltage Δvp.
Further, the principle of obtaining the capacitor array error voltage and the polarity of the analog-to-digital converter 1 in steps S1 to S3 is described as follows:
in each error voltage generation process, only the unilateral capacitor is switched, and the state of the capacitor at the other end is kept unchanged at 1, so that unilateral delta V is obtained, namely errors of all the capacitors are accumulated together and considered as unilateral errors as a whole. The error voltage of the positive input capacitor of the comparator 11 is Δvp and the error voltage of the negative input capacitor is Δvn. The reason for analyzing the single-side error voltage of the comparator 11 is that each bit capacitor has a bit capacitor error; secondly, the offset voltage in the comparator; the positive input of the comparator 11 is inverted to the negative input, and an error voltage value, called offset voltage Vos, is present between the positive and negative inputs.
Therefore, the error voltage Δvp (Δvp=v3-V4) of the positive input capacitor of the comparator 11 includes the sum of the error voltages of each bit capacitor on the positive input, -Vep, and the offset voltage Vos; the error voltage Δvn (Δvn=v1-V2) of the voltage at the inverting input of the comparator 11 includes the sum of the error voltages of each bit capacitor on the inverting input-Ven and the offset voltage Vos. Based on this, equation (1) is further written as:
（3）
where-Ven is the sum of the error voltages of each bit capacitor on the inverting input and Vos is the offset voltage of the comparator.
Equation (2) can be further written as:
（4）
where-Vep is the sum of the error voltages of each bit capacitor on the positive input.
At this time, the capacitance array error voltage of the analog-to-digital converter satisfies:
（5）
where Ve is the capacitor array error voltage of the analog-to-digital converter. In the error voltage generation process, only the single-side capacitor is switched, so that single-side error voltages are obtained, offset voltage Vos of the comparator is contained between the error voltages of the sides, and when the error voltages of the two sides are differenced, the error part generated by the offset voltage Vos of the comparator in the analog-digital converter can be counteracted. It should be noted that, the formula (5) may be the error voltage at any input terminal minus the error voltage at another input terminal, and the polarity of the error voltage is obtained according to the final arithmetic sign of the capacitor array error voltage Ve. For example, if ve= - Δvp+Δvn is positive, that is, the error voltage Δvn at the inverting input terminal subtracts the error voltage Δvp at the forward input terminal, and if the final result is positive, it means that the error voltage Δvn at the inverting input terminal participates in the final capacitor array error voltage Ve, and the polarity of the capacitor array error voltage Ve is negative as a whole.
And S4, providing a calibration voltage with the same magnitude as the capacitor array error voltage Ve to the input end of the comparator 11 with opposite polarity based on the polarity of the capacitor array error voltage Ve, so as to calibrate the voltage error of the analog-to-digital converter.
Specifically, in the present embodiment, as shown in fig. 2, step S4 includes:
and S41, providing a voltage equal to the capacitor array error voltage Ve to a first polarity input end of the comparator 11 (wherein the polarity of the first polarity input end is the same as that of the capacitor array error voltage; the polarity of the second polarity input end is opposite to that of the capacitor array error voltage Ve) based on the polarity of the capacitor array error voltage Ve. If the polarity of the capacitor array error voltage Ve is negative, a voltage equal to the capacitor array error voltage Ve is provided to the inverting input terminal of the comparator 11, so that the capacitor array error voltage Ve can be calibrated directly by the comparator 11.
S42, determining the potential states of the capacitors of the input ends of the comparator 11 with opposite polarities sequentially from the highest capacitor to the lowest capacitor based on a binary search algorithm until the output voltage of the comparator is smaller than a set value, and judging that the first polarity input end and the second polarity input end of the comparator are equal. When the output voltage of the comparator is smaller than the set value, the input voltage of the input end with the same polarity of the comparator 11 is balanced. In this embodiment, the set value is set to a value close to 0, for example, to any value in 0 to 0.1, for example, a value of 0.005, 0.001, etc., the closer it is to 0, the closer it is to indicate that the first polarity input terminal and the second polarity input terminal of the comparator are, and the voltage output by the comparator is determined to be equal to the first polarity input terminal and the second polarity input terminal of the comparator if the voltage output by the comparator is less than the preset value due to the accuracy of the comparator 11.
S43, removing the voltage of the first polarity input end of the comparator 11 to obtain the calibration voltage.
For example, when the polarity of the capacitor array error voltage Ve is negative and the error magnitude is 0.3V, and the DAC capacitor array is calibrated based on the binary search algorithm, a voltage of 0.3V should be input to the inverting input terminal of the comparator 11, and then the bit capacitance of the non-inverting input terminal of the comparator should be adjusted. In this embodiment, if the highest capacitance is "1", it represents an output voltage of 0.5V; if the next highest capacitor is at "1" and represents an output voltage of 0.25V, then the highest capacitor should be at "0", the next highest capacitor should be at "1", and the positive input terminal is equivalent to balancing the voltage of 0.25V at the reverse input terminal, while the error of 0.05V is still not compensated, so that the subsequent lower capacitor needs to be continuously matched based on the binary search algorithm until the error voltage at the reverse input terminal of the comparator 11 is balanced by the positive input terminal of the comparator 11, and the process is not repeated here. When the level state of each bit capacitor at the positive input of the comparator 11 is confirmed, the capacitor array error voltage Ve is calibrated within the limited representation range of the analog-to-digital converter 1, and the voltage initially applied to the negative input of the comparator 11 is removed, so that the analog-to-digital converter 1 is calibrated.
In this embodiment, since the capacitor array error voltage Ve of the analog-to-digital converter has been obtained, the calibration voltage equal to the capacitor array error voltage Ve in magnitude may be provided to the input terminal of the comparator 11 with the opposite polarity directly based on the polarity of the capacitor array error voltage Ve, instead of the calibration by the binary search algorithm. Indeed, other algorithms may be employed to bring the comparator to a calibrated state quickly. In this embodiment, compared to the method of directly providing the calibration voltage to the capacitor array, the binary search algorithm calibration may not require additional circuits to provide the calibration voltage to the capacitor array when the analog-to-digital converter is packaged later.
It should be further noted that, according to the calibration method of the analog-to-digital converter of the present embodiment, the offset voltage Vos of the comparator 11 can be offset only by measuring four voltages, so as to obtain the capacitor array error voltage Ve of the analog-to-digital converter. Compared with other error calibration methods of analog-to-digital converters in the prior art, the method is simple, convenient, high in accuracy and wide in application range.
Specifically, the analog-to-digital converter calibration method further includes:
providing an error voltage to be calibrated to the logic control module 14 based on a table look-up; the logic control module 14 switches the level states of the capacitors of the respective bits at the input ends of the comparator 11 with opposite polarities based on the polarity and the magnitude of the error voltage until a voltage equal to the magnitude of the error voltage is obtained, thereby calibrating the voltage error of the analog-to-digital converter. Wherein the error voltage is set as a temperature error voltage or an input error voltage.
As an example, based on the polarity of the error voltage, a voltage equal to the error voltage is supplied to the input terminal of the same polarity of the comparator 11; the potential states of the capacitors at the input ends of the comparator 11 with opposite polarities are sequentially determined according to the sequence from the highest capacitor to the lowest capacitor based on a binary search algorithm until the input voltages at the two input ends of the comparator are equal when the output voltage of the comparator is smaller than a set value. And removing the input terminal voltages with the same polarity of the comparator, thereby obtaining the calibrated analog-to-digital converter 1.
As an example, a table-storing and recording step is further provided before the temperature error voltage to be calibrated or the input error voltage is provided to the logic control module 14 by a table-look-up method: taking calibration of temperature error voltage as an example, the voltage error memory table of the analog-digital converter 1 tested at different temperatures is recorded in the calibration module 16 in the analog-digital converter, so that when the temperature error voltage of the analog-digital converter is calibrated later, the value of the temperature error corresponding to the current temperature can be found through table lookup, and the temperature error voltage to be calibrated is further provided to the logic control module 14. The input error voltages are the error voltages of the analog-to-digital converter 1 tested under different input voltages, and the specific steps of storing and looking up the table are basically the same as those of the temperature error voltages, and are not repeated here.
It should be noted that, by calibrating either the temperature error voltage or the input error voltage by the binary search algorithm, both factors can be calibrated, and because the capacitor array error voltage Ve is calibrated first, the calibration of the temperature error voltage or the input error voltage of the analog-to-digital converter 1 is performed again on the basis of the calibration, so that the accuracy of the analog-to-digital converter 1 can be greatly improved.
As shown in fig. 1, the present application further provides an analog-to-digital converter 1, configured to implement the above-mentioned analog-to-digital converter calibration method, including: the device comprises a comparator 11, a first DAC capacitor array 12, a second DAC capacitor array 13, a logic control module 14 and a sample hold module 15; the connection relationships of the comparator 11, the first DAC capacitor array 12, the second DAC capacitor array 13, and the logic control module 14 are all described above, and are not described in detail herein, but only the connection relationship of the sample-and-hold module 15 is described further.
Specifically, as shown in fig. 1, the analog-to-digital converter 1 further includes a sample-and-hold module 15. The input end of the sample-hold module 15 is connected with an input voltage, and the output end is connected with the comparator 11, and is used for sampling voltage data and inputting the voltage data into the comparator 11.
As an example, as shown in fig. 1, the sample-and-hold module 15 is provided as two sample-and-hold units; each sample-and-hold unit is connected to two input terminals (respectively receiving a first input voltage vin+ and a second input voltage Vin-) of the comparator 11. In this embodiment, the sample-and-hold unit is provided as a sampling switch. As another example, the sample-and-hold module 15 is provided as a sample-and-hold unit; the positive input end of the comparator 11 is connected with the sample-hold unit, the negative input end is grounded, and the sample-hold unit can also be set as a sampling switch.
It should be noted that, the sample-and-hold module 15 may be configured in other configurations, and any arrangement that can sample the voltage signal and transmit the voltage signal to the comparator 11 is the protection scope of the present embodiment.
As shown in fig. 1, in this embodiment, the analog-to-digital converter further comprises a calibration module 16. The input end of the calibration module 16 is connected to the output end of the comparator 11, and the output end is connected to the logic control module 14, and is used for storing an error voltage (a temperature error voltage and/or an input error voltage) and outputting the error voltage to be calibrated to the logic control module 14, so as to calibrate the analog-to-digital converter 1.
In the present embodiment, the analog-to-digital converter 1 further includes a reference voltage generating unit (not shown) for generating a reference voltage V, a clock signal generating unit (not shown) REF And output to the comparator 11 and the sample-and-hold module 15, respectively, for being used as a reference of voltage to further realize conversion from analog signals to digital signals; the clock signal generating unit is configured to generate a clock signal CLK and output the clock signal CLK to the comparator 11 and the logic control module 14, respectively, for providing timing.
It should be noted that the analog-to-digital converter 1 is not limited to the embodiment, and any analog-to-digital converter 1 having a first DAC capacitor array and a second DAC capacitor array can be calibrated by the analog-to-digital converter calibration method of the present application.
In summary, the present application provides an analog-to-digital converter calibration method and an analog-to-digital converter, including: and respectively measuring a first error voltage and a second error voltage of a forward input end and a reverse input end of the comparator, performing difference calculation based on the first error voltage and the second error voltage to obtain a capacitor array error voltage of the analog-to-digital converter and the polarity of the capacitor array error voltage, and providing a calibration voltage with the same magnitude as the capacitor array error voltage for the input end of the comparator with opposite polarity so as to calibrate the voltage error of the analog-to-digital converter. According to the application, capacitors at two input ends of the comparator are respectively switched, so that errors of all side capacitors are counted in single-side error voltages, and then difference is directly made based on the error voltages at two sides, so that common offset voltage of the comparator is eliminated, and the calibration of the analog-to-digital converter is realized. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A calibration method of an analog-to-digital converter is realized based on a comparator, a first DAC capacitor array, a second DAC capacitor array and a logic control module; the first DAC capacitor array and the second DAC capacitor array are respectively provided with n-bit capacitors and n switches, and the capacitors and the switches are arranged in a one-to-one correspondence manner; n is an integer greater than or equal to 1; the first polar plates of all the capacitors in the first DAC capacitor array are connected with the first input end of the comparator, and the second polar plates are respectively connected with the corresponding switches; the first polar plates of all the bit capacitors of the second DAC capacitor array are connected with the second input end of the comparator, and the second polar plates are respectively connected with the corresponding switches; the output end of the logic control module is respectively connected with each switch in the first DAC capacitor array and the second DAC capacitor array and is used for switching each switch so as to control the second pole plate of each capacitor to be connected with reference voltage or reference ground; the method is characterized in that: the analog-to-digital converter calibration method at least comprises the following steps:
s1, connecting second polar plates of n-bit capacitors of a first input end of a comparator with the reference voltage, connecting a second polar plate of i-bit capacitors of a second input end with the reference voltage, and connecting a second polar plate of (n-i) bit capacitors with the reference ground, and measuring the output voltage of the comparator as a first measurement voltage; all the bit capacitance level states of the second input end are overturned, and the output voltage of the comparator is measured again to be used as a second measurement voltage; calculating a first error voltage of the second input end based on the difference between the first measurement voltage and the second measurement voltage; i is an integer of 0 or more and n or less;
s2, connecting second polar plates of n-bit capacitors of a second input end of the comparator with the reference voltage, connecting a second polar plate of i-bit capacitors of a first input end with the reference voltage, and connecting a second polar plate of (n-i) bit capacitors with the reference ground, and measuring the output voltage of the comparator as a third measurement voltage; all the bit capacitance level states of the first input end are turned over, and the output voltage of the comparator is measured again to be used as a fourth measurement voltage; calculating a second error voltage of the first input end based on the difference between the third measurement voltage and the fourth measurement voltage;
s3, calculating a capacitance array error voltage of the analog-to-digital converter and the polarity of the capacitance array error voltage based on the difference between the first error voltage and the second error voltage;
and S4, providing a calibration voltage with the same magnitude as the capacitor array error voltage to the input end of the comparator with opposite polarity based on the polarity of the capacitor array error voltage, so as to calibrate the voltage error of the analog-to-digital converter.
2. The analog-to-digital converter calibration method of claim 1, wherein: the step S4 includes:
s41, providing a voltage with the same size as the capacitor array error voltage to a first polarity input end of the comparator based on the polarity of the capacitor array error voltage;
s42, sequentially determining potential states of all the capacitors at the second polarity input end of the comparator according to the sequence from the highest capacitor to the lowest capacitor based on a binary search algorithm until the output voltage of the comparator is smaller than a set value, and judging that the first polarity input end of the comparator is equal to the second polarity input end;
s43, removing the voltage of the first polarity input end of the comparator, and further obtaining a calibrated analog-digital converter;
the polarity of the first polarity input end is the same as the polarity of the capacitor array error voltage; the polarity of the second polarity input is opposite to the polarity of the capacitor array error voltage.
3. The analog-to-digital converter calibration method of claim 1, wherein: the analog-to-digital converter calibration method further comprises the following steps:
providing an error voltage to be calibrated for the logic control module based on a table look-up mode;
the logic control module switches the level state of each bit capacitor at the input end of the opposite polarity of the comparator based on the polarity and the magnitude of the error voltage until the voltage equal to the error voltage is obtained, so as to calibrate the voltage error of the analog-to-digital converter;
wherein the error voltage is set as a temperature error voltage or an input error voltage.
4. A method of calibrating an analog to digital converter according to claim 3, characterized in that:
providing a voltage with the same polarity as the error voltage to an input end of the comparator based on the polarity of the error voltage to be calibrated;
sequentially determining potential states of all bit capacitors of the input ends of the comparator with opposite polarities according to the sequence from the highest bit capacitor to the lowest bit capacitor based on a binary search algorithm until the output voltage of the comparator is smaller than a set value, and judging that the input voltages of the two input ends of the comparator are equal;
and removing the input terminal voltages with the same polarity of the comparator, thereby obtaining the calibrated analog-to-digital converter.
5. An analog-to-digital converter for implementing the calibration method of an analog-to-digital converter according to any one of claims 1 to 4, characterized in that: the analog-to-digital converter comprises a comparator, a first DAC capacitor array, a second DAC capacitor array, a logic control module and a sampling and holding module;
the first DAC capacitor array and the second DAC capacitor array are respectively provided with n-bit capacitors and n switches, and the capacitors and the switches are arranged in a one-to-one correspondence manner; n is an integer greater than or equal to 1;
the first polar plates of all the capacitors in the first DAC capacitor array are connected with the first input end of the comparator, and the second polar plates are respectively connected with the corresponding switches; the first polar plates of all the bit capacitors of the second DAC capacitor array are connected with the second input end of the comparator, and the second polar plates are respectively connected with the corresponding switches;
the output end of the logic control module is respectively connected with each switch in the first DAC capacitor array and the second DAC capacitor array and is used for switching each switch so as to control the second pole plate of each capacitor to be connected with reference voltage or reference ground;
and the input end of the sampling and holding module is connected with the input voltage, and the output end of the sampling and holding module is connected with the comparator and is used for sampling voltage data and inputting the voltage data into the comparator.
6. The analog-to-digital converter of claim 5, wherein: the sample and hold module is arranged as two sample and hold units; each sample hold unit is connected with two input ends of the comparator respectively.
7. The analog-to-digital converter of claim 5, wherein: the sample and hold module is set as a sample and hold unit; and the positive input end of the comparator is connected with the sampling and holding unit, and the negative input end of the comparator is grounded.
8. An analog-to-digital converter according to claim 6 or 7, characterized in that: the sample and hold unit is provided as a sampling switch.
9. The analog-to-digital converter of claim 5, wherein: the analog-to-digital converter further comprises a calibration module; the input end of the calibration module is connected with the output end of the comparator, and the output end of the calibration module is connected with the logic control module and is used for storing error voltage and providing the error voltage to be calibrated to the logic control module so as to calibrate the analog-to-digital converter.
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