TWI441456B - Can reduce the energy consumption of the successive approximation of the temporary analog-to-digital converter - Google Patents

Description

Successive approximation temporary storage analog converter for reducing energy consumption

The present invention relates to a successive approximation temporary analog analog-to-digital converter, and more particularly to a successive approximation temporary analog analog-to-digital converter that minimizes energy loss.

With the booming of portable electronic products, low power consumption, which extends battery life, has become a trend in electronics. Among the many analog-to-digital converters, the successive approximation register analog-to-digital converter (SAR ADC) has the advantage of power saving - its analog-to-digital conversion requires only one comparator, and the architecture is simple. The number of components is small, so it has been widely used in electronic products.

Please refer to FIG. 1 , which is a block diagram of a conventional N-bit SAR ADC. As shown in FIG. 1, the SAR ADC includes a bit value decision unit 100 and a successive approximation register 140, wherein the bit value decision unit 100 includes a sample hold circuit 110 and a digital analog conversion circuit 120. And a comparator 130.

The sample and hold circuit 110 is operative to sample and hold an analog input signal V _A during a sampling phase to generate a sample signal V _A1 .

The digital analog conversion circuit 120 is configured to generate a quantized voltage V _A2 according to a plurality of switching control signals SW _N to SW ₁ under a bias voltage of a reference voltage V _REF and a ground voltage V _GND .

The comparator 130 is configured to compare the voltage of the sampling signal V _A1 with the quantized voltage V _A2 to generate a one-bit output value B.

The successive approximation register 140 is configured to sequentially change the contents of the switch control signals SW _N ~SW ₁ to change the quantization voltage V _A2 in a voltage comparison phase, and sequentially read the bit output value B to generate a digital output code D _OUT .

When in the voltage comparison phase, first, the successive approximation register 140 outputs a set of prediction numbers through the switch control signals SW _N ~SW ₁ , usually by making the maximum bit (MSB) 1 to log-to-digital analog conversion. The circuit 120 is charged and discharged to generate a corresponding level of the quantized voltage V _A2 . Next, the comparator 130 compares the voltage between the sampled signal V _A1 and the quantized voltage V _A2 to determine the content of the bit output value B - which is 0 or 1. Then, the successive approximation register 140 stores the bit output value B in a temporary register, and outputs the next set of prediction numbers according to the content of the bit output value B to determine the content of the next bit. By repeating N times in this manner, the N-bit digital output code D _{OUT of the} sampled signal V _A1 can be generated.

In the process of generating the digital output code D _OUT , the quantized voltage V _A2 generated by the digital analog conversion circuit 120 is gradually approached to the sampling signal V _{A1 in a} binary-weighted manner. That is, the N-bit SAR ADC generates N different quantized voltages V _A2 , if V _A2(1) , V _A2(2) , V _A2(3) , ..., V _{A2(N) respectively} For the value, the voltage difference between V _A2(K) and V _A2(K-1) will be equal to half the voltage difference between V _A2(K-1) and V _A2(K-2) , where k=3~N.

Since the digital analog conversion circuit 120 charges and discharges the capacitors of different weights through the switching of the switches, most of the energy loss occurs during the switching process.

For a circuit architecture of a general digital analog conversion circuit, please refer to FIG. 2, which illustrates a block diagram of a conventional bit value decision unit including a digital analog conversion circuit. As shown in FIG. 2, the conventional bit value determining unit includes a switching unit 210, a digital analog conversion circuit 220, and a comparator 230. The digital analog conversion circuit 220 has a first capacitor array 221 and a second. A capacitor array 222, a voltage selection circuit 223, and a voltage selection circuit 224.

The switch unit 210 has a pair of sampling switches, one side of which has a first contact and a second contact, respectively coupled to a reference voltage V _REF , and the other side has a third contact and a fourth contact The first capacitor array 221 and the second capacitor array 222 are coupled respectively.

The first capacitor array 221 and the second capacitor array 222 each have N+1 capacitors, and their capacitance values are C, C, 2C, 4C, 8C, ..., 2 ^N-1 C, respectively. The N+1 capacitors of the first capacitor array 221 have a common contact to couple the third contact of the switch unit 210, and N+1 bias contacts to couple the voltage selection circuit 223. The N+1 capacitors of the second capacitor array 222 have a common contact to couple the fourth contact of the switch unit 210, and N+1 bias contacts to couple the voltage selection circuit 224.

The voltage selection circuit 223 is configured to output N+1 bias voltages to the N+1 bias contacts of the first capacitor array 221 according to the switch control signals SW _N SWSW ₁ , wherein the voltage selection circuit 223 outputs Each of the bias voltages is derived from a negative analog input voltage V _AN , the reference voltage V _REF , or a ground voltage V _GND . The selection circuit 224 is configured to output N+1 bias voltages to the N+1 bias contacts of the second capacitor array 222 according to the switch control signals SW _N ~SW ₁ , wherein the voltage selection circuit 224 outputs Each of the bias voltages is derived from a positive analog input voltage V _AP , the reference voltage V _REF , or a ground voltage V _GND .

The comparator 230 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is coupled to the third contact of the switch unit 210, and the negative input terminal is coupled to the switch unit 210. The fourth contact is coupled. The comparator 230 is configured to use a voltage difference between the positive input terminal and the negative input terminal - the value can be expressed as V _AP -V _AN -γV _REF , 0 ≦ γ<1 - generating a one-element output value B . When V _AP -V _AN -γV _REF >0, B=1; when V _AP -V _AN -γV _REF <0, B=0.

Please refer to FIG. 3, which illustrates the circuit configuration of the conventional bit value determining unit of FIG. 2 in a sampling phase. As shown in FIG. 3, when in the sampling phase, the common contacts of the first capacitor array 221 and the second capacitor array 222 are coupled to V _REF , and the N+1 bias terminals of the first capacitor array 221 are connected. The points are both coupled to the negative analog input voltage V _AN , and the N+1 bias contacts of the second capacitor array 222 are coupled to the positive analog input voltage V _AP . Before the end of the sampling phase, the first capacitor array 221 stores a voltage of (V _REF - V _AN ), and the second capacitor array 222 stores a voltage of (V _REF - V _AP ).

Please refer to FIG. 4, which illustrates the circuit configuration of the conventional bit value determining unit of FIG. 2 in a voltage comparison phase. As shown in FIG. 4, when in the voltage comparison phase, the switching unit 210 is in an off state; the first capacitor array 221 has a first equivalent capacitance with a capacitance of KC and a capacitance of (2 ^N - K) the second equivalent capacitance of C; and the second capacitor array 222 has a third equivalent capacitance of capacitance KC and a fourth equivalent capacitance of capacitance (2 ^N -K) C, where K, N A positive integer, K=1~2 ^N -1, and the biasing contact of the first equivalent capacitor is coupled to V _REF , and the bias contact of the second equivalent capacitor is coupled to V _GND , a bias contact of the third equivalent capacitor is coupled to V _GND , and a bias contact of the fourth equivalent capacitor is coupled to V _REF .

During the voltage comparison phase, the positive input of comparator 230 exhibits a voltage of V _REF -V _AN +(K/2 ^N )V _REF , and the negative input presents V _REF -V _AP +(1-K/ The voltage of 2 ^N )V _REF , that is, the voltage difference between V _AP -V _AN -(1-K/2 ^N-1 )V _REF between the positive input terminal and the negative input terminal of the comparator 230. Taking N=4 as an example, when K=1, the voltage difference is equal to V _AP -V _AN -(7/8)V _REF ; when K=2, the voltage difference is equal to V _AP -V _AN -(3/ 4) V _REF ; when K=3, the voltage difference is equal to V _AP -V _AN -(5/8)V _REF ; when K=4, the voltage difference is equal to V _AP -V _AN -(1/2) V _REF ; when K=5, the voltage difference is equal to V _AP -V _AN -(3/8)V _REF ; when K=6, the voltage difference is equal to V _AP -V _AN -(1/4)V _REF When K=7, the voltage difference is equal to V _AP -V _AN -(1/8)V _REF ; when K=8, the voltage difference is equal to V _AP -V _AN -0; when K=9, the The voltage difference is equal to V _AP -V _AN -(-1/8)V _REF ; when K=10, the voltage difference is equal to V _AP -V _AN -(-1/4)V _REF ; when K=11, the The voltage difference is equal to V _AP -V _AN -(-3/8)V _REF ; when K=12, the voltage difference is equal to V _AP -V _AN -(-1/2)V _REF ; when K=13, the The voltage difference is equal to V _AP -V _AN -(-5/8)V _REF ; when K=14, the voltage difference is equal to V _AP -V _AN -(-3/4)V _REF ; when K=15, the The voltage difference is equal to V _AP -V _AN -(-7/8)V _REF . In the voltage comparison phase, the K value is first set to 8 to compare V _AP -V _AN with zero volts. If V _AP -V _{AN is} greater than zero volts, then the K value will be changed to 4 to make V _AP -V _{AN is} compared with (1/2)V _REF . If V _AP -V _{AN is} less than (1/2)V _REF , then the K value will be changed to 6 to make V _AP -V _AN and (1 /4) V _REF is compared, and so on. When K=8, (first equivalent capacitor, second equivalent capacitor) will form a combination of (8C, 8C); when K=4, ( The first equivalent capacitor, the second equivalent capacitor) forms a combination of (4C, 12C); when K=6, the (first equivalent capacitor, the second equivalent capacitor) forms a combination of (6C, 10C) .

Therefore, assuming V _AP -V _AN =(9/32)V _REF , at the beginning K = 8, since (9/32)V _REF -0 is greater than zero volts, comparator 230 outputs 1 and then K Will be changed to 4; at K=4, since (9/32)V _REF -(1/2)V _{REF is} less than zero volts, comparator 230 outputs 0, and then K is changed to 6; When =6, since (9/32)V _REF -(1/4)V _{REF is} greater than zero volts, comparator 230 outputs 1 and then K is changed to 5; at K=5, due to (9/ 32) V _REF -(3/8)V _{REF is} less than zero volts, so comparator 230 outputs zero. Accordingly, a digital output (1010) of (9/32) V _REF can be generated.

In addition, since the N-bit SAR ADC has N dynamic energy losses during the generation of each N-bit number, the dynamic energy loss is equal to the product of the reference voltage V _REF and the amount of electricity flowing from the reference voltage V _REF . Therefore, how to reduce the amount of power flowing out of the reference voltage V _REF has become the key to reduce the dynamic energy loss of the SAR analog-to-digital conversion given the reference voltage V _REF . According to the above-mentioned structure of the SAR ADC, the dynamic energy loss can only be reduced by reducing the basic capacitance value C. However, reducing the basic capacitance value C degrades the Signal to Noise Ratio (SNR), thereby affecting the analog digital conversion accuracy of the SAR ADC.

In view of the foregoing problems, we need a novel SAR analog-to-digital conversion architecture to reduce dynamic energy consumption without affecting SNR.

It is an object of the present invention to provide a successive approximation temporary analog digital converter that minimizes energy consumption, and has a novel capacitor array architecture in which the maximum capacitance of the capacitor array is 2 ^N of its minimum capacitance value. ^-2 times, where N is the number of digit output bits of the analog to digital converter.

Another object of the present invention is to provide a successive approximation temporary analog digital converter capable of minimizing energy consumption, which adopts a novel input voltage sampling mode and a novel voltage comparison mode to reduce dynamic energy consumption, wherein The novel voltage comparison mode allows most of the capacitors contained in the two capacitor arrays to have floating options.

It is still another object of the present invention to provide a successive approximation temporary analog digital converter that minimizes energy consumption, using a novel input voltage sampling mode and a novel voltage comparison mode to reduce dynamic energy consumption, wherein Both the novel input voltage sampling mode and the novel voltage comparison mode use a common mode voltage between a reference voltage and a ground voltage.

In order to achieve the foregoing object, the present invention provides a successive approximation temporary analog digital converter capable of reducing energy consumption, comprising: a comparator having a positive input terminal, a negative input terminal, and a comparison output terminal; a capacitor circuit having a first capacitor array and a second capacitor array, the first capacitor array and the second capacitor array each having N sets of capacitors, in the N sets of capacitors: the first group and the second group It has one capacitor and its capacitance is C; the third group has one capacitor and its capacitance is 2C; the Kth group has K-2 capacitors, and its capacitance is 2C, 2 ¹ C, 2 ² C, ... 2 ^K3 C, K=4~N, wherein each capacitor included in the first capacitor array is coupled to the positive input terminal of the comparator by an electrode, and the capacitors included in the second capacitor array Each of the two sides is coupled to the negative input terminal of the comparator; a pair of sampling switches having one side coupled to a positive input voltage and a negative input voltage, and the other side coupled to the comparison The positive input terminal and the negative input terminal; a logic circuit having a one-bit output value An input terminal, N bit output terminals, and a plurality of switch control output terminals, wherein the bit output value input end is coupled to the comparison output end of the comparator, and the switch control output end is used And outputting a plurality of switch control signals; and a voltage selection circuit for causing the other electrode of each capacitor included in the capacitor circuit to be in a floating state or connected to a reference voltage, a common mode voltage, or A ground voltage.

The detailed description of the drawings and the preferred embodiments are set forth in the accompanying drawings.

Referring to FIG. 5, a block diagram of a preferred embodiment of a successive approximation temporary analog digital converter capable of reducing energy consumption is illustrated. As shown in FIG. 5, the analog-to-digital converter includes a switch unit 510, a first capacitor array 521, a second capacitor array 522, a voltage selection circuit 523, a comparator 530, and a logic circuit 540, wherein the switch The unit 510, the first capacitor array 521, the second capacitor array 522, the voltage selection circuit 523, and the comparator 530 are used to form a one-bit value decision unit.

The switch unit 510 has a pair of sampling switches, one side of which has a first contact and a second contact, respectively coupled to a positive analog input voltage V _AP and a negative analog input voltage V _AN , and the other side has a The third contact and the fourth contact are respectively coupled to the first capacitor array 521 and the second capacitor array 522.

The first capacitor array 521 and the second capacitor array 522 each have N sets of capacitors. Among the N sets of capacitors, the first group and the second group each have one capacitor, and the capacitance is C; the third group has one. The capacitance has a capacitance of 2C; the Kth group has K-2 capacitors, and the capacitances thereof are 2C, 2 ¹ C, 2 ² C, ... 2 ^K-3 C, K=4~N, wherein the capacitor Each of the capacitors of the capacitor array 521 is coupled to the third contact of the switch unit 510 by an electrode, and the other electrode of each capacitor is a bias contact, and each of the bias contacts is coupled Connected to bias signals V _U (1), V _U (2), V _U (3), V _U (4,1), V _U (4,2), V _U (5,1), V _U ( 5,2), V _U (5,3)..., V _U (N,1), V _U (N,2),...V _U (N,N-3), V _U (N,N- 2); each capacitor of the second capacitor array is coupled to the fourth contact of the switch unit 510 by an electrode, and the other electrode of each capacitor is a bias contact, each of the bias The contacts are respectively coupled to the bias signals V _D (1), V _D (2), V _D (3), V _D (4, 1), V _D (4, 2), V _D (5, 1) , V _D (5, 2), V _D (5, 3)..., V _D (N, 1), V _D (N, 2), ... V _D (N, N-3), V _D (N, N-2).

The voltage selection circuit 523 is configured to output the bias signals V _U (1), V _U (2), V _U (3), V _U (4, 1), V _U (4) according to the switch control signals SW _N ~ SW _{1 .} , 2), V _U (5,1), V _U (5,2), V _U (5,3)..., V _U (N,1), V _U (N,2),...V _U (N , N-3), V _U (N, N-2) to the bias contact of the first capacitor array 521, and output bias signals V _D (1), V _D (2), V _D (3 ), V _D (4,1), V _D (4,2), V _D (5,1), V _D (5,2), V _D (5,3)..., V _D (N,1) V _D (N, 2), ... V _D (N, N-3), V _D (N, N-2) are applied to the bias contact of the second capacitor array 522 to make the first capacitor array 521 Each of the bias contacts of the second capacitor array 522 is in a floating state or connected to a reference voltage V _REF , a common mode voltage V _CM , or a ground voltage V _GND . Wherein, the common mode voltage V _{CM is} lower than the reference voltage V _REF and higher than the ground voltage V _GND , and the preferred voltage value is V _REF /2.

The comparator 530 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is coupled to the third contact of the switch unit 510, and the negative input terminal is coupled to the switch unit 510. The fourth contact is coupled. The comparator 530 is configured to generate a one-bit output value B according to a voltage difference between the positive input terminal and the negative input terminal.

The logic circuit 540 has a one-bit output value input terminal, N bit output terminals, and a plurality of switch control output terminals, wherein the bit output value input terminal is coupled to the comparison output terminal of the comparator 530. The N bit outputs are used to output a digital D _OUT , and the switch control output is used to output the switch control signals SW _N ~SW ₁ . The logic circuit 540 includes a register to temporarily store the digital D _OUT .

Please refer to FIG. 6 , which illustrates the circuit configuration of the bit value determining unit of FIG. 5 in a sampling phase. As shown in FIG. 6, when in the sampling phase, the common contacts of the first capacitor array 521 and the second capacitor array 522 are coupled to V _AP and V _AN , respectively, the first capacitor array 521 and the second capacitor array. A plurality of bias contacts of 522 are coupled to a common mode voltage V _CM . Before the end of the sampling phase, the first capacitor array 521 stores a voltage of (V _AP -V _CM ), the second capacitor array 522 stores a voltage of (V _AN -V _CM ), and the comparator 530 is positive. There is a voltage difference between V _AP -V _AN -0 between the input and the negative input.

When the bit value determining unit of FIG. 5 is in a voltage comparison phase, if V _AP -V _AN >0, it is V _AP -V _AN and ((2m-1) in a first circuit configuration. /2 ⁿ )V _REF voltage comparison; if V _AP -V _AN <0, it is a voltage of V _AP -V _AN and ((1-2m)/2 ⁿ )V _REF in a second circuit configuration In comparison, m and n are positive integers, m≦2 ^n-1 , n≦N-1.

Please refer to FIG. 7(a), which is a schematic diagram of the first circuit configuration. As shown in FIG. 7(a), when the bit value determining unit forms the first circuit configuration, the switching unit 510 is in a disconnected state; the first capacitor array 521 has a capacitance of (2m-). 1) The first equivalent capacitance of C, the second equivalent capacitance of (2 ⁿ -2m+1)C, and the third equivalent capacitance of (2 ^N-1 -2 ⁿ )C; The second capacitor array 522 has a fourth equivalent capacitance of (2m-1)C, a fifth equivalent capacitance of (2 ⁿ -2m+1)C, and a capacitance of (2 ^N- The sixth equivalent capacitance of ¹ -2 ⁿ )C. The biasing contact of the first equivalent capacitor is coupled to V _GND , the biasing contact of the second equivalent capacitor is coupled to V _CM , and the biasing contact of the third equivalent capacitor Is in a floating state, the biasing contact of the fourth equivalent capacitor is coupled to V _REF , the biasing contact of the fifth equivalent capacitor is coupled to V _CM , and the sixth The bias contact of the capacitor is floating.

In the first circuit configuration, the positive input of comparator 530 will present a voltage of V _AP -((2m-1)/2 ⁿ )V _CM , and the negative input will present V _AN +((2m- 1) / 2 ⁿ ) (V _REF - V _CM ), that is, there will be V _AP -V _AN -((2m-1)/2 ⁿ )V between the positive input terminal and the negative input terminal of the comparator 530 The voltage difference of _REF . Taking N=4 as an example, when (n, m) = (1, 1), the voltage difference is equal to V _AP -V _AN -(1/2)V _REF ; when (n,m)=(2,1 When the voltage difference is equal to V _AP -V _AN -(1/4)V _REF ; when (n,m)=(2,2), the voltage difference is equal to V _AP -V _AN -(3/4) V _REF ; when (n,m)=(3,1), the voltage difference is equal to V _AP -V _AN -(1/8)V _REF ; when (n,m)=(3,2), The voltage difference is equal to V _AP -V _AN -(3/8)V _REF ; when (n,m)=(3,3), the voltage difference is equal to V _AP -V _AN -(5/8)V _REF ; When (n, m) = (3, 4), the voltage difference is equal to V _AP -V _AN -(7/8)V _REF .

Please refer to FIG. 7(b), which is a schematic diagram of the second circuit configuration. As shown in FIG. 7(b), when the bit value determining unit forms the second circuit configuration, the switching unit 510 is in a disconnected state; the first capacitor array 521 has a capacitance of (2m-). 1) The first equivalent capacitance of C, the second equivalent capacitance of (2 ⁿ -2m+1)C, and the third equivalent capacitance of (2 ^N-1 -2 ⁿ )C; The second capacitor array 522 has a fourth equivalent capacitance of (2m-1)C, a fifth equivalent capacitance of (2 ⁿ -2m+1)C, and a capacitance of (2 ^N- The sixth equivalent capacitance of ¹ -2 ⁿ )C. The biasing contact of the first equivalent capacitor is coupled to V _REF , the biasing contact of the second equivalent capacitor is coupled to V _CM , and the biasing contact of the third equivalent capacitor Is in a floating state, the biasing contact of the fourth equivalent capacitor is coupled to V _GND , the biasing contact of the fifth equivalent capacitor is coupled to V _CM , and the sixth The bias contact of the capacitor is floating.

In the second circuit configuration, the positive input of comparator 530 will present a voltage of V _AP +((2m-1)/2 ⁿ )(V _REF -V _CM ), and the negative input will present V _AN -((2m-1)/2 ⁿ )V _CM voltage, that is, there will be V _AP -V _AN -((1-2m)/2 ⁿ )V between the positive input terminal and the negative input terminal of the comparator 530 The voltage difference of _REF . Taking N=4 as an example, when (n, m) = (1, 1), the voltage difference is equal to V _AP -V _AN -(-1/2)V _REF ; when (n,m)=(2, 1), the voltage difference is equal to V _AP -V _AN -(-1/4)V _REF ; when (n,m)=(2,2), the voltage difference is equal to V _AP -V _AN -(-3 /4)V _REF ; when (n,m)=(3,1), the voltage difference is equal to V _AP -V _AN -(-1/8)V _REF ; when (n,m)=(3,2 When the voltage difference is equal to V _AP -V _AN -(-3/8)V _REF ; when (n,m)=(3,3), the voltage difference is equal to V _AP -V _AN -(-5/ 8) V _REF ; when (n, m) = (3, 4), the voltage difference is equal to V _AP -V _AN -(-7/8)V _REF .

In the voltage comparison phase, if V _AP -V _AN >0, then (n,m) will be sequentially set so that V _AP -V _{AN is} first compared with (1/2)V _REFF , then with ( 1/4) V _REF or (3/4) V _REF for comparison, then with (1/8) V _REF or (3/8) V _REF or (5/8) V _REF or (7/8) V _REF is compared. If V _AP -V _AN <0, then (n,m) will be set sequentially so that V _AP -V _{AN is} first compared with (-1/2)V _REFF , followed by (-1/4)V _REF Or (-3/4)V _REF for comparison, then with (-1/8)V _REF or (-3/8)V _REF or (-5/8)V _REF or (-7/8)V _REF comparing.

Therefore, assuming V _AP -V _AN =(9/32)V _REF , since (9/32)V _{REF is} greater than zero volts, comparator 530 outputs 1 and then (n,m) is set to (1, 1); at (n, m) = (1, 1), since (9/32) V _REF - (1/2) V _{REF is} less than zero volts, comparator 530 outputs 0, and then (n, m) ) will be set to (2,1); at (n,m)=(2,1), since (9/32)V _REF -(1/4)V _{REF is} greater than zero volts, comparator 530 outputs 1, and then (n, m) will be set to (3, 2); when (n, m) = (3, 2), because (9/32) V _REF - (3 / 8) V _{REF is} less than Zero volt, so comparator 530 outputs 0, where (n, m) = (1, 1), (first equivalent capacitance, second equivalent capacitance) will form a combination of (C, C); (n, m) = (2, 1), (first equivalent capacitance, second equivalent capacitance) will form a combination of (C, 3C); and when (n, m) = (3, 2) , (the first equivalent capacitor, the second equivalent capacitor) will form a combination of (3C, 8C). Accordingly, the corresponding digital output (1010) of (9/32) V _REF can be generated.

So far, the present invention has disclosed in detail a SAR ADC which can reduce energy loss, and the difference from the conventional one is as follows:

1. Compared with the capacitance value of the maximum capacitance of the conventional SAR ADC (2 ^N-1 C), the capacitance value of the maximum capacitance of the present invention (2 ^N-3 C) is only a quarter of the conventional one; According to the total capacitance value (2×2 ^N C) of the conventional SAR ADC, the total capacitance value (2×2 ^N-1 C) of the present invention is only one-half of the conventional one, so the invention can greatly reduce the wafer area. .

2. The conventional SAR ADC architecture first performs a voltage comparison operation with its largest capacitance, whereas the present invention first performs the voltage comparison operation with its minimum capacitance. Since there are several voltage comparison operations (such as comparison of analog input voltage with ±(1/2)V _REF and ±(1/4)V _REF ) before the SAR analog digital conversion process, there will be a large voltage fluctuation range. Therefore, the present invention first performs the voltage comparison operation with a minimum capacitance to greatly reduce the amount of power flowing out of the reference voltage V _REF , thereby greatly reducing the energy consumption.

3. The conventional SAR ADC architecture uses all of the capacitances during the voltage comparison operation described above, while the present invention allows portions of the capacitors to be floated to further reduce energy losses.

4. Compared to a conventional SAR ADC using a reference voltage V _REF and a ground voltage to define a biasing range of -V _REF to V _REF , the present invention is at the reference voltage V _REF and the ground voltage A bias design that adds a common-mode voltage to define a comparison range of -V _REF to V _REF can reduce the voltage across a capacitor circuit, helping to further reduce energy losses.

It is derived that the average energy consumption of a conventional N-bit SAR ADC is:

Taking N=10 as an example, the average energy consumption is 1363.33 CV _REF ² ; and the average energy consumption of the present invention is:

Taking N=10 as an example, the average energy consumption is 31.88 CV _REF ² , which can save 97.66% of energy compared with the conventional architecture.

The disclosure of the present invention is a preferred embodiment. Any change or modification of the present invention originating from the technical idea of the present invention and being easily inferred by those skilled in the art will not deviate from the scope of patent rights of the present invention.

In summary, this case, regardless of its purpose, means and efficacy, is showing its technical characteristics that are different from the conventional ones, and its first invention is practical and practical, and it is also in compliance with the patent requirements of the invention. I will be granted a patent at an early date.

100. . . Bit value decision unit

110. . . Sample and hold circuit

120. . . Digital analog conversion circuit

130, 230, 530. . . Comparators

140. . . Successive approximation register

210, 510. . . Switch unit

220. . . Digital analog conversion circuit

221, 521. . . First capacitor array

222, 522. . . Second capacitor array

223, 224, 523. . . Voltage selection circuit

540. . . Logic circuit

1 is a block diagram of a conventional N-bit SAR ADC.

2 is a block diagram of a conventional bit value decision unit including a digital analog conversion circuit.

3 is a circuit diagram of the conventional bit value determining unit of FIG. 2 in a sampling phase.

4 is a circuit configuration of the conventional bit value determining unit of FIG. 2 in a voltage comparison phase.

FIG. 5 is a block diagram showing a preferred embodiment of a successive approximation temporary analog digital converter capable of reducing energy consumption according to the present invention.

6 is a circuit diagram of the bit value determining unit of FIG. 5 in a sampling phase.

FIG. 7(a) illustrates a first circuit configuration of the bit value determining unit of FIG. 5 in a voltage comparison phase.

FIG. 7(b) illustrates a second circuit configuration of the bit value determining unit of FIG. 5 in a voltage comparison phase.

530. . . Comparators

510. . . Switch unit

521. . . First capacitor array

522. . . Second capacitor array

523. . . Voltage selection circuit

540. . . Logic circuit

Claims (7)

A successive approximation temporary analog analog-to-digital converter capable of reducing energy consumption, comprising: a comparator having a positive input terminal, a negative input terminal, and a comparison output terminal; a capacitor circuit having a first capacitor An array and a second capacitor array, the first capacitor array and the second capacitor array each having N sets of capacitors. In the N sets of capacitors, the first group and the second group each have a capacitor, and the capacitance is C. The third group has one capacitor and its capacitance is 2C; the Kth group has K-2 capacitors, and its capacitance is 2C, 2 ¹ C, 2 ² C, ... 2 ^K-3 C, K=4 ~N, wherein each capacitor included in the first capacitor array is coupled to the positive input terminal of the comparator by an electrode, and each capacitor included in the second capacitor array is coupled to the capacitor by an electrode a negative input terminal of the comparator; a pair of sampling switches, one side of which is coupled to a positive input voltage and a negative input voltage, and the other side of which is coupled to the positive input terminal of the comparator and The negative input terminal; a logic circuit having a one-bit output value input terminal, N bit output terminals, and a complex a switch control output terminal, wherein the bit output value input end is coupled to the comparison output end of the comparator, and the switch control output end is configured to output a plurality of switch control signals; and a voltage selection And a circuit for causing another electrode of each capacitor included in the capacitor circuit to be in a floating state or connected to a reference voltage, a common mode voltage, or a ground voltage according to the switch control signal. A successive approximation temporary analog digital converter capable of reducing energy consumption as described in claim 1 wherein the logic circuit further has a register. A successive approximation temporary analog analog-to-digital converter capable of reducing energy consumption as described in claim 1 wherein the common mode voltage is lower than the reference voltage and higher than the ground voltage. A successive approximation temporary analog analog-to-digital converter capable of reducing energy consumption, comprising: a comparator having a positive input terminal, a negative input terminal, and a comparison output terminal; a capacitor circuit having a first capacitor An array and a second capacitor array; a pair of sampling switches, one side of which is coupled to a positive input voltage and a negative input voltage, and the other side of which is coupled to the positive input end of the comparator a negative input terminal; a logic circuit having a one-bit output value input terminal, N bit output terminals, and a plurality of switch control output terminals, wherein the bit output value input terminal is associated with the comparator The comparison output is coupled, and the switch control output is configured to output a plurality of switch control signals; and a voltage selection circuit is configured to perform the following operations according to the switch control signal: planning the first capacitor array to Providing a first equivalent capacitor having a capacitance of (2m-1)C and a second equivalent capacitor having a capacitance of (2 ⁿ -2m+1)C, wherein one of the first equivalent capacitors is Coupled with the positive input of the comparator And the other electrode is coupled to a reference voltage or a ground voltage, and one of the second equivalent capacitors is coupled to the positive input terminal of the comparator, and the other electrode is coupled To a common mode voltage; and planning the second capacitor array to provide a fourth equivalent capacitance having a capacitance of (2m - 1) C and a capacitance of (2 ^{n -} 2m + 1) C, a fifth, etc. An effective capacitor, wherein one of the fourth equivalent capacitors is coupled to the negative input of the comparator, and the other electrode is coupled to the ground voltage or the reference voltage, and One of the fifth equivalent capacitors is coupled to the negative input terminal of the comparator, and the other electrode is coupled to the common mode voltage, wherein n and m are positive integers and m≦2 ^N-1 . A successive approximation temporary analog analog-to-digital converter capable of reducing energy consumption as described in claim 4, wherein the logic circuit further has a register. A successive approximation temporary analog analog-to-digital converter capable of reducing energy consumption as described in claim 4, wherein the common mode voltage is lower than the reference voltage and higher than the ground voltage. A successive approximation temporary analog digital converter capable of reducing energy consumption, comprising: a comparator having a positive input terminal, a negative input terminal, and a comparison output terminal, wherein the comparison output terminal is configured to provide a a bit output value; and a voltage selection circuit for performing the following operations according to the plurality of switch control signals: planning a first capacitor array to provide a first equivalent capacitance of a capacitance (2m-1) C, and a capacitance Is a second equivalent capacitor of (2 ⁿ -2m+1)C, and a third equivalent capacitor having a capacitance of (2 ^N-1 -2 ⁿ )C, wherein the first equivalent capacitor is one of the electrodes Connected to the positive input terminal of the comparator, and the other electrode is coupled to a reference voltage or a ground voltage, and one of the second equivalent capacitors and the positive input of the comparator The other end is coupled to a common mode voltage, and one of the third equivalent capacitors is coupled to the positive input end of the comparator, and the other electrode is floated State; and planning a second capacitor array to provide a fourth equivalent capacitance having a capacitance of (2m-1)C, The fifth equivalent capacitance of the capacitance (2 ⁿ -2m+1) C and the sixth equivalent capacitance of the capacitance (2 ^N-1 -2 ⁿ ) C, wherein the fourth equivalent capacitance An electrode is coupled to the negative input of the comparator, and another electrode is coupled to the ground voltage or the reference voltage, and one of the fifth equivalent capacitors is compared The negative input terminal of the device is coupled to the common mode voltage, and the other electrode of the third equivalent capacitor is coupled to the positive input terminal of the comparator. The other electrode is in a floating state, where n and m are positive integers and m≦2 ^n-1 .