CN116936601A

CN116936601A - Integrated chip, preparation method thereof and display device

Info

Publication number: CN116936601A
Application number: CN202310900303.8A
Authority: CN
Inventors: 周玮; 陈家华
Original assignee: Shenzhen Stan Technology Co Ltd
Current assignee: Shenzhen Stan Technology Co Ltd
Priority date: 2023-07-21
Filing date: 2023-07-21
Publication date: 2023-10-24
Anticipated expiration: 2043-07-21
Also published as: CN116936601B

Abstract

The disclosure provides an integrated chip, a preparation method thereof and a display device. The method comprises the following steps: providing a substrate provided with a first passivation layer, wherein the substrate is provided with an array of micro LED areas, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate; forming a micro LED epitaxial wafer in each micro LED region; etching each micro LED epitaxial wafer to form a micro LED mesa structure array comprising a boss, so as to obtain a first intermediate structure; disposing a second passivation layer on the first intermediate structure; a driving structure is arranged on the second passivation layer at one side of the boss of each micro LED mesa structure; a first electrode metal layer and a second electrode metal layer are arranged on each micro LED mesa structure, and a third electrode metal layer is arranged on each driving structure, wherein the second electrode metal layer and the third electrode metal layer are connected into a whole.

Description

Integrated chip, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of semiconductor LEDs, in particular to an integrated chip, a preparation method thereof and a display device.

Background

The Micro-LED has the advantages of smaller size, higher resolution, higher brightness, higher luminous efficiency, lower power consumption, good controllability and the like. The Micro-LED display technology is particularly suitable for application fields of Micro-display such as Virtual Reality (VR) and augmented Reality (Augmented Reality, AR). The bonding of Micro-LEDs and a driving chip is mainly realized by adopting a mode of mass transfer or single-chip bonding, and the conditions of low yield, easy occurrence of dead points and the like are the main problems for preventing mass production. Therefore, integrating the Micro-LED with the driver chip, so that the Micro-LED chip can be driven without bonding the Micro-LED with the driver chip, is a better solution.

However, in the related art, there are still some problems in the single-substrate integration of Micro-LEDs with a driving chip, so that the reliability of the formed integrated chip is low.

Disclosure of Invention

In order to solve the technical problems mentioned in the background art, the scheme of the disclosure provides an integrated chip, a preparation method thereof and a display device.

According to one aspect of an embodiment of the present disclosure, a method of integrated chip fabrication is provided. The method comprises the following steps: providing a substrate provided with a first passivation layer, wherein the substrate is provided with an array of micro LED areas, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate; performing epitaxial growth in each micro LED region in the array of micro LED regions and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer comprising a first semiconductor layer, a multiple quantum well structure and a second semiconductor layer; etching each micro LED epitaxial wafer from the second semiconductor layer, exposing the first semiconductor layer to form a micro LED mesa structure array, and obtaining a first intermediate structure, wherein each micro LED mesa structure in the micro LED mesa structure array comprises a boss; disposing a second passivation layer on the first intermediate structure; setting a corresponding driving structure on a second passivation layer on the first passivation layer at one side of a boss of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure comprises a first driving electrode; for the second intermediate structure, a first electrode metal layer is arranged on the exposed first semiconductor layer of each micro LED mesa structure, a second electrode metal layer is arranged on the second semiconductor layer of each micro LED mesa structure, and a third electrode metal layer is arranged on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

Further, providing a substrate provided with a first passivation layer, wherein the substrate has an array of micro LED areas thereon, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate comprising: providing a substrate; disposing a first passivation layer on the substrate; and etching the first passivation layer to expose the substrate, so as to form a micro LED area array.

Further, the height of each micro LED epitaxial wafer in the array of micro LED epitaxial wafers is flush with the height of the first passivation layer.

Further, for the second intermediate structure, disposing a first electrode metal layer on the exposed first semiconductor layer of each micro LED mesa, disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa, disposing a third electrode metal layer on the first driving electrode of each driving structure, wherein the second electrode metal layer disposed on each micro LED mesa and the third electrode metal layer disposed on the corresponding driving structure are integrally connected, comprising: disposing a third passivation layer on the second intermediate structure; starting from the third passivation layer, a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes are formed, so that each first contact hole exposes a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposes a second semiconductor layer on a boss of the corresponding micro LED mesa, and each third contact hole exposes a first driving electrode of the corresponding driving structure; the first electrode metal layer is arranged on the exposed first semiconductor layer, the second electrode metal layer is arranged on the exposed second semiconductor layer, and the third electrode metal layer is arranged on the exposed first driving electrode, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

Further, the driving structure further comprises a second driving electrode, the method further comprising: a plurality of fourth contact holes are formed from the third passivation layer, so that each fourth contact hole exposes a second driving electrode of a corresponding driving structure; a fourth electrode metal layer is disposed on the exposed second driving electrode.

Further, a corresponding driving structure is arranged on a second passivation layer on the first passivation layer at one side of a boss of each micro LED mesa structure, so as to obtain a second intermediate structure, wherein the driving structure comprises a first driving electrode comprising: an active layer is arranged on a second passivation layer on the first passivation layer on one side of a boss of each micro LED mesa structure to obtain a third intermediate structure, wherein the active layer comprises a middle part, and a first part and a second part which are positioned on two sides of the middle part; a dielectric layer is arranged on the third intermediate structure; a third driving electrode is arranged on the dielectric layer and corresponds to the middle part of the active layer; ion implantation is performed on a first portion of the active layer to form a first driving electrode, and ion implantation is performed on a second portion to form a second driving electrode, and the intermediate portion in which ions are not implanted forms a conductive channel.

Further, disposing an active layer on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure includes: disposing an amorphous silicon layer over the entire second passivation layer; carrying out laser annealing on the amorphous silicon layer to form a polycrystalline silicon layer; and etching the polycrystalline silicon layer to form an active layer based on polycrystalline silicon on the second passivation layer on the first passivation layer at the boss side of each micro LED mesa structure.

Further, before disposing a second passivation layer on the first intermediate structure, the method further comprises: providing a current spreading layer on the second semiconductor layer of the mesa, and providing a second passivation layer on the first intermediate structure includes: disposing a second passivation layer on the first intermediate structure provided with the current spreading layer, disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa structure includes: and a second electrode metal layer is arranged on the current expansion layer.

Further, each micro LED epitaxial wafer is etched from the second semiconductor layer, the first semiconductor layer is exposed to form a micro LED mesa structure array, and a first intermediate structure is obtained, wherein each micro LED mesa structure in the micro LED mesa structure array comprises a boss including: and starting to etch each micro LED epitaxial wafer from the second semiconductor layer to form the boss, so that the side wall of each micro LED epitaxial wafer, which is positioned on one side of the boss, is not etched.

Further, the driving structure includes a TFT chip, the first driving electrode is a source electrode, the second driving electrode is a drain electrode, the third driving electrode is a gate electrode, the first electrode metal layer is a cathode metal layer, the second electrode metal layer is an anode metal layer, the third electrode metal layer is a source electrode metal layer, the fourth metal layer is a drain electrode metal layer, and the anode metal layer and the source electrode metal layer are connected together.

Further, the micro LED epitaxial wafer further includes a buffer layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer, wherein the buffer layer is located between the substrate and the first semiconductor layer, the third semiconductor layer is located between the buffer layer and the first semiconductor layer, the fourth semiconductor layer is located between the first semiconductor layer and the multiple quantum well structure, the fifth semiconductor layer is located between the fourth semiconductor layer and the multiple quantum well structure, the sixth semiconductor layer is located between the second semiconductor layer and the multiple quantum well structure, the seventh semiconductor layer is located above the second semiconductor layer and the substrate is a sapphire substrate, the buffer layer is an AlN layer or GaN layer, the first semiconductor layer is an N-layer, the second semiconductor layer is a P-layer, the third semiconductor layer is a U-GaN layer, the fourth semiconductor layer is an ingap-GaN layer, the fifth semiconductor layer is an ingap-GaN layer, the seventh semiconductor layer is an ingap-GaN layer, the GaN layer is a P-GaN layer, and the seventh semiconductor layer is an ingap-GaN layer.

According to another aspect of the present disclosure, there is also provided an integrated chip. The integrated chip includes: a substrate; a first passivation layer disposed on the substrate and including an array of micro LED areas exposing the substrate; a micro LED mesa array, each micro LED mesa in the micro LED mesa array disposed in a corresponding micro LED region in the micro LED region array and on the exposed substrate, wherein each micro LED mesa in the micro LED mesa array comprises a mesa comprising a first semiconductor layer, a multiple quantum well structure, and a second semiconductor layer and an exposed first semiconductor layer; a second passivation layer disposed on the array of micro LED mesas and the first semiconductor layer; a driving structure disposed on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa, and including a first driving electrode; a first electrode metal layer disposed on the exposed first semiconductor layer of each micro LED mesa; a second electrode metal layer disposed on the second semiconductor layer of each micro LED mesa; and the third electrode metal layer is arranged on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

Further, the height of the boss is flush with the height of the first passivation layer.

Further, the integrated chip further includes: a third passivation layer disposed on the second passivation layer and the driving structure; a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes, each first contact hole exposing a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposing a second semiconductor layer on a boss of a corresponding micro LED mesa and each third contact hole exposing a first drive electrode of a corresponding drive structure; a first electrode metal layer disposed on the exposed first semiconductor layer through the first contact hole; a second electrode metal layer disposed on the exposed second semiconductor layer through the second contact hole; and the third electrode metal layer is arranged on the exposed first driving electrode through a third contact hole, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

Further, the driving structure further includes a second driving electrode, and the integrated chip further includes: a plurality of fourth contact holes, each exposing the second driving electrode of the corresponding driving structure; and a fourth electrode metal layer disposed on the exposed second driving electrode through the fourth contact hole.

Further, the driving structure includes: an active layer disposed on a second passivation layer on the first passivation layer on a boss side of each micro LED mesa, the active layer including the first driving electrode, the second driving electrode, and a conductive channel between the first driving electrode and the second driving electrode; a dielectric layer disposed on the active layer; and a third driving electrode disposed on the dielectric layer and corresponding to a position of the conductive channel of the active layer.

Further, the integrated chip further comprises a current expansion layer, the current expansion layer is arranged on the second semiconductor layer of the boss, and the second electrode metal layer is arranged on the current expansion layer.

Further, the boss is located at one side of the micro LED region, and a sidewall of the boss is in contact with a sidewall of the first passivation layer.

According to still another aspect of the embodiments of the present disclosure, there is also provided a display device. The display device comprises the integrated chip prepared by the method or the integrated chip.

By applying the technical scheme disclosed by the invention, the micro LED structure and the driving mechanism can be formed on the same substrate, and the micro LED structure and the driving structure are not required to be connected in a mode of massive transfer or single-chip bonding to form the micro LED display module, so that the process and the structure of the micro LED display module are simplified, the conditions of yield reduction, easy occurrence of dead points and the like are further reduced, and the mass production of the micro LED display module is facilitated. In addition, by applying the technical scheme disclosed by the invention, the micro LED area array surrounded by the passivation layer can be formed, the corresponding micro LED epitaxial wafer array is formed in the micro LED area array, the micro LED mesa structure comprising the boss can be prepared through the micro LED epitaxial wafer, and then the driving structure is prepared on the passivation layer beside the micro LED mesa structure. In addition, by applying the technical scheme disclosed by the invention, the micro LED area array surrounded by the passivation layer can be formed, the corresponding micro LED epitaxial wafer array is formed in the micro LED area array, and the micro LED structure is prepared through each micro LED epitaxial wafer, so that the definition of the micro LED luminous area by using an etching method can be avoided, namely, the formation of a plurality of micro LED structures through the etching of one epitaxial wafer is avoided, the damage of the etching to the side wall of the formed micro LED structure is further avoided, and the reliability of the prepared integrated chip is improved.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 is a flow chart illustrating a method of integrated chip fabrication according to one embodiment of the present disclosure;

fig. 2 to 15 are schematic views illustrating a manufacturing process flow of an integrated chip manufacturing method according to an embodiment of the present disclosure.

Detailed Description

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be oriented 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

Exemplary embodiments according to the present disclosure will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art, that in the drawings, thicknesses of layers and regions are exaggerated for clarity, and identical reference numerals are used to denote identical devices, and thus descriptions thereof will be omitted.

In the related art, the Micro-LED structure is generally connected with the driving structure by a mode of transferring a large amount or bonding a single chip, but the two connection modes can have pixel offset or pixel damage, thereby causing the conditions of reduced yield, easy occurrence of dead spots and the like, and further preventing mass production of the Micro-LED. Micro-LED-driver integration that uses drivers to drive Micro-LEDs without the need for mass transfer or monolithic bonding is a better solution. However, when the Micro-LED is integrated with the driver, the Micro-LED structure and the driver structure need to be wired and climbed when being connected with the electrode, so that the reliability of the integrated chip is reduced. In addition, in some related art, the driving structure is disposed at the light emitting side of the micro LED structure, and thus, in order to avoid the driving structure from blocking the light emitting of the micro LED structure, a complicated manufacturing process, such as flipping or transferring of the substrate, may be employed.

The present disclosure provides a method of manufacturing an integrated chip. Referring to fig. 1 to 15, fig. 1 is a flowchart illustrating an integrated chip manufacturing method according to an embodiment of the present disclosure; fig. 2 to 15 are schematic views illustrating a manufacturing process flow of an integrated chip manufacturing method according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, the pixel size in Micro LEDs (Micro-LEDs) and driver integrated chips is typically less than or equal to 200 microns.

As shown in fig. 1, the integrated chip manufacturing method includes the following steps S101 to S106.

Step S101 of providing a substrate provided with a first passivation layer, wherein the substrate has an array of micro LED areas thereon, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate.

And step S102, carrying out epitaxial growth in each micro LED area in the micro LED area array and on the exposed substrate to form a micro LED epitaxial wafer array, wherein each micro LED epitaxial wafer comprises a first semiconductor layer, a multi-quantum well structure and a second semiconductor layer.

And step S103, etching each micro LED epitaxial wafer from the second semiconductor layer, exposing the first semiconductor layer to form a micro LED mesa structure array, and obtaining a first intermediate structure, wherein each micro LED mesa structure in the micro LED mesa structure array comprises a boss.

And step S104, a second passivation layer is arranged on the first intermediate structure.

And step 105, setting a corresponding driving structure on a second passivation layer on the first passivation layer at one side of the boss of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure comprises a first driving electrode.

And S106, aiming at the second intermediate structure, arranging a first electrode metal layer on the exposed first semiconductor layer of each micro LED mesa structure, arranging a second electrode metal layer on the second semiconductor layer of each micro LED mesa structure, and arranging a third electrode metal layer on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure and the third electrode metal layer arranged on the corresponding driving structure are connected into a whole.

According to the technical scheme, the micro LED structure and the driving mechanism can be formed on the same substrate, the micro LED structure and the driving structure are not required to be connected in a huge amount transfer or single-chip bonding mode to form the micro LED display module, and therefore the process and the structure of the micro LED display module are simplified, the conditions of yield reduction, dead points and the like are reduced, and mass production of the micro LED display module is facilitated. According to the technical scheme, the micro LED area array surrounded by the passivation layer can be formed, the corresponding micro LED epitaxial wafer array is formed in the micro LED area array, the micro LED mesa structure comprising the boss can be prepared through the micro LED epitaxial wafer, and then the driving structure is prepared on the passivation layer beside the micro LED mesa structure. In addition, according to the technical scheme, the micro LED area array surrounded by the passivation layer can be formed, the corresponding micro LED epitaxial wafer array is formed in the micro LED area array, and the micro LED structure is prepared through each micro LED epitaxial wafer, so that the definition of the micro LED luminous area by using an etching method can be avoided, namely, the formation of a plurality of micro LED structures through etching of one epitaxial wafer is avoided, the damage of etching to the side wall of the formed micro LED structure is further avoided, and the reliability of the prepared integrated chip is improved.

In step S101, a substrate provided with a first passivation layer may be provided, wherein the substrate has an array of micro LED areas thereon, and each micro LED area of the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate.

According to an embodiment of the present disclosure, there is provided a substrate provided with a first passivation layer, wherein the substrate has an array of micro LED areas thereon, and each micro LED area of the array of micro LED areas is surrounded by the first passivation layer and exposing the substrate may include: providing a substrate; disposing a first passivation layer on the substrate; and etching the first passivation layer to expose the substrate, so as to form a micro LED area array.

In this embodiment, in order to prepare an integrated chip, a substrate may be obtained first. The micro LED structure and the driving structure included in the integrated chip are prepared on the same substrate.

Further, the substrate may be a sapphire substrate, a monocrystalline silicon substrate, a SiC substrate, or the like, but may be any other transparent or opaque substrate, which is not limited herein.

Referring to fig. 2-15, wherein fig. 2 illustrates a side view of a substrate 101 according to one embodiment of the present disclosure.

After the substrate is obtained, a passivation layer may be disposed on the substrate.

Referring to fig. 2-15, fig. 3 illustrates a side view of a first passivation layer 102 disposed on a substrate 101 according to one embodiment of the present disclosure. As shown in fig. 3, a first passivation layer 102 may be deposited on the substrate 101 using a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD).

After the first passivation layer is provided, an array of micro LED areas to be fabricated into an array of micro LED structures may be etched on the first passivation layer.

Referring to fig. 2-15, fig. 4 illustrates a side view of a micro LED region 1021 formed in a first passivation layer 102 according to one embodiment of the present disclosure. As shown in fig. 4, only one micro LED area 1021 is shown for the sake of simplicity and clarity, and in practical applications, the number of micro LED areas 1021 may be determined according to the number of micro LED structures (light emitting structures) actually required. In this embodiment, the first passivation layer 102 may be patterned by photoresist, and the micro LED region 1021 may be etched by inductively coupled plasma (Inductively Coupled Plasma, ICP) etching, and the photoresist removed to form the structure shown in fig. 4. Wherein the micro LED area 1021 exposes a portion of the substrate 101.

In step S102, epitaxial growth may be performed in each micro LED region in the array of micro LED regions and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer includes a first semiconductor layer, a multiple quantum well structure, and a second semiconductor layer.

According to embodiments of the present disclosure, epitaxial growth may be performed on the exposed substrate for each micro LED region to form a micro LED epitaxial wafer. Further, each micro LED epitaxial wafer may include a first semiconductor layer, a multiple quantum well structure, and a second semiconductor layer in order from bottom to top.

According to an embodiment of the present disclosure, the height of each micro LED epitaxial wafer in the array of micro LED epitaxial wafers is flush with the height of the first passivation layer. The height of each layer of the micro LED epitaxial wafer may be preset so that the total height of the micro LED epitaxial wafer is flush with the height of the first passivation layer. According to the technical scheme, the height of each micro LED epitaxial wafer in the corresponding micro LED epitaxial wafer array formed in the micro LED area array can be flush with the height of the passivation layer, so that the micro LED mesa structure comprising the boss can be prepared through the micro LED epitaxial wafer, the height of the boss is flush with the height of the passivation layer, and therefore when an electrode of a driving structure prepared on the passivation layer beside the micro LED mesa structure is connected with an electrode on the boss, the climbing of a connecting trace can be reduced, and the reliability of the prepared integrated chip is improved.

Further, the epitaxial wafer may further include a buffer layer between the substrate and the first semiconductor layer. In addition, the epitaxial wafer may further include a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer, wherein the third semiconductor layer is located between the buffer layer and the first semiconductor layer, the fourth semiconductor layer is located between the first semiconductor layer and the multiple quantum well structure, the fifth semiconductor layer is located between the fourth semiconductor layer and the multiple quantum well structure, the sixth semiconductor layer is located between the second semiconductor layer and the multiple quantum well structure, and the seventh semiconductor layer is located above the second semiconductor layer. The buffer layer may be an AlN layer or a GaN layer, the first semiconductor may be an N-GaN layer, the second semiconductor may be a P-GaN layer, the third semiconductor may be a U-GaN layer, the fourth semiconductor may be an N-AlGaN layer, the fifth semiconductor may be an InGa or GaN superlattice, the sixth semiconductor may be a P-AlGaN layer, and the seventh semiconductor may be a p+ -GaN layer.

Referring to fig. 2-15, fig. 5 illustrates a side view of a micro LED epitaxial wafer 10 formed in a micro LED region 1021 in accordance with one embodiment of the present disclosure. As shown in fig. 5, the micro LED epitaxial wafer 10 includes, in order from bottom to top, a buffer layer 106, a first semiconductor layer 103, a multiple quantum well structure 104, and a second semiconductor layer 105. The buffer layer 106 may be an AlN layer or a GaN layer, the first semiconductor 103 may be an N-GaN layer, and the second semiconductor 105 may be a P-GaN layer. In addition, the epitaxial wafer 10 may be deposited in the micro LED region 1021 and formed layer by layer on the substrate 101 using a Metal-organic chemical vapor deposition (MOCVD) method.

In step S103, each micro LED epitaxial wafer may be etched from the second semiconductor layer, and the first semiconductor layer is exposed to form an array of micro LED mesa structures, so as to obtain a first intermediate structure, where each micro LED mesa structure in the array of micro LED mesa structures includes a boss.

According to embodiments of the present disclosure, after the micro LED epitaxial wafer is formed, it may be etched to obtain a micro LED mesa structure including a mesa.

Further, each micro LED epitaxial wafer is etched from the second semiconductor layer, the first semiconductor layer is exposed to form a micro LED mesa structure array, and a first intermediate structure is obtained, wherein each micro LED mesa structure in the micro LED mesa structure array comprises a boss including: and starting to etch each micro LED epitaxial wafer from the second semiconductor layer to form the boss, so that the side wall of each micro LED epitaxial wafer, which is positioned on one side of the boss, is not etched. By reducing the etching of the side wall of the micro LED epitaxial wafer, the possibility of damage to the side wall of the micro LED epitaxial wafer can be reduced, so that the reliability of the prepared integrated chip is further improved.

Further, referring to fig. 2-15, fig. 6 shows a schematic side cross-sectional view of a micro LED mesa 20 etched into a micro LED epitaxial wafer.

Specifically, a photoresist may be coated on the micro LED epitaxial wafer 10 and the first passivation layer 102, and then the photoresist is exposed, developed, and baked to photo-etch the pattern of the micro LED mesa structure. Subsequently, the patterned etching obtained by photolithography is mapped to the micro LED epitaxial wafer by inductively coupled plasma etching (ICP), exposing the surface layer of the first semiconductor layer 103, and then the photoresist is removed, thereby forming the micro LED mesa structure 20 including the mesa 201, thereby forming the first intermediate structure 1 as shown in fig. 6. As shown in fig. 6, the etching of the micro LED epitaxial wafer may be performed by using a preset mask plate, that is, the boss 201 is formed on one side of the micro LED mesa structure 20, and the sidewall (one sidewall of the epitaxial wafer) of the boss 201 in contact with the first passivation layer 102 is not etched, so that the etching of the sidewall of the epitaxial wafer may be reduced, and the possibility of damage to the sidewall of the micro LED epitaxial wafer may be reduced.

In step S104, a second passivation layer may be disposed on the first intermediate structure.

According to an embodiment of the present disclosure, before disposing the second passivation layer on the first intermediate structure, the method may further include: and a current expansion layer is arranged on the second semiconductor layer of the boss. Thus, disposing a second passivation layer on the first intermediate structure may include: a second passivation layer is disposed on the first intermediate structure provided with the current spreading layer. Wherein the current spreading layer may include an indium tin oxide layer. By arranging the current expansion layer, the contact resistance between the electrode layer and the semiconductor layer can be improved, and the light extraction efficiency can be improved.

Referring to fig. 2-15, wherein fig. 7 shows a side cross-sectional view of the current spreading layer 107 provided on the second semiconductor layer 105 on the mesa 201 in the first intermediate structure 1. Specifically, as shown in fig. 7, the current spreading layer 107 may be disposed on the second semiconductor layer 105 of the mesa 201 using photolithography and magnetron sputtering methods, and then an annealing process may be performed using a rapid annealing technique (RTA) such that a good ohmic contact is formed between the second semiconductor layer 105 and the current spreading layer 107.

Referring to fig. 2-15, fig. 8 illustrates a side view of a second passivation layer 108 disposed on a first intermediate structure 1 provided with a current spreading layer 107, according to one embodiment of the present disclosure. As shown in fig. 8, a second passivation layer 108 may be deposited on the first intermediate structure 1 provided with the current spreading layer 107 using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

In step S105, a corresponding driving structure may be disposed on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure, to obtain a second intermediate structure, where the driving structure includes a first driving electrode.

According to the embodiment of the disclosure, the driving structure can be arranged on the second passivation layer on the first passivation layer beside the boss of each micro LED mesa structure, and the driving structure formed by the driving structure is not located right above the micro LED mesa structure but shields the micro LED mesa structure. In addition, the driving structure may further include a second driving electrode.

According to an embodiment of the disclosure, a corresponding driving structure is disposed on a second passivation layer on the first passivation layer on one side of a boss of each micro LED mesa structure, to obtain a second intermediate structure, where the driving structure includes a first driving electrode and may include: an active layer is arranged on a second passivation layer on the first passivation layer on one side of a boss of each micro LED mesa structure to obtain a third intermediate structure, wherein the active layer comprises a middle part, and a first part and a second part which are positioned on two sides of the middle part; a dielectric layer is arranged on the third intermediate structure; a third driving electrode is arranged on the dielectric layer and corresponds to the middle part of the active layer; ion implantation is performed on a first portion of the active layer to form a first driving electrode, and ion implantation is performed on a second portion to form a second driving electrode, and the intermediate portion in which ions are not implanted forms a conductive channel.

According to an embodiment of the present disclosure, the driving structure may include a TFT chip, the first driving electrode is a source electrode, the second driving electrode is a drain electrode, and the third driving electrode is a gate electrode. The TFT chip may be any suitable structure, such as a top gate structure or a bottom gate structure, and the driving structure may also be other driving chips, which is not limited herein.

Referring to fig. 2-15, fig. 9 shows a side cross-sectional view of an active layer 109, e.g., polysilicon-based, disposed on a second semiconductor layer 108. As shown in fig. 9, the active layer 109 includes a middle portion 1092 and first and second portions 1091 and 1093 located on both sides of the middle portion 1092. Specifically, an amorphous silicon layer, for example, may be first deposited on the entire second passivation layer 108 by a Plasma Enhanced Chemical Vapor Deposition (PECVD), then laser annealed for the amorphous silicon layer to form a polysilicon layer, and then patterned using photolithography and etching, thereby forming a polysilicon-based active layer 109 on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa as shown in fig. 4, thereby obtaining a third intermediate structure as shown in fig. 9.

Referring to fig. 2-15, fig. 10 illustrates a side cross-sectional view of a dielectric layer 110 disposed on a third intermediate structure as shown in fig. 9. As shown in fig. 10, a dielectric layer 110, which may be a gate oxide layer such as a silicon oxide layer, an aluminum oxide layer, or a silicon nitride layer, may be deposited on the third intermediate structure by a Plasma Enhanced Chemical Vapor Deposition (PECVD).

Referring to fig. 2-15, fig. 11 shows a side cross-sectional view of a third drive electrode 111 disposed on a dielectric layer 110. As shown in fig. 11, a third driving electrode 111 may be disposed on the dielectric layer 110 and corresponding to the middle portion 1092 of the active layer 109 by a Plasma Enhanced Chemical Vapor Deposition (PECVD). The third drive electrode is located above the intermediate portion 1092 and may be, for example, a gate electrode.

Referring to fig. 2-15, fig. 12 shows a side cross-sectional view of the first and second drive electrodes 1094, 1095. As shown in fig. 12, the first portion 1091 of the active layer 109 is ion-implanted to form a first driving electrode 1094, and the second portion 1092 is ion-implanted to form a second driving electrode 1095, and the intermediate portion 1093, into which ions are not implanted, forms a conductive channel, so that the driving structure is completed, resulting in the second intermediate structure 2 shown in fig. 12. The first driving electrode 1094 may be, for example, a source, and the second driving electrode 1095 may be, for example, a drain.

In step S106, for the second intermediate structure, a first electrode metal layer may be disposed on the exposed first semiconductor layer of each micro LED mesa, a second electrode metal layer may be disposed on the second semiconductor layer of each micro LED mesa, and a third electrode metal layer may be disposed on the first driving electrode of each driving structure, wherein the second electrode metal layer disposed on each micro LED mesa is integrally connected with the third electrode metal layer disposed on the corresponding driving structure.

According to embodiments of the present disclosure, after the driving structure is completed, an electrode may be provided for the micro LED mesa and connected with the electrode of the driving structure.

Specifically, for the second intermediate structure, disposing a first electrode metal layer on the exposed first semiconductor layer of each micro LED mesa, disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa, disposing a third electrode metal layer on the first driving electrode of each driving structure, wherein the second electrode metal layer disposed on each micro LED mesa and the third electrode metal layer disposed on the corresponding driving structure are integrally connected, comprising: disposing a third passivation layer on the second intermediate structure; starting from the third passivation layer, a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes are formed, so that each first contact hole exposes a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposes a second semiconductor layer on a boss of the corresponding micro LED mesa, and each third contact hole exposes a first driving electrode of the corresponding driving structure; the first electrode metal layer is arranged on the exposed first semiconductor layer, the second electrode metal layer is arranged on the exposed second semiconductor layer, and the third electrode metal layer is arranged on the exposed first driving electrode, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

According to an embodiment of the present disclosure, when the driving structure further comprises a second driving electrode, the method further comprises: a plurality of fourth contact holes are formed from the third passivation layer, so that each fourth contact hole exposes a second driving electrode of a corresponding driving structure; a fourth electrode metal layer is disposed on the exposed second driving electrode.

According to an embodiment of the present disclosure, when the current spreading layer is disposed on the second semiconductor layer of the mesa, disposing the second electrode metal layer on the second semiconductor layer of each micro LED mesa includes: and a second electrode metal layer is arranged on the current expansion layer.

According to an embodiment of the disclosure, the first electrode metal layer is a cathode metal layer, the second electrode metal layer is an anode metal layer, the third electrode metal layer is a source metal layer, the fourth metal layer is a drain metal layer, and the anode metal layer is integrally connected with the source metal layer.

Referring to fig. 2-15, fig. 13 shows a side cross-sectional view of a third passivation layer 112 disposed on the second intermediate structure 2. As shown in fig. 13, a third passivation layer 112 may be deposited on the second intermediate structure 2 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

Referring to fig. 2-15, fig. 14 shows side cross-sectional views of the first contact hole 113, the second contact hole 114, the third contact hole 115, and the fourth contact hole 116. As shown in fig. 14, after the third passivation layer 112 is deposited, patterns of the first contact hole 113, the second contact hole 114, the third contact hole 115 and the fourth contact hole 116 are photoresist-coated and etched on the third passivation layer 112, and the first contact hole 113, the second contact hole 114, the third contact hole 115 and the fourth contact hole 116 are etched by using an Inductively Coupled Plasma (ICP) etching method, and the photoresist is removed to form the structure shown in fig. 14. Wherein each first contact hole 113 exposes the first semiconductor layer 103 of the corresponding micro LED mesa through the third passivation layer 112, the dielectric layer 110 and the second passivation layer 108, each second contact hole 114 exposes the current spreading layer 107 on the mesa of the corresponding micro LED mesa through the third passivation layer 112, the dielectric layer 110 and the second passivation layer 108, each third contact hole 115 exposes the first driving electrode 1094 of the corresponding driving structure, such as a source electrode, through the third passivation layer 112 and the dielectric layer 110, and each fourth contact hole 116 exposes the second driving electrode 1095 of the corresponding driving structure, such as a drain electrode, through the third passivation layer 112 and the dielectric layer 110.

Referring to fig. 2-15, wherein fig. 15 shows a side view of first electrode metal layer 117, second electrode metal layer 118, third electrode metal layer 119, and fourth electrode metal layer 120. Specifically, as shown in fig. 15, a metal layer may be deposited on the third passivation layer 112 and the exposed first semiconductor layer 103, the current spreading layer 107, the first driving electrode 1094, and the second driving electrode 1095 using photolithography and electron beam evaporation methods, and then photoresist and excess metal may be removed using a lift-off process to obtain the first electrode metal layer 117, the second electrode metal layer 118, the third electrode metal layer 119, and the fourth electrode metal layer 120. The first electrode metal layer is, for example, a cathode metal layer and the second electrode metal layer is, for example, an anode metal layer, wherein the second electrode metal layer 118, such as the anode metal layer, is integrated with the third electrode metal layer 119, such as the source electrode, provided on the corresponding driving structure, thereby obtaining the integrated chip 3 as shown in fig. 15. Wherein the second electrode metal layer 118 may be an anode metal layer that serves as the anode of the micro LED mesa and the first electrode metal layer 117 may be a cathode metal layer that serves as the cathode of the micro LED mesa that is disposed on the exposed first semiconductor layer 103, all cathodes disposed on the micro LED mesa may be connected together to ground, although the cathode is disposed at a valley, and thus need not be LED off uphill. In addition, as shown in fig. 15, since the first driving electrode 1094 of the driving structure is substantially flush with the height of the current spreading layer 107 on the micro LED mesa structure, the trace climbing is greatly reduced when the first driving electrode 1094 and the current spreading layer 107 are connected by the electrode metal layer, thereby facilitating the reliability of the integrated chip.

Thus, the integrated chip preparation is completed, and fig. 15 shows the integrated chip 3 prepared according to one embodiment of the present disclosure.

The disclosure also provides an integrated chip.

As shown in fig. 2 to 15, the integrated chip 3 includes: a substrate 101; a first passivation layer 102 disposed on the substrate 101 and including an array of micro LED areas exposing the substrate; a micro LED mesa array, each micro LED mesa 20 of the micro LED mesa array being disposed in a corresponding micro LED region 1021 of the micro LED region array and on the exposed substrate 101, wherein each micro LED mesa 20 of the micro LED mesa array comprises a mesa 201 and an exposed first semiconductor layer 103, the mesa 201 comprising a first semiconductor layer 103, a multiple quantum well structure 104 and a second semiconductor layer 105; a second passivation layer 108 disposed on the array of micro LED mesas and the first semiconductor layer 102; a driving structure disposed on the second passivation layer 108 on the first passivation layer 102 on the boss 201 side of each micro LED mesa 20, and including a first driving electrode 1094; a first electrode metal layer 117 disposed on the exposed first semiconductor layer 103 of each micro LED mesa 20; a second electrode metal layer 118 disposed on the second semiconductor layer 105 of the mesa 201 of each micro LED mesa 20; and a third electrode metal layer 119 disposed on the first driving electrode 1094 of each driving structure, wherein the second electrode metal layer 118 disposed on each micro LED mesa 20 is integrally connected with the third electrode metal layer 119 disposed on the corresponding driving structure.

According to an embodiment of the present disclosure, the height of the boss 201 is flush with the height of the first passivation layer 102.

According to an embodiment of the present disclosure, the mesa 201 includes the first semiconductor layer 103, the multiple quantum well structure 104, and the second semiconductor layer 105 in this order from bottom to top.

According to an embodiment of the present disclosure, the integrated chip 3 further includes: a third passivation layer 112 disposed on the second passivation layer 108 and the driving structure; a plurality of first contact holes 113, a plurality of second contact holes 114, and a plurality of third contact holes 115, each first contact hole 113 exposing the first semiconductor layer 103 of the corresponding micro LED mesa 20, each second contact hole 114 exposing the second semiconductor layer 105 on the mesa 201 of the corresponding micro LED mesa 20, and each third contact hole 115 exposing the first driving electrode 1094 of the corresponding driving structure; a first electrode metal layer 117 disposed on the exposed first semiconductor layer 103 through the first contact hole 113; a second electrode metal layer 118 disposed on the exposed second semiconductor layer 105 through the second contact hole 114; a third electrode metal layer 119 disposed on the exposed first driving electrode 1094 through a third contact hole 115, wherein a second electrode metal layer 118 disposed on each micro LED mesa 20 is integrally connected with the third electrode metal layer 119 disposed on the corresponding driving structure.

According to an embodiment of the present disclosure, the driving structure further includes a second driving electrode 1095, and the integrated chip 3 further includes: a plurality of fourth contact holes 116, each fourth contact hole 116 exposing the second driving electrode 1095 of the corresponding driving structure; a fourth electrode metal layer 120 disposed on the exposed second driving electrode 1095 through the fourth contact hole 116.

According to an embodiment of the present disclosure, the driving structure includes: an active layer 109 disposed on the second passivation layer 108 on the first passivation layer 102 on the boss 201 side of each micro LED mesa 20, the active layer 109 including the first driving electrode 1094, the second driving electrode 1095, and a conductive channel between the first driving electrode 1094 and the second driving electrode 1095; a dielectric layer 110 disposed on the active layer 109; and a third driving electrode 111 disposed on the dielectric layer 110 and corresponding to a position of a conductive channel of the active layer 109.

According to an embodiment of the present disclosure, the integrated chip 3 further includes a current spreading layer 107, the current spreading layer 107 is disposed on the second semiconductor layer 105 of the boss 201, and the second electrode metal layer 118 is disposed on the current spreading layer 107.

According to an embodiment of the present disclosure, the boss 201 is located at one side of the micro LED region 1021, and a sidewall of the boss 201 is in contact with a sidewall of the first passivation layer 102.

It is noted that any of the relevant descriptions (including but not limited to technical features and their roles, explanations, etc.) regarding the structure of the integrated chip in the above-described integrated chip manufacturing method can be applied to the integrated chip of the present disclosure.

The disclosure also provides a display device. The display device comprises the integrated chip. The display device can be applied to electronic equipment to realize technologies such as AR, VR, extended Reality (XR), mixed Reality (MR) and the like. For example, the Display device may be a projection portion of an electronic apparatus, such as a projector, head Up Display (HUD), or the like; for another example, the display device may be a display portion of an electronic apparatus, and for example, the electronic apparatus may include: smart phones, smart watches, notebook computers, tablet computers, automobile recorders, navigator, head-mounted devices, and any device having a display screen.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence number of each step/process described above does not mean that the execution sequence of each step/process should be determined by its functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. Moreover, the foregoing description of the embodiments of the application is provided for the purpose of illustration only, and does not represent the advantages or disadvantages of the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically illustrated and described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The foregoing description of the preferred embodiments of the present disclosure is provided only and not intended to limit the disclosure so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method of integrated chip fabrication, wherein the method comprises:

providing a substrate provided with a first passivation layer, wherein the substrate is provided with an array of micro LED areas, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate;

performing epitaxial growth in each micro LED region in the array of micro LED regions and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer comprising a first semiconductor layer, a multiple quantum well structure and a second semiconductor layer;

etching each micro LED epitaxial wafer from the second semiconductor layer, exposing the first semiconductor layer to form a micro LED mesa structure array, and obtaining a first intermediate structure, wherein each micro LED mesa structure in the micro LED mesa structure array comprises a boss;

Disposing a second passivation layer on the first intermediate structure;

setting a corresponding driving structure on a second passivation layer on the first passivation layer at one side of a boss of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure comprises a first driving electrode;

for the second intermediate structure, a first electrode metal layer is arranged on the exposed first semiconductor layer of each micro LED mesa structure, a second electrode metal layer is arranged on the second semiconductor layer of each micro LED mesa structure, and a third electrode metal layer is arranged on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

2. The integrated chip manufacturing method according to claim 1, wherein providing a substrate provided with a first passivation layer, wherein the substrate has an array of micro LED areas thereon, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate comprises:

providing a substrate;

disposing a first passivation layer on the substrate;

and etching the first passivation layer to expose the substrate, so as to form a micro LED area array.

3. The integrated chip manufacturing method of claim 1, wherein a height of each micro LED epitaxial wafer in the array of micro LED epitaxial wafers is flush with a height of the first passivation layer.

4. The integrated chip manufacturing method according to claim 1, wherein for the second intermediate structure, disposing a first electrode metal layer on the exposed first semiconductor layer of each micro LED mesa, disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa, disposing a third electrode metal layer on the first driving electrode of each driving structure, wherein the disposing the second electrode metal layer on each micro LED mesa integrally with the disposing the third electrode metal layer on the corresponding driving structure comprises:

disposing a third passivation layer on the second intermediate structure;

starting from the third passivation layer, a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes are formed, so that each first contact hole exposes a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposes a second semiconductor layer on a boss of the corresponding micro LED mesa, and each third contact hole exposes a first driving electrode of the corresponding driving structure;

The first electrode metal layer is arranged on the exposed first semiconductor layer, the second electrode metal layer is arranged on the exposed second semiconductor layer, and the third electrode metal layer is arranged on the exposed first driving electrode, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

5. The integrated chip manufacturing method according to claim 4, wherein the driving structure further includes a second driving electrode, the method further comprising:

a plurality of fourth contact holes are formed from the third passivation layer, so that each fourth contact hole exposes a second driving electrode of a corresponding driving structure;

a fourth electrode metal layer is disposed on the exposed second driving electrode.

6. The method of claim 5, wherein a corresponding driving structure is disposed on a second passivation layer on the first passivation layer on a boss side of each micro LED mesa, resulting in a second intermediate structure, wherein the driving structure includes a first driving electrode including:

an active layer is arranged on a second passivation layer on the first passivation layer on one side of a boss of each micro LED mesa structure to obtain a third intermediate structure, wherein the active layer comprises a middle part, and a first part and a second part which are positioned on two sides of the middle part;

A dielectric layer is arranged on the third intermediate structure;

a third driving electrode is arranged on the dielectric layer and corresponds to the middle part of the active layer;

ion implantation is performed on a first portion of the active layer to form a first driving electrode, and ion implantation is performed on a second portion to form a second driving electrode, and the intermediate portion in which ions are not implanted forms a conductive channel.

7. The integrated chip manufacturing method according to claim 6, wherein disposing an active layer on the second passivation layer on the first passivation layer on the mesa side of each micro LED mesa comprises:

disposing an amorphous silicon layer over the entire second passivation layer;

carrying out laser annealing on the amorphous silicon layer to form a polycrystalline silicon layer;

and etching the polycrystalline silicon layer to form an active layer based on polycrystalline silicon on the second passivation layer on the first passivation layer at the boss side of each micro LED mesa structure.

8. The integrated chip manufacturing method of claim 1, wherein prior to disposing a second passivation layer on the first intermediate structure, the method further comprises: a current spreading layer is provided on the second semiconductor layer of the mesa,

Disposing a second passivation layer on the first intermediate structure includes: a second passivation layer is provided on the first intermediate structure provided with the current spreading layer,

disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa structure comprises: and a second electrode metal layer is arranged on the current expansion layer.

9. The integrated chip manufacturing method of claim 1, wherein etching each micro LED epitaxial wafer from the second semiconductor layer exposes the first semiconductor layer to form an array of micro LED mesas resulting in a first intermediate structure, wherein each micro LED mesa in the array of micro LED mesas comprises a boss comprising: and starting to etch each micro LED epitaxial wafer from the second semiconductor layer to form the boss, so that the side wall of each micro LED epitaxial wafer, which is positioned on one side of the boss, is not etched.

10. The integrated chip manufacturing method according to claim 6, wherein the driving structure includes a TFT chip, the first driving electrode is a source electrode, the second driving electrode is a drain electrode, the third driving electrode is a gate electrode, the first electrode metal layer is a cathode metal layer, the second electrode metal layer is an anode metal layer, the third electrode metal layer is a source metal layer, the fourth metal layer is a drain metal layer, and the anode metal layer is integrally connected with the source metal layer.

11. The integrated chip manufacturing method according to any one of claims 1 to 10, wherein the micro LED epitaxial wafer further comprises a buffer layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer, the buffer layer being located between the substrate and the first semiconductor layer, the third semiconductor layer being located between the buffer layer and the first semiconductor layer, the fourth semiconductor layer being located between the first semiconductor layer and the multiple quantum well structure, the fifth semiconductor layer being located between the fourth semiconductor layer and the multiple quantum well structure, the sixth semiconductor layer being located between the second semiconductor layer and the multiple quantum well structure, the seventh semiconductor layer being located above the second semiconductor layer and the substrate being a blue substrate, the buffer layer being an AlN layer or an N-layer, the second semiconductor layer being a P-layer, the third semiconductor layer being a P-GaN layer, the fifth semiconductor layer being a GaN layer, the GaN layer.

12. An integrated chip, wherein the integrated chip comprises:

a substrate;

a first passivation layer disposed on the substrate and including an array of micro LED areas exposing the substrate;

a micro LED mesa array, each micro LED mesa in the micro LED mesa array disposed in a corresponding micro LED region in the micro LED region array and on the exposed substrate, wherein each micro LED mesa in the micro LED mesa array comprises a mesa comprising a first semiconductor layer, a multiple quantum well structure, and a second semiconductor layer and an exposed first semiconductor layer;

a second passivation layer disposed on the array of micro LED mesas and the first semiconductor layer;

a driving structure disposed on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa, and including a first driving electrode;

a first electrode metal layer disposed on the exposed first semiconductor layer of each micro LED mesa;

a second electrode metal layer disposed on the second semiconductor layer of each micro LED mesa;

And the third electrode metal layer is arranged on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

13. The integrated chip of claim 12, wherein a height of the boss is flush with a height of the first passivation layer.

14. The integrated chip of claim 12, wherein the integrated chip further comprises:

a third passivation layer disposed on the second passivation layer and the driving structure;

a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes, each first contact hole exposing a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposing a second semiconductor layer on a boss of a corresponding micro LED mesa and each third contact hole exposing a first drive electrode of a corresponding drive structure;

a first electrode metal layer disposed on the exposed first semiconductor layer through the first contact hole;

a second electrode metal layer disposed on the exposed second semiconductor layer through the second contact hole;

A third electrode metal layer disposed on the exposed first driving electrode through a third contact hole,

the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

15. The integrated chip of claim 14, wherein the drive structure further comprises a second drive electrode, the integrated chip further comprising:

a plurality of fourth contact holes, each exposing the second driving electrode of the corresponding driving structure;

and a fourth electrode metal layer disposed on the exposed second driving electrode through the fourth contact hole.

16. The integrated chip of claim 15, wherein the driving structure comprises:

an active layer disposed on the second passivation layer on the first passivation layer at the boss side of each micro LED mesa structure, the active layer including the first driving electrode, the first driving electrode

A second drive electrode and a conductive channel between the first drive electrode and the second drive electrode;

a dielectric layer disposed on the active layer;

and a third driving electrode disposed on the dielectric layer and corresponding to a position of the conductive channel of the active layer.

17. The integrated chip of claim 12, further comprising a current spreading layer disposed on the second semiconductor layer of the mesa, the second electrode metal layer disposed on the current spreading layer.

18. The integrated chip of claim 12, wherein the boss is located on one side of the micro LED area and a sidewall of the boss is in contact with a sidewall of the first passivation layer.

19. A display device, wherein the display device comprises the integrated chip manufactured by the manufacturing method according to any one of claims 1 to 11, or the integrated chip according to any one of claims 12 to 18.