CN116936601A - Integrated chip, preparation method thereof and display device - Google Patents

Abstract

The present disclosure provides an integrated chip, a manufacturing method thereof, and a display device. The method includes: providing a substrate provided with a first passivation layer, wherein a micro LED area array is provided on the substrate, and each micro LED area in the micro LED area array is surrounded by the first passivation layer and exposes the substrate; Micro LED epitaxial wafers are formed in each micro LED area; each micro LED epitaxial wafer is etched to form a micro LED mesa structure array including bosses to obtain a first intermediate structure; a second passivation is provided on the first intermediate structure layer; a driving structure is provided on the second passivation layer on one side of the boss of each micro LED mesa structure; a first electrode metal layer and a second electrode metal layer are provided on each micro LED mesa structure, and a first electrode metal layer and a second electrode metal layer are provided on each driver A third electrode metal layer is structurally provided, wherein the second electrode metal layer and the third electrode metal layer are integrated.

Description

Integrated chip, preparation method thereof and display device

Technical field

The present disclosure relates to the technical field of semiconductor LEDs, and specifically, to an integrated chip, a manufacturing method thereof, and a display device.

Background technique

Micro-LED has the advantages of smaller size, higher resolution, higher brightness, higher luminous efficiency, lower power consumption and good controllability. Micro-LED display technology is particularly suitable for micro-display application fields such as virtual reality (VR) and augmented reality (AR). The bonding of Micro-LED and driver chips is mainly achieved by mass transfer or monolithic bonding. Low yield and prone to dead spots are the main problems that hinder its mass production. Therefore, it is a better solution to integrate Micro-LED with the driver chip so that the Micro-LED chip can be driven without bonding the Micro-LED to the driver chip.

However, in related technologies, there are still some problems in the single-substrate integration of Micro-LED and driver chips, making the formed integrated chip less reliable.

Contents of the invention

In order to solve the technical problems mentioned in the background art, the solution of the present disclosure provides an integrated chip, a manufacturing method thereof, and a display device.

According to an aspect of an embodiment of the present disclosure, an integrated chip manufacturing method is provided. The method includes: providing a substrate provided with a first passivation layer, wherein the substrate has an array of micro LED regions, and each micro LED region in the array of micro LED regions is surrounded and exposed by the first passivation layer Taking out the substrate; performing epitaxial growth in each micro LED area in the array of micro LED areas and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer includes a first semiconductor layer, a multi-quantum well structure and a second semiconductor layer; starting from the second semiconductor layer, each micro LED epitaxial wafer is etched to expose the first semiconductor layer to form a micro LED mesa structure array to obtain a third An intermediate structure, wherein each micro LED mesa structure in the array of micro LED mesa structures includes a boss; a second passivation layer is provided on the first intermediate structure; and a boss on each micro LED mesa structure is provided. A corresponding drive structure is provided on the second passivation layer on the first passivation layer on one side to obtain a second intermediate structure, wherein the drive structure includes a first drive electrode; for the second intermediate structure, in each A first electrode metal layer is provided on the exposed first semiconductor layer of each micro LED mesa structure, a second electrode metal layer is provided on the second semiconductor layer of each micro LED mesa structure, and a first electrode metal layer is provided on the first driver of each driving structure. A third electrode metal layer is provided on the electrode, wherein the second electrode metal layer provided on each micro LED mesa structure is integrated with the third electrode metal layer provided on the corresponding driving structure.

Further, a substrate provided with a first passivation layer is provided, wherein a micro LED area array is provided on the substrate, and each micro LED area in the micro LED area array is surrounded by the first passivation layer and exposed. The substrate includes: providing a substrate; setting a first passivation layer on the substrate; and etching the first passivation layer to expose the substrate to form a micro LED area array.

Further, the height of each micro LED epitaxial wafer in the micro LED epitaxial wafer array is flush with the height of the first passivation layer.

Further, for the second intermediate structure, a first electrode metal layer is provided on the exposed first semiconductor layer of each micro LED mesa structure, and a second electrode metal layer is provided on the second semiconductor layer of each micro LED mesa structure. The electrode metal layer and the third electrode metal layer are provided on the first driving electrode of each driving structure, wherein the second electrode metal layer provided on each micro LED mesa structure and the third electrode metal layer provided on the corresponding driving structure The integration includes: arranging a third passivation layer on the second intermediate structure; opening a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes starting from the third passivation layer. , so that each first contact hole exposes the first semiconductor layer of the corresponding micro LED mesa structure, each second contact hole exposes the second semiconductor layer on the boss of the corresponding micro LED mesa structure, and each third The contact hole exposes the first driving electrode of the corresponding driving structure; a first electrode metal layer is provided on the exposed first semiconductor layer, a second electrode metal layer is provided on the exposed second semiconductor layer, and a first electrode metal layer is provided on the exposed second semiconductor layer. A third electrode metal layer is provided on the first driving electrode, wherein the second electrode metal layer provided on each micro LED mesa structure is integrated with the third electrode metal layer provided on the corresponding driving structure.

Further, the driving structure further includes a second driving electrode, and the method further includes: opening a plurality of fourth contact holes starting from the third passivation layer, so that each fourth contact hole exposes a corresponding driving structure. a second driving electrode; and a fourth electrode metal layer is provided on the exposed second driving electrode.

Further, a corresponding driving structure is provided on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure includes a third passivation layer. A driving electrode includes: arranging an active layer on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure to obtain a third intermediate structure, wherein the active layer It includes a middle part and a first part and a second part located on both sides of the middle part; a dielectric layer is provided on the third middle structure; a third middle part is provided on the dielectric layer and corresponding to the active layer. Three driving electrodes; ion implantation is performed on the first part of the active layer to form the first driving electrode, and the second part is ion implanted to form the second driving electrode, and the middle part where ions are not implanted forms a conductive channel. .

Further, arranging an active layer on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure includes: arranging an amorphous silicon layer on the entire second passivation layer. ; Laser annealing the amorphous silicon layer to form a polysilicon layer; etching the polysilicon layer to form a second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure A polysilicon-based active layer is formed on the passivation layer.

Further, before disposing the second passivation layer on the first intermediate structure, the method further includes: disposing a current spreading layer on the second semiconductor layer of the boss, and disposing a current spreading layer on the first intermediate structure. The second passivation layer includes: arranging a second passivation layer on the first intermediate structure provided with the current expansion layer; arranging a second electrode metal layer on the second semiconductor layer of each micro LED mesa structure includes: A second electrode metal layer is provided on the current spreading layer.

Further, each micro LED epitaxial wafer is etched starting from the second semiconductor layer to expose the first semiconductor layer to form a micro LED mesa structure array to obtain a first intermediate structure, wherein the micro LED Each micro LED mesa structure in the mesa structure array includes a boss including: etching each micro LED epitaxial wafer starting from the second semiconductor layer to form the boss, so that each micro LED epitaxial wafer is located The side wall on one side of the boss is not etched.

Further, the driving structure includes a TFT chip, the first driving electrode is a source, the second driving electrode is a drain, the third driving electrode is a gate, and the first electrode metal layer is a cathode. Metal layer, the second electrode metal layer is an anode metal layer, the third electrode metal layer is a source metal layer, the fourth metal layer is a drain metal layer, the anode metal layer and the source The metal layers are connected into one.

Further, the micro LED epitaxial wafer further includes a buffer layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer, the buffer layer is located on the substrate and the between the first semiconductor layer, the third semiconductor layer between the buffer layer and the first semiconductor, and the fourth semiconductor layer between the first semiconductor layer and the multi-quantum well structure , the fifth semiconductor layer is located between the fourth semiconductor layer and the multiple quantum well structure, the sixth semiconductor layer is located between the second semiconductor layer and the multiple quantum well structure, and the third semiconductor layer is located between the second semiconductor layer and the multiple quantum well structure. Seven semiconductor layers are located above the second semiconductor layer and the substrate is a sapphire substrate, the buffer layer is an AlN layer or a GaN layer, the first semiconductor layer is an N-GaN layer, and the second semiconductor layer is P -GaN layer, the third semiconductor layer is a U-GaN layer, the fourth semiconductor layer is an N-AlGaN layer, the fifth semiconductor layer is InGa or GaN superlattice, and the sixth semiconductor layer is P -AlGaN layer, the seventh semiconductor layer is a P+-GaN layer.

According to another aspect of the present disclosure, an integrated chip is also provided. The integrated chip includes: a substrate; a first passivation layer, which is disposed on the substrate and includes a micro LED area array exposing the substrate; a micro LED mesa structure array, in which the micro LED mesa structure array Each micro LED mesa structure is disposed in a corresponding micro LED area in the array of micro LED areas and on the exposed substrate, wherein each micro LED mesa structure in the array of micro LED mesa structures includes a boss and The exposed first semiconductor layer, the boss includes a first semiconductor layer, a multi-quantum well structure and a second semiconductor layer; a second passivation layer, which is provided on the micro LED mesa structure array and the first semiconductor layer on; a driving structure, which is provided on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure, and the driving structure includes a first driving electrode; a first electrode a metal layer disposed on the exposed first semiconductor layer of each micro LED mesa structure; a second electrode metal layer disposed on the second semiconductor layer of each micro LED mesa structure; a third electrode metal layer , which is provided on the first driving electrode of each driving structure, wherein the second electrode metal layer provided on each micro LED mesa structure is integrated with the third electrode metal layer provided on the corresponding driving structure.

Further, the height of the boss is flush with the height of the first passivation layer.

Further, the integrated chip further includes: a third passivation layer disposed on the second passivation layer and the driving structure; a plurality of first contact holes, a plurality of second contact holes and a plurality of third passivation layers. Contact holes, each first contact hole exposes the first semiconductor layer of the corresponding micro LED mesa structure, each second contact hole exposes the second semiconductor layer on the boss of the corresponding micro LED mesa structure, and each third contact hole exposes the first semiconductor layer of the corresponding micro LED mesa structure. The three contact holes expose the first driving electrode of the corresponding driving structure; the first electrode metal layer is provided on the exposed first semiconductor layer through the first contact hole; the second electrode metal layer is provided through the second contact holes are provided on the exposed second semiconductor layer; a third electrode metal layer is provided on the exposed first driving electrode through the third contact hole, wherein the second electrode metal layer provided on each micro LED mesa structure The third electrode metal layer is integrated with the third electrode metal layer provided on the corresponding driving structure.

Further, the driving structure further includes a second driving electrode, and the integrated chip further includes: a plurality of fourth contact holes, each fourth contact hole exposing the second driving electrode of the corresponding driving structure; the fourth electrode metal A layer is disposed on the exposed second driving electrode through the fourth contact hole.

Further, the driving structure includes: an active layer, which is provided on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure, the active layer includes the first driving electrode, the second driving electrode and a conductive channel between the first driving electrode and the second driving electrode; a dielectric layer disposed on the active layer; a third A driving electrode is provided on the dielectric layer and corresponds to the position of the conductive channel of the active layer.

Further, the integrated chip further includes a current expansion layer, the current expansion layer is provided on the second semiconductor layer of the boss, and the second electrode metal layer is provided on the current expansion layer.

Further, the boss is located on one side of the micro LED area, and the side wall of the boss is in contact with the side wall of the first passivation layer.

According to yet another aspect of the embodiments of the present disclosure, a display device is also provided. The display device includes an integrated chip prepared by the above method or the above integrated chip.

By applying the technical solution of the present disclosure, a micro LED structure and a driving mechanism can be formed on the same substrate. There is no need to connect the micro LED structure and the driving structure through mass transfer or monolithic bonding to form a micro LED display module, thereby simplifying It improves the process and structure of micro LED display modules, thereby reducing yield decline and prone to dead spots, which is conducive to the mass production of micro LED display modules. Moreover, by applying the technical solution of the present disclosure, a micro LED area array surrounded by a passivation layer can be formed, and a corresponding micro LED epitaxial wafer array can be formed in the micro LED area array. The micro LED epitaxial wafer can be used to prepare a micro LED epitaxial wafer including a boss. The micro LED mesa structure, and then the driving structure is prepared on the passivation layer next to the micro LED mesa structure. Since the driving structure is set next to the micro LED mesa structure, the driving structure will not block the light emission of the micro LED mesa structure, thereby avoiding the need to make the micro LED The mesa structure uses a complex structure to emit light without being blocked, thereby simplifying the preparation process. In addition, by applying the technical solution of the present disclosure, a micro-LED area array surrounded by a passivation layer can be formed, and a corresponding array of micro-LED epitaxial wafers can be formed in the micro-LED area array, and micro-LEDs can be prepared through each micro-LED epitaxial wafer. structure, thereby avoiding the use of etching methods to define micro-LED light-emitting areas, that is, avoiding the formation of multiple micro-LED structures by etching one epitaxial wafer, thereby avoiding etching damage to the side walls of the formed micro-LED structures, Therefore, the reliability of the prepared integrated chip is improved.

Description of the drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are shown by way of illustration and not limitation, and like or corresponding reference numerals designate like or corresponding parts, wherein:

Figure 1 is a flow chart illustrating an integrated chip manufacturing method according to one embodiment of the present disclosure;

2 to 15 are schematic diagrams showing a manufacturing process flow of an integrated chip manufacturing method according to an embodiment of the present disclosure.

Detailed ways

It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other. The present disclosure will be described in detail below in conjunction with embodiments with reference to the accompanying drawings.

It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meanings commonly understood by one of ordinary skill in the art to which this application belongs.

For the convenience of description, spatially relative terms can be used here, such as "on...", "on...", "on the upper surface of...", "above", etc., to describe what is shown in the figure. The spatial relationship between one device or feature and other devices or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a feature in the figure is turned upside down, then one feature described as "above" or "on top of" other features or features would then be oriented "below" or "below" the other features or features. under other devices or structures". Thus, the exemplary term "over" may include both orientations "above" and "below." The device may be otherwise oriented, rotated 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

Now, exemplary embodiments according to the present disclosure will be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of these exemplary embodiments to those skilled in the art, and in the drawings, the layers are exaggerated for clarity. and the thickness of the region, and the same reference numerals are used to denote the same devices, and thus their descriptions will be omitted.

In related technologies, the way the Micro-LED structure is connected to the driving structure is generally to connect the Micro-LED chip to the driving structure through mass transfer or monolithic bonding. However, these two connection methods will cause pixel offset or pixel distortion. Damage, resulting in reduced yield and prone to dead spots, thus hindering the mass production of Micro-LEDs. Therefore, Micro-LED-driver integration that can use drivers to drive Micro-LEDs without requiring massive transfer or monolithic bonding is a better solution. However, when Micro-LED and driver are integrated, trace climbing is required when the electrodes are connected between the Micro-LED structure and the driver structure, thus reducing the reliability of the integrated chip. In addition, in some related technologies, the driving structure is arranged on the light emitting side of the micro LED structure. Therefore, in order to prevent the driving structure from blocking the light emitting of the micro LED structure, complex preparation processes are used, such as flipping or transferring the substrate.

The present disclosure provides an integrated chip preparation method. Referring to FIGS. 1 to 15 , FIG. 1 is a flow chart illustrating an integrated chip manufacturing method according to one embodiment of the present disclosure; FIG. 2 to 15 is a flow chart illustrating an integrated chip manufacturing method according to one embodiment of the present disclosure. Process flow diagram.

According to embodiments of the present disclosure, the pixel size in the micro-LED (Micro-LED) and driver integrated chip is generally less than or equal to 200 microns.

As shown in Figure 1, the integrated chip preparation method includes the following steps S101-S106.

Step S101: Provide a substrate provided with a first passivation layer, wherein a micro LED area array is provided on the substrate, and each micro LED area in the micro LED area array is surrounded by the first passivation layer and exposed. the substrate.

Step S102: Perform epitaxial growth in each micro LED area in the array of micro LED areas and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer includes a first semiconductor layer, Multiple quantum well structure and second semiconductor layer.

Step S103: Etch each micro LED epitaxial wafer starting from the second semiconductor layer to expose the first semiconductor layer to form a micro LED mesa structure array to obtain a first intermediate structure, wherein the micro LED Each micro LED mesa structure in the array of mesa structures includes a boss.

Step S104: Set a second passivation layer on the first intermediate structure.

Step S105: Set a corresponding driving structure on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure includes a third passivation layer. A driving electrode.

Step S106: For the second intermediate structure, a first electrode metal layer is provided on the exposed first semiconductor layer of each micro LED mesa structure, and a second electrode metal layer is provided on the second semiconductor layer of each micro LED mesa structure. The electrode metal layer and the third electrode metal layer are provided on the first driving electrode of each driving structure, wherein the second electrode metal layer provided on each micro LED mesa structure and the third electrode metal layer provided on the corresponding driving structure Connected as one.

According to this technical solution, a micro-LED structure and a driving mechanism can be formed on the same substrate. There is no need to connect the micro-LED structure and the driving structure through mass transfer or monolithic bonding to form a micro-LED display module, thus simplifying the process of micro-LED display. The process and structure of LED display modules further reduce yield decline and prone to dead spots, which is conducive to the mass production of micro LED display modules. Moreover, according to this technical solution, a micro-LED area array surrounded by a passivation layer can be formed, and a corresponding micro-LED epitaxial wafer array can be formed in the micro-LED area array. Micro-LEDs including bosses can be prepared through the micro-LED epitaxial wafers. Mesa structure, and then prepare a driving structure on the passivation layer next to the micro LED mesa structure. Since the driving structure is set next to the micro LED mesa structure, the driving structure will not block the light emission of the micro LED mesa structure, thereby avoiding the need to make the micro LED mesa structure The light output is not blocked and adopts a complex structure, thereby simplifying the preparation process. In addition, according to this technical solution, a micro LED area array surrounded by a passivation layer can be formed, and a corresponding micro LED epitaxial wafer array can be formed in the micro LED area array, and a micro LED structure can be prepared through each micro LED epitaxial wafer, Therefore, it is possible to avoid using etching methods to define micro-LED light-emitting areas, that is, to avoid forming multiple micro-LED structures by etching one epitaxial wafer, thereby avoiding etching damage to the side walls of the formed micro-LED structures, thus improving the efficiency of the micro-LED structure. The reliability of the integrated chips prepared.

In step S101, a substrate provided with a first passivation layer may be provided, wherein a micro LED area array is provided on the substrate, and each micro LED area in the micro LED area array is surrounded by the first passivation layer and The substrate is exposed.

According to an embodiment of the present disclosure, a substrate provided with a first passivation layer is provided, wherein an array of micro LED areas is provided on the substrate, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer And exposing the substrate may include: providing a substrate; providing a first passivation layer on the substrate; and etching the first passivation layer to expose the substrate to form a micro LED area array.

In this embodiment, in order to prepare an integrated chip, a substrate may first be obtained. The micro LED structure and driving structure included in the integrated chip are prepared on the same substrate.

Furthermore, the substrate can be a sapphire substrate, a single crystal silicon substrate, a SiC substrate, etc., and of course it can also be any other transparent or opaque substrate, which is not limited here.

Referring to Figures 2-15, Figure 2 illustrates a side view of a substrate 101 according to one embodiment of the present disclosure.

After the substrate is obtained, a passivation layer can be provided on the substrate.

Referring to FIGS. 2-15 , FIG. 3 shows a side view of the first passivation layer 102 provided on the substrate 101 according to one embodiment of the present disclosure. As shown in FIG. 3 , the first passivation layer 102 can be deposited on the substrate 101 using plasma enhanced chemical vapor deposition (PECVD).

After the first passivation layer is provided, a micro LED area array to be prepared as a micro LED structure array can be etched on the first passivation layer.

Referring to FIGS. 2-15 , FIG. 4 illustrates a side view of the micro LED region 1021 formed in the first passivation layer 102 according to one embodiment of the present disclosure. As shown in Figure 4, for reasons of simplicity and clarity, this figure only shows one micro-LED area 1021. In practical applications, the number of micro-LED areas 1021 can be based on the actual required micro-LED structure (light-emitting structure). quantity to determine. In this embodiment, glue can be applied on the first passivation layer 102 to photo-etch the pattern of the micro-LED area, and an inductively coupled plasma (ICP) etching method can be used to etch the micro-LED area 1021 to remove light. After etching, the structure shown in Figure 4 is formed. Among them, the micro LED area 1021 exposes a part of the substrate 101 .

In step S102, epitaxial growth may be performed in each micro LED area in the array of micro LED areas and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer includes a first Semiconductor layer, multiple quantum well structure and second semiconductor layer.

According to embodiments of the present disclosure, epitaxial growth can be performed on an exposed substrate for each micro LED area to form a micro LED epitaxial wafer. Further, each micro LED epitaxial wafer may include a first semiconductor layer, a multi-quantum well structure and a second semiconductor layer in order from bottom to top.

According to an embodiment of the present disclosure, the height of each micro LED epitaxial wafer in the array of micro LED epitaxial wafers is flush with the height of the first passivation layer. The height of each layer of the micro LED epitaxial wafer can be preset so that the total height of the micro LED epitaxial wafer is flush with the height of the first passivation layer. According to this technical solution, the height of each micro LED epitaxial wafer in the corresponding micro LED epitaxial wafer array formed in the micro LED area array can be flush with the height of the passivation layer, so that the micro LED epitaxial wafer can be prepared A micro LED mesa structure including a boss such that the height of the boss is flush with the height of the passivation layer, so that the electrodes of the drive structure subsequently prepared on the passivation layer next to the micro LED mesa structure are connected to the electrodes on the boss At this time, the connection trace creep can be reduced, thereby improving the reliability of the prepared integrated chip.

Further, the epitaxial wafer may further include a buffer layer located between the substrate and the first semiconductor layer. In addition, the epitaxial wafer may further include a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer. The third semiconductor layer is located between the buffer layer and the first semiconductor layer. The fourth semiconductor layer is located between the first semiconductor layer and the multiple quantum well structure, and the fifth semiconductor layer is located between the fourth semiconductor layer and the multiple quantum well structure, The sixth semiconductor layer is located between the second semiconductor layer and the multiple quantum well structure, and the seventh semiconductor layer is located above the second semiconductor layer. The buffer layer may be an AlN layer or a GaN layer, the first semiconductor layer may be an N-GaN layer, the second semiconductor layer may be a P-GaN layer, and the third semiconductor layer may be a U-GaN layer. , the fourth semiconductor layer may be an N-AlGaN layer, the fifth semiconductor layer may be an InGa or GaN superlattice, the sixth semiconductor layer may be a P-AlGaN layer, and the seventh semiconductor layer may be P+-GaN layer.

Referring to FIGS. 2-15 , FIG. 5 shows a side view of the micro LED epitaxial wafer 10 formed in the micro LED area 1021 according to one embodiment of the present disclosure. As shown in FIG. 5 , the micro LED epitaxial wafer 10 includes a buffer layer 106 , a first semiconductor layer 103 , a multi-quantum well structure 104 and a second semiconductor layer 105 in order from bottom to top. The buffer layer 106 may be an AlN layer or a GaN layer, the first semiconductor layer 103 may be an N-GaN layer, and the second semiconductor layer 105 may be a P-GaN layer. In addition, the epitaxial wafer 10 can be deposited layer by layer in the micro LED area 1021 and on the substrate 101 using a metal-organic chemical vapor deposition (MOCVD) method.

In step S103, each micro LED epitaxial wafer can be etched starting from the second semiconductor layer to expose the first semiconductor layer to form a micro LED mesa structure array to obtain a first intermediate structure, wherein the Each micro LED mesa structure in the array of micro LED mesa structures includes a boss.

According to embodiments of the present disclosure, after the micro LED epitaxial wafer is formed, it can be etched to obtain a micro LED mesa structure including bosses.

Further, each micro LED epitaxial wafer is etched starting from the second semiconductor layer to expose the first semiconductor layer to form a micro LED mesa structure array to obtain a first intermediate structure, wherein the micro LED Each micro LED mesa structure in the mesa structure array includes a boss including: etching each micro LED epitaxial wafer starting from the second semiconductor layer to form the boss, so that each micro LED epitaxial wafer is located The side wall on one side of the boss is not etched. By reducing the etching of the side walls of the micro LED epitaxial wafer, the possibility of damage to the side walls of the micro LED epitaxial wafer can be reduced, thereby further improving the reliability of the prepared integrated chip.

Further, referring to FIGS. 2 to 15 , FIG. 6 shows a schematic side cross-sectional view of the micro LED mesa structure 20 etched from the micro LED epitaxy.

Specifically, photoresist can be applied on the micro LED epitaxial wafer 10 and the first passivation layer 102 first, and then the photoresist can be exposed, developed and baked to photoetch the pattern of the micro LED mesa structure. Subsequently, the pattern etching obtained by photolithography is mapped to the micro LED epitaxial wafer through inductively coupled plasma etching (ICP) to expose the surface layer of the first semiconductor layer 103, and then the photoresist is removed, thereby forming a micro micro LED epitaxial wafer including the boss 201. The LED mesa structure 20 forms the first intermediate structure 1 as shown in FIG. 6 . As shown in Figure 6, using a preset mask, the etching of the micro LED epitaxial wafer only involves one side wall in the figure, that is, the boss 201 is formed on one side of the micro LED mesa structure 20, and the boss 201 is formed on one side of the micro LED mesa structure 20. The sidewall 201 in contact with the first passivation layer 102 (one sidewall of the epitaxial wafer) is not etched, thereby reducing etching of the sidewall of the epitaxial wafer and reducing the possibility of damage to the sidewall of the micro LED epitaxial wafer.

In step S104, a second passivation layer may be provided on the first intermediate structure.

According to an embodiment of the present disclosure, before disposing the second passivation layer on the first intermediate structure, the method may further include: disposing a current spreading layer on the second semiconductor layer of the boss. Therefore, providing the second passivation layer on the first intermediate structure may include: providing a second passivation layer on the first intermediate structure provided with the current spreading layer. Wherein, the current spreading layer may include an indium tin oxide layer. By providing a current spreading layer, the contact resistance between the electrode layer and the semiconductor layer can be improved and the light extraction efficiency can be improved.

Referring to FIGS. 2 to 15 , FIG. 7 shows a side cross-sectional view of the current spreading layer 107 provided on the second semiconductor layer 105 on the boss 201 in the first intermediate structure 1 . Specifically, as shown in FIG. 7 , photolithography and magnetron sputtering methods can be used to set the current spreading layer 107 on the second semiconductor layer 105 of the boss 201 , and then use a rapid annealing technology (RTA) to perform annealing treatment, so that the third A good ohmic contact is formed between the two semiconductor layers 105 and the current spreading layer 107 .

Referring to FIGS. 2-15 , FIG. 8 shows a side view of the second passivation layer 108 provided on the first intermediate structure 1 provided with the current spreading layer 107 according to one embodiment of the present disclosure. As shown in FIG. 8 , plasma enhanced chemical vapor deposition (PECVD) may be used to deposit the second passivation layer 108 on the first intermediate structure 1 provided with the current spreading layer 107 .

In step S105, a corresponding driving structure can be provided on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure The structure includes a first drive electrode.

According to embodiments of the present disclosure, a driving structure may be disposed on the second passivation layer on the first passivation layer next to the boss of each micro LED mesa structure, and the driving structure thus formed will not be located on the micro LED mesa structure directly above the micro LED table structure. In addition, the driving structure may further include a second driving electrode.

According to an embodiment of the present disclosure, a corresponding driving structure is provided on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure to obtain a second intermediate structure, wherein the The driving structure including the first driving electrode may include: arranging an active layer on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure to obtain a third intermediate structure, wherein The active layer includes a middle part and a first part and a second part located on both sides of the middle part; a dielectric layer is provided on the third middle structure; on the dielectric layer and corresponding to the active layer The middle part of the active layer is provided with a third driving electrode; the first part of the active layer is ion implanted to form the first driving electrode, and the second part is ion implanted to form the second driving electrode, and the middle part of the active layer is not implanted with ions. A conductive channel is partially formed.

Further, arranging an active layer on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure includes: arranging an amorphous silicon layer on the entire second passivation layer. ; Laser annealing the amorphous silicon layer to form a polysilicon layer; etching the polysilicon layer to form a second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure A polysilicon-based active layer is formed on the passivation layer.

According to an embodiment of the present disclosure, the driving structure may include a TFT chip, the first driving electrode is a source electrode, the second driving electrode is a drain electrode, and the third driving electrode is a gate electrode. The TFT chip can be any suitable structure such as a top gate structure or a bottom gate structure, and the driving structure can also be other driving chips, which are not limited here.

Referring to FIGS. 2-15 , FIG. 9 shows a side cross-sectional view of an active layer 109 , for example based on polysilicon, disposed on the second semiconductor layer 108 . As shown in FIG. 9 , the active layer 109 includes a middle portion 1092 and a first portion 1091 and a second portion 1093 located on both sides of the middle portion 1092 . Specifically, an amorphous silicon layer, for example, may be deposited on the entire second passivation layer 108 by plasma enhanced chemical vapor deposition (PECVD), and then laser annealing is performed on the amorphous silicon layer to form a polysilicon layer, and then photolithography is used. and etching to pattern the polysilicon layer, thereby forming a polysilicon-based second passivation layer on the first passivation layer on the boss side of each micro LED mesa structure as shown in Figure 4 Active layer 109, thereby obtaining the third intermediate structure as shown in Figure 9.

Referring to FIGS. 2-15 , FIG. 10 shows a side cross-sectional view of the dielectric layer 110 disposed on the third intermediate structure as shown in FIG. 9 . As shown in FIG. 10 , a dielectric layer 110 may be deposited on the third intermediate structure by plasma enhanced chemical vapor deposition (PECVD). The dielectric layer may be such as a silicon dioxide layer, an aluminum oxide layer, or a silicon nitride layer. gate oxide layer.

Referring to FIGS. 2-15 , FIG. 11 shows a side cross-sectional view of the third driving electrode 111 disposed on the dielectric layer 110 . As shown in FIG. 11 , a third driving electrode 111 may be disposed on the dielectric layer 110 and corresponding to the middle portion 1092 of the active layer 109 through plasma enhanced chemical vapor deposition (PECVD). The third driving electrode is located above the middle portion 1092, and the third driving electrode may be a gate electrode, for example.

Referring to FIGS. 2-15 , FIG. 12 shows a side cross-sectional view of the first driving electrode 1094 and the second driving electrode 1095 . As shown in FIG. 12 , ion implantation is performed on the first portion 1091 of the active layer 109 to form the first driving electrode 1094 , and the second portion 1092 is ion implanted to form the second driving electrode 1095 . The middle part 1093 forms a conductive channel, so that the driving structure is prepared, and the second middle structure 2 shown in FIG. 12 is obtained. The first driving electrode 1094 may be, for example, a source electrode, and the second driving electrode 1095 may be, for example, a drain electrode.

In step S106, for the second intermediate structure, a first electrode metal layer may be disposed on the exposed first semiconductor layer of each micro LED mesa structure, and on the second semiconductor layer of each micro LED mesa structure. A second electrode metal layer is provided and a third electrode metal layer is provided on the first driving electrode of each driving structure, wherein the second electrode metal layer provided on each micro LED mesa structure is consistent with the third electrode metal layer provided on the corresponding driving structure. The electrode metal layers are connected into one body.

According to embodiments of the present disclosure, after the driving structure is prepared, electrodes may be provided for the micro LED mesa structure and connected to electrodes of the driving structure.

Specifically, for the second intermediate structure, a first electrode metal layer is provided on the exposed first semiconductor layer of each micro LED mesa structure, and a second electrode metal layer is provided on the second semiconductor layer of each micro LED mesa structure. The electrode metal layer and the third electrode metal layer are provided on the first driving electrode of each driving structure, wherein the second electrode metal layer provided on each micro LED mesa structure and the third electrode metal layer provided on the corresponding driving structure The integration includes: arranging a third passivation layer on the second intermediate structure; opening a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes starting from the third passivation layer. , so that each first contact hole exposes the first semiconductor layer of the corresponding micro LED mesa structure, each second contact hole exposes the second semiconductor layer on the boss of the corresponding micro LED mesa structure, and each third The contact hole exposes the first driving electrode of the corresponding driving structure; a first electrode metal layer is provided on the exposed first semiconductor layer, a second electrode metal layer is provided on the exposed second semiconductor layer, and a first electrode metal layer is provided on the exposed second semiconductor layer. A third electrode metal layer is provided on the first driving electrode, wherein the second electrode metal layer provided on each micro LED mesa structure is integrated with the third electrode metal layer provided on the corresponding driving structure.

According to an embodiment of the present disclosure, when the driving structure further includes a second driving electrode, the method further includes: opening a plurality of fourth contact holes starting from the third passivation layer, such that each fourth contact hole The second driving electrode of the corresponding driving structure is exposed; and a fourth electrode metal layer is provided on the exposed second driving electrode.

According to an embodiment of the present disclosure, when arranging a current expansion layer on the second semiconductor layer of the boss, arranging a second electrode metal layer on the second semiconductor layer of each micro LED mesa structure includes: A second electrode metal layer is provided on the layer.

According to an embodiment of the present disclosure, the first electrode metal layer is a cathode metal layer, the second electrode metal layer is an anode metal layer, the third electrode metal layer is a source metal layer, and the fourth metal layer It is a drain metal layer, and the anode metal layer and the source metal layer are integrated.

Referring to FIGS. 2-15 , FIG. 13 shows a side cross-sectional view of the third passivation layer 112 provided on the second intermediate structure 2 . As shown in FIG. 13 , the third passivation layer 112 may be deposited on the second intermediate structure 2 by plasma enhanced chemical vapor deposition (PECVD).

Referring to FIGS. 2-15 , FIG. 14 shows a side cross-sectional view of the first contact hole 113 , the second contact hole 114 , the third contact hole 115 and the fourth contact hole 116 . As shown in FIG. 14 , after depositing the third passivation layer 112 , glue is applied on the third passivation layer 112 and photolithography is performed to form the first contact hole 113 , the second contact hole 114 , the third contact hole 115 and the fourth contact hole 115 . For the pattern of the contact hole 116, the first contact hole 113, the second contact hole 114, the third contact hole 115 and the fourth contact hole 116 are etched using an inductively coupled plasma (ICP) etching method. After removing the photoresist, the following is formed: The structure shown in Figure 14. Wherein, each first contact hole 113 passes through the third passivation layer 112, the dielectric layer 110 and the second passivation layer 108 to expose the first semiconductor layer 103 and each second contact hole 114 of the corresponding micro LED mesa structure. The current spreading layer 107 on the boss of the corresponding micro LED mesa structure is exposed through the third passivation layer 112, the dielectric layer 110 and the second passivation layer 108, and each third contact hole 115 passes through the third passivation layer 112. The layer 112 and the dielectric layer 110 expose the first driving electrode 1094 such as the source electrode of the corresponding driving structure, and each fourth contact hole 116 passes through the third passivation layer 112 and the dielectric layer 110 to expose the corresponding driving structure. A second drive electrode 1095 such as a drain electrode.

Referring to FIGS. 2-15 , FIG. 15 shows a side view of the first electrode metal layer 117 , the second electrode metal layer 118 , the third electrode metal layer 119 and the fourth electrode metal layer 120 . Specifically, as shown in FIG. 15 , photolithography and electron beam evaporation methods can be used to form layers on the third passivation layer 112 and the exposed first semiconductor layer 103 , current spreading layer 107 , first driving electrode 1094 and second driving electrode 1094 . A metal layer is deposited on the electrode 1095, and then the photoresist and excess metal are removed using a lift-off process to obtain the first electrode metal layer 117, the second electrode metal layer 118, the third electrode metal layer 119 and the fourth electrode. Metal layer 120. The first electrode metal layer is, for example, a cathode metal layer, and the second electrode metal layer is, for example, an anode metal layer. The second electrode metal layer 118, such as the anode metal layer, is connected to a third electrode metal layer, such as a source, provided on the corresponding driving structure. The electrode metal layers 119 are integrated into one body, thereby obtaining the integrated chip 3 as shown in FIG. 15 . The second electrode metal layer 118 may be an anode metal layer that serves as the anode of the micro LED mesa structure, and the first electrode metal layer 117 may be a cathode metal layer that serves as the cathode of the micro LED mesa structure. The cathode is disposed on the exposed first semiconductor layer 103. Although the cathode is disposed in a valley, all cathodes disposed on the micro LED mesa structure can be connected together to ground, so there is no need to climb out. In addition, as shown in Figure 15, since the height of the first driving electrode 1094 of the driving structure is basically flush with the current spreading layer 107 on the micro LED mesa structure, the electrode metal layer is used to spread the first driving electrode 1094 and the current. When layer 107 is connected, trace creep is greatly reduced, which is beneficial to the reliability of the integrated chip.

Thus, the integrated chip is prepared, and FIG. 15 shows the integrated chip 3 prepared according to an embodiment of the present disclosure.

The present disclosure also provides an integrated chip.

As shown in Figures 2 to 15, the integrated chip 3 includes: a substrate 101; a first passivation layer 102, which is provided on the substrate 101 and includes a micro LED area array exposing the substrate; micro LEDs Mesa structure array, each micro LED mesa structure 20 in the micro LED mesa structure array is disposed in a corresponding micro LED area 1021 in the micro LED area array and on the exposed substrate 101, wherein the micro Each micro-LED mesa structure 20 in the LED mesa structure array includes a boss 201 and an exposed first semiconductor layer 103. The boss 201 includes the first semiconductor layer 103, the multi-quantum well structure 104 and the second semiconductor layer 105; A second passivation layer 108 is provided on the micro LED mesa structure array and the first semiconductor layer 102; a driving structure is provided on the third side of the boss 201 of each micro LED mesa structure 20. A passivation layer 102 is on the second passivation layer 108, and the driving structure includes a first driving electrode 1094; a first electrode metal layer 117 disposed on the exposed third of each micro-LED mesa structure 20. a semiconductor layer 103; a second electrode metal layer 118, which is disposed on the second semiconductor layer 105 of the boss 201 of each micro LED mesa structure 20; a third electrode metal layer 119, which is disposed on each driving structure On the first driving electrode 1094, the second electrode metal layer 118 provided on each micro LED mesa structure 20 is integrated with the third electrode metal layer 119 provided on the corresponding driving structure.

According to an embodiment of the present disclosure, the height of the boss 201 is flush with the height of the first passivation layer 102 .

According to an embodiment of the present disclosure, the boss 201 includes a first semiconductor layer 103, a multi-quantum well structure 104 and a second semiconductor layer 105 in order from bottom to top.

According to an embodiment of the present disclosure, the integrated chip 3 further includes: a third passivation layer 112 disposed on the second passivation layer 108 and the driving structure; a plurality of first contact holes 113, a plurality of Two contact holes 114 and a plurality of third contact holes 115, each first contact hole 113 exposes the first semiconductor layer 103 of the corresponding micro LED mesa structure 20, and each second contact hole 114 exposes the corresponding micro LED mesa. The second semiconductor layer 105 on the boss 201 of the structure 20 and each third contact hole 115 exposes the first driving electrode 1094 of the corresponding driving structure; the first electrode metal layer 117 is disposed through the first contact hole 113 disposed on the exposed first semiconductor layer 103; a second electrode metal layer 118, which is disposed on the exposed second semiconductor layer 105 through the second contact hole 114; and a third electrode metal layer 119, which passes through the third contact hole 115 is provided on the exposed first driving electrode 1094, wherein the second electrode metal layer 118 provided on each micro LED mesa structure 20 is integrated with the third electrode metal layer 119 provided on the corresponding driving structure.

According to an embodiment of the present disclosure, the driving structure further includes a second driving electrode 1095, and the integrated chip 3 further includes: a plurality of fourth contact holes 116, each fourth contact hole 116 exposing the corresponding third driving structure. Two driving electrodes 1095; a fourth electrode metal layer 120, which is disposed on the exposed second driving electrode 1095 through the fourth contact hole 116.

According to an embodiment of the present disclosure, the driving structure includes: an active layer 109 disposed on the first passivation layer 102 on one side of the boss 201 of each micro LED mesa structure 20 and a second passivation layer 108, the active layer 109 includes the first driving electrode 1094, the second driving electrode 1095 and a conductive channel located between the first driving electrode 1094 and the second driving electrode 1095; dielectric A layer 110 is provided on the active layer 109; a third driving electrode 111 is provided on the dielectric layer 110 and corresponds to the position of the conductive channel of the active layer 109.

According to an embodiment of the present disclosure, the integrated chip 3 further includes a current expansion layer 107 disposed on the second semiconductor layer 105 of the boss 201 , and the second electrode metal layer 118 is disposed on on the current spreading layer 107 .

According to an embodiment of the present disclosure, the boss 201 is located on one side of the micro LED area 1021 , and the side wall of the boss 201 is in contact with the side wall of the first passivation layer 102 .

It is worth noting that any relevant description of the integrated chip structure in the above integrated chip preparation method (including but not limited to technical features and their functions, explanations, etc.) can be applied to the integrated chip of the present disclosure.

The present disclosure also provides a display device. The display device includes the above integrated chip. The display device can be applied to electronic equipment to implement AR, VR, extended reality (XR), mixed reality (MixedReality, MR) and other technologies. For example, the display device may be a projection part of an electronic device, such as a projector, a Head Up Display (HUD), etc.; for another example, the display device may also be a display part of an electronic device, for example, the electronic device may include: Smartphones, smart watches, laptops, tablets, driving recorders, navigators, head-mounted devices and any other device with a display.

It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, it will be understood that when the terms "comprises" and/or "includes" are used in this specification, they indicate There are features, steps, operations, means, components and/or combinations thereof.

It will be understood that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present application, the size of the serial numbers of the above steps/processes does not mean the order of execution. The execution order of each step/process should be determined by its function and internal logic, and should not be The implementation process of the embodiments of this application does not constitute any limitations. Moreover, the above-mentioned serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the application described herein, for example, can be practiced in sequences other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.

The above descriptions are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this disclosure shall be included in the protection scope of this disclosure.

Claims (19)

1. A method of integrated chip fabrication, wherein the method comprises:

providing a substrate provided with a first passivation layer, wherein the substrate is provided with an array of micro LED areas, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate;

performing epitaxial growth in each micro LED region in the array of micro LED regions and on the exposed substrate to form an array of micro LED epitaxial wafers, and each micro LED epitaxial wafer comprising a first semiconductor layer, a multiple quantum well structure and a second semiconductor layer;

etching each micro LED epitaxial wafer from the second semiconductor layer, exposing the first semiconductor layer to form a micro LED mesa structure array, and obtaining a first intermediate structure, wherein each micro LED mesa structure in the micro LED mesa structure array comprises a boss;

Disposing a second passivation layer on the first intermediate structure;

setting a corresponding driving structure on a second passivation layer on the first passivation layer at one side of a boss of each micro LED mesa structure to obtain a second intermediate structure, wherein the driving structure comprises a first driving electrode;

for the second intermediate structure, a first electrode metal layer is arranged on the exposed first semiconductor layer of each micro LED mesa structure, a second electrode metal layer is arranged on the second semiconductor layer of each micro LED mesa structure, and a third electrode metal layer is arranged on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

2. The integrated chip manufacturing method according to claim 1, wherein providing a substrate provided with a first passivation layer, wherein the substrate has an array of micro LED areas thereon, and each micro LED area in the array of micro LED areas is surrounded by the first passivation layer and exposes the substrate comprises:

providing a substrate;

disposing a first passivation layer on the substrate;

and etching the first passivation layer to expose the substrate, so as to form a micro LED area array.

3. The integrated chip manufacturing method of claim 1, wherein a height of each micro LED epitaxial wafer in the array of micro LED epitaxial wafers is flush with a height of the first passivation layer.

4. The integrated chip manufacturing method according to claim 1, wherein for the second intermediate structure, disposing a first electrode metal layer on the exposed first semiconductor layer of each micro LED mesa, disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa, disposing a third electrode metal layer on the first driving electrode of each driving structure, wherein the disposing the second electrode metal layer on each micro LED mesa integrally with the disposing the third electrode metal layer on the corresponding driving structure comprises:

disposing a third passivation layer on the second intermediate structure;

starting from the third passivation layer, a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes are formed, so that each first contact hole exposes a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposes a second semiconductor layer on a boss of the corresponding micro LED mesa, and each third contact hole exposes a first driving electrode of the corresponding driving structure;

The first electrode metal layer is arranged on the exposed first semiconductor layer, the second electrode metal layer is arranged on the exposed second semiconductor layer, and the third electrode metal layer is arranged on the exposed first driving electrode, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

5. The integrated chip manufacturing method according to claim 4, wherein the driving structure further includes a second driving electrode, the method further comprising:

a plurality of fourth contact holes are formed from the third passivation layer, so that each fourth contact hole exposes a second driving electrode of a corresponding driving structure;

a fourth electrode metal layer is disposed on the exposed second driving electrode.

6. The method of claim 5, wherein a corresponding driving structure is disposed on a second passivation layer on the first passivation layer on a boss side of each micro LED mesa, resulting in a second intermediate structure, wherein the driving structure includes a first driving electrode including:

an active layer is arranged on a second passivation layer on the first passivation layer on one side of a boss of each micro LED mesa structure to obtain a third intermediate structure, wherein the active layer comprises a middle part, and a first part and a second part which are positioned on two sides of the middle part;

A dielectric layer is arranged on the third intermediate structure;

a third driving electrode is arranged on the dielectric layer and corresponds to the middle part of the active layer;

ion implantation is performed on a first portion of the active layer to form a first driving electrode, and ion implantation is performed on a second portion to form a second driving electrode, and the intermediate portion in which ions are not implanted forms a conductive channel.

7. The integrated chip manufacturing method according to claim 6, wherein disposing an active layer on the second passivation layer on the first passivation layer on the mesa side of each micro LED mesa comprises:

disposing an amorphous silicon layer over the entire second passivation layer;

carrying out laser annealing on the amorphous silicon layer to form a polycrystalline silicon layer;

and etching the polycrystalline silicon layer to form an active layer based on polycrystalline silicon on the second passivation layer on the first passivation layer at the boss side of each micro LED mesa structure.

8. The integrated chip manufacturing method of claim 1, wherein prior to disposing a second passivation layer on the first intermediate structure, the method further comprises: a current spreading layer is provided on the second semiconductor layer of the mesa,

Disposing a second passivation layer on the first intermediate structure includes: a second passivation layer is provided on the first intermediate structure provided with the current spreading layer,

disposing a second electrode metal layer on the second semiconductor layer of each micro LED mesa structure comprises: and a second electrode metal layer is arranged on the current expansion layer.

9. The integrated chip manufacturing method of claim 1, wherein etching each micro LED epitaxial wafer from the second semiconductor layer exposes the first semiconductor layer to form an array of micro LED mesas resulting in a first intermediate structure, wherein each micro LED mesa in the array of micro LED mesas comprises a boss comprising: and starting to etch each micro LED epitaxial wafer from the second semiconductor layer to form the boss, so that the side wall of each micro LED epitaxial wafer, which is positioned on one side of the boss, is not etched.

10. The integrated chip manufacturing method according to claim 6, wherein the driving structure includes a TFT chip, the first driving electrode is a source electrode, the second driving electrode is a drain electrode, the third driving electrode is a gate electrode, the first electrode metal layer is a cathode metal layer, the second electrode metal layer is an anode metal layer, the third electrode metal layer is a source metal layer, the fourth metal layer is a drain metal layer, and the anode metal layer is integrally connected with the source metal layer.

11. The integrated chip manufacturing method according to any one of claims 1 to 10, wherein the micro LED epitaxial wafer further comprises a buffer layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer, the buffer layer being located between the substrate and the first semiconductor layer, the third semiconductor layer being located between the buffer layer and the first semiconductor layer, the fourth semiconductor layer being located between the first semiconductor layer and the multiple quantum well structure, the fifth semiconductor layer being located between the fourth semiconductor layer and the multiple quantum well structure, the sixth semiconductor layer being located between the second semiconductor layer and the multiple quantum well structure, the seventh semiconductor layer being located above the second semiconductor layer and the substrate being a blue substrate, the buffer layer being an AlN layer or an N-layer, the second semiconductor layer being a P-layer, the third semiconductor layer being a P-GaN layer, the fifth semiconductor layer being a GaN layer, the GaN layer.

12. An integrated chip, wherein the integrated chip comprises:

a substrate;

a first passivation layer disposed on the substrate and including an array of micro LED areas exposing the substrate;

a micro LED mesa array, each micro LED mesa in the micro LED mesa array disposed in a corresponding micro LED region in the micro LED region array and on the exposed substrate, wherein each micro LED mesa in the micro LED mesa array comprises a mesa comprising a first semiconductor layer, a multiple quantum well structure, and a second semiconductor layer and an exposed first semiconductor layer;

a second passivation layer disposed on the array of micro LED mesas and the first semiconductor layer;

a driving structure disposed on the second passivation layer on the first passivation layer on the boss side of each micro LED mesa, and including a first driving electrode;

a first electrode metal layer disposed on the exposed first semiconductor layer of each micro LED mesa;

a second electrode metal layer disposed on the second semiconductor layer of each micro LED mesa;

And the third electrode metal layer is arranged on the first driving electrode of each driving structure, wherein the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

13. The integrated chip of claim 12, wherein a height of the boss is flush with a height of the first passivation layer.

14. The integrated chip of claim 12, wherein the integrated chip further comprises:

a third passivation layer disposed on the second passivation layer and the driving structure;

a plurality of first contact holes, a plurality of second contact holes and a plurality of third contact holes, each first contact hole exposing a first semiconductor layer of a corresponding micro LED mesa, each second contact hole exposing a second semiconductor layer on a boss of a corresponding micro LED mesa and each third contact hole exposing a first drive electrode of a corresponding drive structure;

a first electrode metal layer disposed on the exposed first semiconductor layer through the first contact hole;

a second electrode metal layer disposed on the exposed second semiconductor layer through the second contact hole;

A third electrode metal layer disposed on the exposed first driving electrode through a third contact hole,

the second electrode metal layer arranged on each micro LED mesa structure is connected with the third electrode metal layer arranged on the corresponding driving structure into a whole.

15. The integrated chip of claim 14, wherein the drive structure further comprises a second drive electrode, the integrated chip further comprising:

a plurality of fourth contact holes, each exposing the second driving electrode of the corresponding driving structure;

and a fourth electrode metal layer disposed on the exposed second driving electrode through the fourth contact hole.

16. The integrated chip of claim 15, wherein the driving structure comprises:

an active layer disposed on the second passivation layer on the first passivation layer at the boss side of each micro LED mesa structure, the active layer including the first driving electrode, the first driving electrode

A second drive electrode and a conductive channel between the first drive electrode and the second drive electrode;

a dielectric layer disposed on the active layer;

and a third driving electrode disposed on the dielectric layer and corresponding to a position of the conductive channel of the active layer.

17. The integrated chip of claim 12, further comprising a current spreading layer disposed on the second semiconductor layer of the mesa, the second electrode metal layer disposed on the current spreading layer.

18. The integrated chip of claim 12, wherein the boss is located on one side of the micro LED area and a sidewall of the boss is in contact with a sidewall of the first passivation layer.

19. A display device, wherein the display device comprises the integrated chip manufactured by the manufacturing method according to any one of claims 1 to 11, or the integrated chip according to any one of claims 12 to 18.