CN115939271A

CN115939271A - Preparation method of micro LED device, micro LED device and display device

Info

Publication number: CN115939271A
Application number: CN202211483373.XA
Authority: CN
Inventors: 符民; 张珂
Original assignee: Shenzhen Stan Technology Co Ltd
Current assignee: Shenzhen Stan Technology Co Ltd
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2023-04-07
Anticipated expiration: 2042-11-24
Also published as: CN115939271B

Abstract

The disclosure provides a preparation method of a micro LED device, the micro LED device and a display device. The method comprises the following steps: providing a micro LED epitaxial wafer, wherein the epitaxial wafer comprises a first semiconductor layer, a multi-layer quantum well structure and a second semiconductor layer; etching from the second semiconductor layer until the first semiconductor layer is exposed to obtain a mesa structure, wherein the mesa structure comprises a plurality of bosses; providing a metal layer on each boss and on the exposed first semiconductor layer, resulting in a first intermediate structure; arranging an extinction layer on the first intermediate structure, and forming a plurality of contact holes on the extinction layer to expose the metal layer; arranging a metal block on the exposed metal layer to obtain a micro LED chip array; and inversely bonding the micro LED chip array and the driving substrate through the metal block to obtain the micro LED device. According to the scheme, the optical crosstalk phenomenon and the peripheral light leakage phenomenon can be improved.

Description

Preparation method of micro LED device, micro LED device and display device

Technical Field

The disclosure relates to the technical field of semiconductor LEDs, in particular to a micro LED device manufacturing method, a micro LED device and a display device.

Background

The Micro-LED has the characteristics of self-luminescence, low power consumption, high brightness, high contrast, high resolution and the like, and the Micro-LED display screen has a high-density pixel array, and the size of a single pixel is dozens of micrometers or even several micrometers. With the gradual development of display technology, micro-LED technology has gradually become a trend of new display technology. However, micro-LEDs suffer from optical crosstalk.

Disclosure of Invention

In order to solve the technical problems mentioned in the background art, the present disclosure provides a method for manufacturing a micro LED device, and a display apparatus.

According to one aspect of the disclosed embodiments, a method for manufacturing a micro LED device is provided. The method comprises the following steps: providing a micro LED epitaxial wafer, wherein the micro LED epitaxial wafer sequentially comprises a first semiconductor layer, a multi-layer quantum well structure and a second semiconductor layer from bottom to top; etching from the second semiconductor layer until the first semiconductor layer is exposed to obtain a mesa structure, wherein the mesa structure comprises a plurality of bosses; providing a metal layer on the second semiconductor layer of each mesa and on the exposed first semiconductor layer, resulting in a first intermediate structure; arranging a light extinction layer on the first intermediate structure, and forming a plurality of contact holes on the light extinction layer to expose the metal layer; arranging a metal block on the exposed metal layer to obtain a micro LED chip array; and inversely bonding the micro LED chip array and the driving substrate through the metal block to obtain the micro LED device.

Further, the plurality of bosses form an array of bosses and the array of bosses is located in the center of the mesa structure.

Further, providing a metal layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer includes: providing a current spreading layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer; disposing the metal layer on the current spreading layer.

Further, the current spreading layer includes an indium tin oxide layer.

Further, the matte layer including a first matte portion and an insulating portion, the matte layer being disposed on the first intermediate structure, and the matte layer having a plurality of contact holes opened thereon to expose the metal layer includes: arranging a first extinction part on the exposed first semiconductor layer to obtain a second intermediate structure; an insulating portion is disposed on the second intermediate structure and a plurality of contact holes are opened in the insulating portion to expose the metal layer.

Further, the insulating portion includes an insulating photoresist layer.

Further, the height of the first extinction part is flush with the height of the metal layer on the first semiconductor layer.

Further, the first light extinction portion includes a black photoresist, and disposing the first light extinction portion on the exposed first semiconductor layer includes: arranging the black photoresist on the first intermediate structure to cover the whole first intermediate structure; and carrying out whole-surface etching on the black photoresist by dry etching to expose the metal layer.

Further, opening a plurality of contact holes on the insulating portion to expose the metal layer includes: a plurality of first contact holes and a plurality of second contact holes are opened on the insulating part such that each of the plurality of first contact holes exposes the metal layer on the first semiconductor layer and each of the plurality of second contact holes exposes the metal layer on the second semiconductor layer.

Further, the extinction layer including a second extinction portion, the extinction layer being disposed on the first intermediate structure, and the extinction layer being provided with a plurality of contact holes to expose the metal layer includes: and arranging a second extinction part on the first intermediate structure, and forming a plurality of contact holes on the second extinction part to expose the metal layer.

Further, the material of the metal block includes indium.

Further, the flip-chip bonding of the micro LED chip array and the driving substrate through the metal block to obtain the micro LED device includes: reflowing the metal block to form a metal bump; and flip-chip bonding the micro LED chip array and the driving substrate through the metal bumps.

Further, the substrate is a sapphire substrate, the first semiconductor layer is an N-GaN layer, and the second semiconductor layer is a P-GaN layer.

Further, etching from the second semiconductor layer until the first semiconductor layer is exposed, and obtaining the mesa structure includes: and etching from the second semiconductor layer by adopting an inductively coupled plasma etching method until the first semiconductor layer is exposed to obtain a mesa structure.

Further, providing a current spreading layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer includes: and arranging a current spreading layer on the second semiconductor layer of each boss and on the exposed first semiconductor layer by using an electron beam evaporation method and a lift-off process method.

Further, disposing the metal layer on the current spreading layer comprises: and arranging the metal layer on the current expansion layer by adopting an electron beam evaporation method and a stripping process method.

Further, providing an insulating portion on the second intermediate structure and opening a plurality of contact holes on the insulating portion to expose the metal layer includes: spin coating an insulating layer over the second intermediate structure; and etching a plurality of contact holes on the insulating layer by adopting exposure and development to expose the metal layer.

Further, providing a second extinction portion on the first intermediate structure, and opening a plurality of contact holes on the second extinction portion to expose the metal layer includes: spin coating a second extinction portion on the first intermediate structure; and etching a plurality of contact holes on the second extinction part by adopting exposure and development to expose the metal layer.

Further, disposing a metal block on the exposed metal layer includes: and arranging a metal block on the metal layer by adopting an evaporation method and a wet etching method.

Further, reflowing the slug to form a metalThe bump includes: placing the metal block in a vacuum reflow oven and in N ₂ And refluxing in formic acid environment to form the metal bump.

According to another aspect of the present disclosure, there is also provided a micro LED device. The micro LED device comprises a micro LED chip array and a driving substrate. The micro LED chip array comprises a first intermediate structure, the first intermediate structure comprises a table-board structure and a metal layer, the table-board structure comprises a plurality of bosses, each boss in the plurality of bosses sequentially comprises a first semiconductor layer, a quantum well structure and a second semiconductor layer, and the metal layer is arranged on the second semiconductor layer of each boss and the exposed first semiconductor layer. And the micro LED chip array further comprises: an extinction layer disposed on the first intermediate structure and including a contact hole for exposing the metal layer; and the metal block is arranged on the exposed metal layer, and the micro LED chip array is in flip-chip bonding with the driving substrate through the metal block.

Further, the micro LED chip array further includes a current spreading layer disposed on the second semiconductor layer and the exposed first semiconductor layer of each of the bosses, and the metal layer is disposed on the current spreading layer.

Further, the matte layer includes a first matte portion disposed on the exposed first semiconductor layer, and an insulating portion disposed on the first intermediate structure provided with the first matte portion, and the insulating portion is provided with a plurality of contact holes to expose the metal layer.

Further, the insulating portion includes an insulating photoresist layer.

Further, the extinction layer comprises a second extinction part, the second extinction part is arranged on the first intermediate structure, and a plurality of contact holes are formed in the second extinction part to expose the metal layer.

According to still another aspect of the disclosed embodiments, there is also provided a display device. The display device comprises the micro LED device.

By applying the technical scheme, the table top structure comprising a plurality of bosses can be obtained by etching the epitaxial wafer, the metal layer is arranged on the table top structure to form an intermediate structure, the extinction layer is arranged on the intermediate structure, a plurality of contact holes are formed in the extinction layer to expose the metal layer, and the metal block is arranged on the exposed metal layer to form the micro LED chip array so as to form the micro LED device. Each micro LED chip in the array of micro LED chips in the micro LED device prepared in the way is used as a pixel, and the light which is not normally emitted from the pixel can be absorbed through the extinction layer, namely, the light reflected from the substrate to the inside of the device can be absorbed, so that the phenomenon of optical crosstalk among different pixels can be improved, the phenomenon that the light is continuously reflected in the device and is emitted from the periphery of the device can be improved, in other words, the optical crosstalk phenomenon and the peripheral light leakage problem can be improved while high resolution is realized, and high-efficiency display is realized.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to like or corresponding parts and in which:

fig. 1 is a flow chart illustrating a method of fabricating a micro LED device according to one embodiment of the present disclosure;

fig. 2 a-2 i are schematic diagrams illustrating a fabrication process flow of a method of fabricating a micro LED device according to one embodiment of the present disclosure;

fig. 3 a-3 d are schematic fabrication process flow diagrams illustrating a method of fabricating a micro LED device according to another embodiment of the present disclosure.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

For ease of description, spatially relative terms such as "over 8230," "upper surface," "above," and the like may be used herein to describe the spatial positional relationship of one device or feature to other devices or features as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary terms "at 8230; \8230; 'above" may include both orientations "at 8230; \8230;' above 8230; 'at 8230;' below 8230;" above ". The device may also be oriented 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

Exemplary embodiments according to the present disclosure will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same devices are denoted by the same reference numerals, and thus the description thereof will be omitted.

The disclosure provides a method for manufacturing a micro LED device. Referring to fig. 1, 2 a-2 i, and 3 a-3 d, fig. 1 is a flowchart illustrating a method of fabricating a micro LED device according to one embodiment of the present disclosure. Fig. 2 a-2 i are schematic views illustrating a process flow of a method for fabricating a micro LED device according to an embodiment of the present disclosure. Fig. 3 a-3 d are schematic process flow diagrams illustrating a method for fabricating a micro LED device according to another embodiment of the present disclosure.

According to an embodiment of the present disclosure, a Micro LED device includes an array of Micro LED chips, each of which is as a pixel, typically less than or equal to 200 microns in size, and a driving substrate.

As shown in fig. 1, the method for manufacturing the micro LED device includes the following steps S101 to S107.

Step S101, providing a micro LED epitaxial wafer, wherein the micro LED epitaxial wafer sequentially comprises a first semiconductor layer, a multi-layer quantum well structure and a second semiconductor layer from bottom to top.

And S102, etching is carried out from the second semiconductor layer until the first semiconductor layer is exposed, so as to obtain a mesa structure, wherein the mesa structure comprises a plurality of bosses.

Step S103, a metal layer is arranged on the second semiconductor layer of each boss and on the exposed first semiconductor layer, and a first intermediate structure is obtained.

And step S104, arranging a light extinction layer on the first intermediate structure, and arranging a plurality of contact holes on the light extinction layer to expose the metal layer.

And S105, arranging a metal block on the exposed metal layer to obtain the micro LED chip array.

And S106, inversely bonding the micro LED chip array and the driving substrate through the metal block to obtain the micro LED device.

By applying the technical scheme, the table top structure comprising a plurality of bosses can be obtained by etching the epitaxial wafer, the metal layer is arranged on the table top structure to form an intermediate structure, the extinction layer is arranged on the intermediate structure, a plurality of contact holes are formed in the extinction layer to expose the metal layer, and the metal block is arranged on the exposed metal layer to form the micro LED chip array so as to form the micro LED device. Each micro LED chip in the micro LED chip array in the micro LED device prepared in the way is used as a pixel, and the light which is not normally emitted from the pixel can be absorbed through the extinction layer, namely, the light reflected from the substrate to the inside of the device can be absorbed, so that the light crosstalk phenomenon among different pixels can be improved, the phenomenon that the light is continuously reflected in the device and is emitted from the periphery of the device can be improved, in other words, the optical crosstalk phenomenon and the peripheral light leakage problem can be improved while the high resolution is realized, and the high-efficiency display is realized.

In step S101, a micro LED epitaxial wafer may be provided, which includes, in order from bottom to top, a first semiconductor layer, a multi-layer quantum well structure, and a second semiconductor layer.

According to the embodiment of the disclosure, in order to prepare a micro LED device, a micro LED chip array needs to be prepared first, and then a micro LED epitaxial wafer can be obtained first, where the epitaxial wafer may be prepared in advance, or may be prepared in the preparation process of the micro LED chip array of the disclosure. Referring to fig. 2 a-3 c, wherein fig. 2a shows a micro LED epitaxial wafer 10 according to one embodiment of the present disclosure. As shown in fig. 2a, the micro LED epitaxial wafer 10 may include, in order from bottom to top, a substrate 101, a buffer layer 102, a third semiconductor layer 103, a first semiconductor layer 104, a multi-layer quantum well structure 105, and a second semiconductor layer 106.

According to an embodiment of the present disclosure, the first substrate 101 may be a sapphire substrate, the third semiconductor layer 103 may be a U-GaN layer, the first semiconductor layer 104 may be an N-GaN layer, and the second semiconductor layer 106 may be a P-GaN layer.

In step S102, etching may be performed from the second semiconductor layer until the first semiconductor layer is exposed, resulting in a mesa structure, wherein the mesa structure includes a plurality of mesas.

According to the embodiment of the disclosure, after the micro LED epitaxial wafer is obtained, it may be etched to obtain a mesa structure for disposing an electrode. Wherein the mesa structure includes a plurality of mesas. Further, the plurality of mesas form a mesa array and the mesa array is centered on the mesa structure. The plurality of mesas form an array of mesas such that an array of chips can be formed using the array of mesas, the array of mesas being centrally located in the mesa structure to facilitate subsequent electrode placement.

Specifically, performing etching from the second semiconductor layer until the first semiconductor layer is exposed, and obtaining the mesa structure may include: and etching from the second semiconductor layer by adopting an inductively coupled plasma etching method until the first semiconductor layer is exposed to obtain a mesa structure.

Referring to fig. 2 a-2 i, fig. 2b illustrates a mesa structure 20 formed after etching the epitaxial wafer 10 shown in fig. 2 a. As shown in fig. 2b, the mesa structure 20 comprises a plurality of mesas 21. Specifically, a silicon oxide layer may be deposited on the second semiconductor layer 106 of the epitaxial wafer 10 shown in fig. 2a as a hard mask by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, a photoresist is then spin-coated on the hard mask, a mesa pattern is photo-etched, an inductively coupled Plasma etching (ICP) method is used to etch until the first semiconductor layer 104 is exposed after the photoresist is removed, and finally the silicon oxide layer is removed to form the mesa structure 20 shown in fig. 2 b. Of course, the mesa structure may also be etched using any other suitable process.

In step S103, a metal layer may be provided on the second semiconductor layer of each mesa and on the exposed first semiconductor layer, resulting in a first intermediate structure.

According to an embodiment of the present disclosure, in order to better dispose the electrode, a metal layer may be disposed on the second semiconductor layer of each of the mesas and on at least a portion of the exposed first semiconductor layer.

Further, providing a metal layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer includes: providing a current spreading layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer; disposing the metal layer on the current spreading layer. Wherein the current spreading layer may include an indium tin oxide layer. The light emitting efficiency can be improved by arranging the current spreading layer.

Further, providing a current spreading layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer may include: and arranging a current spreading layer on the second semiconductor layer of each boss and on the exposed first semiconductor layer by using an electron beam evaporation method and a lift-off process method. Disposing the metal layer on the current spreading layer comprises: and arranging the metal layer on the current expansion layer by adopting an electron beam evaporation method and a stripping process method.

Referring to fig. 2 a-2 i, fig. 2c shows a current spreading layer 107 disposed on the second semiconductor layer 106 of each mesa 21 and on a portion of the exposed first semiconductor layer 104. Specifically, an electron beam evaporation method may be used to deposit a current spreading layer 107, such as an indium tin oxide layer, on the structure shown in fig. 2b, and then a lift-off process is used to remove the photoresist and excess metal, resulting in the structure shown in fig. 2 c.

Referring to fig. 2 a-2 i, fig. 2d shows a metal layer 108 disposed on the current spreading layer 107. Specifically, the electron beam evaporation method may be used to deposit a metal layer 108 on the structure shown in FIG. 2c, and then a lift-off process is used to remove the photoresist and excess metal, resulting in a first intermediate structure as shown in FIG. 2 d.

In step S104, an extinction layer may be disposed on the first intermediate structure, and a plurality of contact holes may be opened on the extinction layer to expose the metal layer.

According to an embodiment of the present disclosure, after the metal layer is disposed on the exposed first semiconductor layer in step S103, a first intermediate structure is obtained, whereby the extinction layer may be disposed on the first intermediate structure.

According to a first embodiment of the present disclosure, the matte layer may include a first matte layer and an insulating layer, whereby providing the matte layer on the first intermediate structure, and opening a plurality of contact holes on the matte layer to expose the metal layer may include: arranging a first extinction part on the exposed first semiconductor layer to obtain a second intermediate structure; an insulating portion is disposed on the second intermediate structure and a plurality of contact holes are opened in the insulating portion to expose the metal layer.

In this embodiment, after the metal layer is disposed on the exposed first semiconductor layer in step S103, a part of the first semiconductor layer is still exposed, and a first extinction portion may be disposed on the still exposed first semiconductor layer to obtain a second intermediate structure, and then an insulation layer may be disposed on the second intermediate structure. The first extinction portion may be made of an extinction material such as a dark color resist of a black color resist or a non-metal layer, and the insulating portion may include an insulating photoresist layer, for example, the insulating photoresist layer is made of PFA, so that the surface of the insulating portion disposed on the second intermediate structure is as flat as possible, and the device performance of the micro LED device is improved.

Further, the height of the first extinction part is flush with the height of the metal layer on the first semiconductor layer. In this embodiment, the height of the first extinction portion is flush with the height of the metal layer on the first semiconductor layer, meaning that the absolute value of the height difference between the height of the first extinction portion and the height of the metal layer on the first semiconductor layer is smaller than a preset threshold value, which facilitates the arrangement of the extinction layer and the arrangement of other layers on the extinction layer later.

Further, the first light extinction portion may include a black color resist, and the disposing the first light extinction portion on the exposed first semiconductor layer may include: arranging the black photoresist on the first intermediate structure to cover the whole first intermediate structure; and carrying out whole-surface etching on the black photoresist by dry etching to expose the metal layer. In particular, a black color resist may be spin coated on the first intermediate structure; and etching the black color resistor by adopting an inductively coupled plasma etching method until the metal layer on the first semiconductor layer is exposed. Therefore, the black color resistors with different thicknesses are formed at different positions of the first intermediate structure by utilizing the height difference of different positions on the first intermediate structure, the lower position of the height generally corresponds to the black color resistor with larger thickness, and the black color resistor on the whole surface is etched and etched by a dry method, so that the black color resistor at the position with smaller thickness is etched, and the black color resistor at the position with larger thickness is reserved.

The problem that the pattern position is greatly deviated when a set black light resistance pattern is formed in the related technology is found by the inventor of the application, the extinction performance of the black light resistance, particularly the thick film black light resistance, is excellent, and the positioning mark is difficult to grab during exposure, so that the scheme utilizes the thickness difference of the black color resistance formed by the height difference and then carries out the whole-surface dry etching, the patterning of the black color resistance can be realized without utilizing the positioning mark, the precision of the pattern position can be improved, the improvement effect of the optical crosstalk can be improved, and the aperture ratio of a micro LED device can be improved.

Referring to fig. 2 a-2 i, fig. 2e shows a first matt portion 109, such as a black colour resist, provided on the structure shown in fig. 2 d. As shown in fig. 2e, the first extinction portion 109 may be spin-coated over the entire structure shown in fig. 2d, resulting in the structure shown in fig. 2 e.

Referring to fig. 2a to 2i, fig. 2f illustrates the first extinction portion 109 formed on the structure illustrated in fig. 2 e. After the first extinction portion 109 is spin-coated, the extinction layer is etched by using an Inductively Coupled Plasma (ICP) etching method until the metal layer 108 on the first semiconductor layer 104 is exposed, and at this time, the height of the remaining first extinction portion 109 is flush with the metal layer 108 on the first semiconductor layer 104, thereby obtaining the second intermediate structure 30 as shown in fig. 2 f.

Further, opening a plurality of contact holes on the insulating part to expose the metal layer may include: a plurality of first contact holes and a plurality of second contact holes are opened on the insulating part such that each of the plurality of first contact holes exposes the metal layer on the first semiconductor layer and each of the plurality of second contact holes exposes the metal layer on the second semiconductor layer.

An insulating layer such as a PFA layer may be provided on the second intermediate structure 30 and a contact hole opened to the PFA layer to expose the metal layer. PFA (soluble polytetrafluoroethylene) is an organic photoresist used for preparing the insulating photoresist layer.

Referring to fig. 2 a-2 i, fig. 2g shows the insulating portion 110 with contact holes. As shown in fig. 2g, an insulating part 110 such as a PFA layer may be spin-coated on the second intermediate structure 30 shown in fig. 2f, after the insulating part 110 is spin-coated, a first contact hole 1101 exposing the metal layer 108 on the first semiconductor layer 104 and a second contact hole 1102 exposing the metal layer 108 on the second semiconductor layer 106 are etched on the insulating part using exposure development, and the plurality of second contact holes 1102 form a contact hole array. It is noted that the number of contact holes shown in fig. 2g is merely illustrative, and particularly, the number of second contact holes 1102 may be determined according to the number of chips (pixels) in a desired micro LED chip array.

With the technical solution of the first embodiment, by providing the first extinction portion such as a black color resist on the second semiconductor layer and providing the insulating portion such as PFA on the first extinction portion, it is made possible to make the layers under the insulating portion such as PFA more protected by the insulating portion while the first extinction portion can absorb light reflected from the substrate to the inside of the device.

According to a second embodiment of the present disclosure, the matte layer may include a second matte layer, the matte layer disposed on the first intermediate structure, and the opening of the plurality of contact holes on the matte layer to expose the metal layer includes: and arranging a second extinction part on the first intermediate structure, and forming a plurality of contact holes on the second extinction part to expose the metal layer.

In this second embodiment, a second extinction portion is provided on the first intermediate structure obtained in step S103, and a hole is opened directly on the second extinction portion. Wherein the material of the second extinction part can be dark color resistance such as black or extinction material such as non-metal layer

Further, providing a second extinction portion on the first intermediate structure, and opening a plurality of contact holes on the second extinction portion to expose the metal layer may include: spin coating a second extinction portion on the first intermediate structure; and etching a plurality of contact holes on the second extinction part by adopting exposure and development to expose the metal layer.

Referring to fig. 2 a-2 d and 3 a-3 d, fig. 3a shows a second extinction portion 209 provided on the structure shown in fig. 2 d. As shown in fig. 3a, the second extinction portion 109 may be spin-coated over the entire structure shown in fig. 2d, resulting in the structure shown in fig. 3 a.

Referring to fig. 2a to 2d and fig. 3a to 3d, fig. 3b shows the second extinction part 209 opened with a contact hole. As shown in fig. 3b, a second light-extinction portion 209, such as a black color resist, may be spin-coated on the first intermediate structure shown in fig. 2d, after the second light-extinction portion 209 is spin-coated, a first contact hole 2091 and a second contact hole 2092 are etched on the second light-extinction portion 209 by exposure development, the first contact hole 2091 exposes the metal layer 108 on the first semiconductor layer 104, the second contact hole 2092 exposes the metal layer 108 on the second semiconductor layer 106, and the plurality of second contact holes 2092 form a contact hole array. It is noted that the number of contact holes shown in fig. 3b is merely illustrative, and particularly, the number of second contact holes 2092 may be determined according to the number of chips (pixels) in the desired micro LED chip array.

With the technical solution of the second embodiment, by disposing the second extinction portion such as black color resistance on the second semiconductor layer for extinction and insulation protection, the disposition of the insulation portion such as PFA on the first extinction portion is reduced, so that while the second extinction portion can absorb light reflected from the substrate to the inside of the device, the preparation of the insulation portion can be reduced, thereby reducing the process progress and the process difficulty and reducing the cost.

In step S105, a metal block may be disposed on the exposed metal layer, resulting in a micro LED chip array.

According to an embodiment of the present disclosure, in order to complete the preparation of the micro LED chip array, a metal block may be disposed on the exposed metal layer so as to be bonded with other components to achieve corresponding functions. The metal block may be made of indium, which has a low melting point and is particularly suitable for flip chip bonding at relatively low temperatures, but may also be made of any suitable metal.

Referring to fig. 2 a-2 i, fig. 2h shows a metal block 111 disposed on the metal layer 108. Specifically, a metal, such as indium, may be deposited on the structure shown in fig. 2g by vacuum thermal evaporation, and wet etching may be performed by using a photoresist as a mask, so as to obtain the structure shown in fig. 2 h.

Thus, the micro LED chip array is completed, and fig. 2h shows the completed micro LED chip array 40.

Referring to fig. 2 a-2 d and 3 a-3 d, fig. 3c shows metal block 211 disposed on metal layer 108. Specifically, a metal, such as indium, may be deposited on the structure shown in fig. 3b by vacuum thermal evaporation, and wet etching may be performed by using a photoresist as a mask, so as to obtain the structure shown in fig. 3 c.

Thus, the micro LED chip array is completed, and fig. 3c shows the completed micro LED chip array 60.

In step S106, the micro LED chip array and the driving substrate may be flip-chip bonded through the metal block, so as to obtain a micro LED device.

According to the embodiment of the present disclosure, in order to realize a micro LED device, the prepared micro LED chip array needs to be bonded with a driving substrate.

Further, the flip-chip bonding of the micro LED chip array and the driving substrate through the metal block to obtain the micro LED device includes: reflowing the metal block to form a metal bump; and the miniature LED chip array is in flip-chip bonding with the driving substrate through the metal bumps.

Specifically, reflowing the metal block to form the metal bump may include: placing the metal block in a vacuum reflow furnace and in N ₂ And refluxing in formic acid environment to form the metal bump.

Referring to fig. 2 a-2 i, fig. 2i shows the micro LED chip array 40 and the driving substrate 50 bonded together. Specifically, the structure shown in fig. 2h is placed in a vacuum reflow furnace for reflow of the metal block 111, the vacuum reflow furnace is first vacuumized to ensure a vacuum state,then introducing N into the vacuum reflux furnace ₂ And formic acid and heated to reflow, resulting in the metal bump 112 shown in fig. 2 i. Wherein the initial vacuum environment can avoid metal oxidation during the reflux process to generate metal oxide with high melting point, formic acid can reduce the metal oxide, and N ₂ Metal oxidation can be reduced. Then, the micro LED chip array 40 may be flipped using a flip-chip bonding machine and the micro LED chip array 40 may be bonded to the driving substrate 50 using the metal bumps 112.

Thereby, the micro LED device is completed, and fig. 2i shows the completed micro LED device 1.

Referring to fig. 2 a-2 d and 3 a-3 d, fig. 3d shows the array of micro LED chips 60 and the driving substrate 50 bonded together. Specifically, the structure shown in fig. 3c is placed in a vacuum reflow furnace for reflow of the metal block 211, the vacuum reflow furnace is first vacuumized to ensure a vacuum state, and then N is introduced into the vacuum reflow furnace ₂ And formic acid and heated to reflow, resulting in the metal bump 212 shown in fig. 3 d. Wherein the initial vacuum environment can avoid metal oxidation during the reflux process to generate metal oxide with high melting point, formic acid can reduce the metal oxide, and N ₂ Metal oxidation can be reduced. Then, the micro LED chip array 60 may be flipped using a flip-chip bonding machine and the micro LED chip array 60 may be bonded to the driving substrate 50 using the metal bumps 212.

Thereby, the micro LED device is completed, and fig. 3d shows the completed micro LED device 2.

It should be noted that, the inventor of the present disclosure finds that, there is reflection at the interface between the U-GaN layer of the light emitting chip (lit pixel) of the single-color Micro-LED device with a sapphire substrate and the sapphire substrate, and the reflected light enters the unlit pixel or exits from the side of the device, thereby causing a crosstalk phenomenon or a light leakage phenomenon. Meanwhile, when a high-resolution display screen is prepared, due to the fact that the size of pixels is reduced, the yield rate problem occurs in part of processes, and the optical crosstalk phenomenon and the light leakage phenomenon are prone to occurring. According to the technical scheme, the mesa structure comprising the bosses can be obtained by etching the epitaxial wafer, the metal layer is arranged on the mesa structure to form the intermediate structure, the extinction layer is arranged on the intermediate structure, the extinction layer is provided with the contact holes to expose the metal layer, the metal block is arranged on the exposed metal layer to form the micro LED chip array, and then the micro LED device is formed. Each micro LED chip in the array of micro LED chips in the micro LED device prepared in the way is used as a pixel, and the light which is not normally emitted from the pixel can be absorbed through the extinction layer, namely, the light reflected from the substrate to the inside of the device can be absorbed, so that the phenomenon of optical crosstalk among different pixels can be improved, the phenomenon that the light is continuously reflected in the device and is emitted from the periphery of the device can be improved, in other words, the optical crosstalk phenomenon and the peripheral light leakage problem can be improved while high resolution is realized, and high-efficiency display is realized.

The present disclosure also provides a micro LED device. The micro LED device can be manufactured by the preparation method of the micro LED device.

As shown in fig. 2a to 2i, the micro LED device 1 includes a micro LED chip array 40 and a driving substrate 50. The micro LED chip array 40 includes a first intermediate structure including a mesa structure 20 and a metal layer 108, the mesa structure 20 including a plurality of mesas 21, each of the plurality of mesas including, in order, a first semiconductor layer 104, a quantum well structure 105, and a second semiconductor layer 106, the metal layer 108 disposed on the second semiconductor layer 106 and on the exposed first semiconductor layer 104 of each mesa, and the micro LED chip array 40 further includes: an extinction layer disposed on the first intermediate structure and including a contact hole for exposing the metal layer; a metal block 111 disposed on the exposed metal layer, wherein the micro LED chip array 40 is flip-chip bonded to the driving substrate 50 through the metal block 111.

According to an embodiment of the present disclosure, the micro LED chip array 40 further includes a current spreading layer 107, the current spreading layer 107 is disposed on the second semiconductor layer 106 and the exposed first semiconductor layer 104 of each of the bosses, and the metal layer 108 is disposed on the current spreading layer 107.

According to an embodiment of the present disclosure, the extinction layer includes a first extinction portion 109 and an insulation portion 110, the first extinction portion 109 is disposed on the exposed first semiconductor layer, the insulation portion 110 is disposed on the first intermediate structure provided with the first extinction portion 109, and the insulation portion 110 is opened with a plurality of contact holes to expose the metal layer. Specifically, the insulating portion 110 is opened with a plurality of first contact holes 1101 and a plurality of second contact holes 1102, each of the plurality of first contact holes 1101 exposing the metal layer 108 on the first semiconductor layer 104 and each of the plurality of second contact holes exposing the metal layer 108 on the second semiconductor layer 106.

According to an embodiment of the present disclosure, a height of the first extinction portion is flush with a height of the metal layer on the first semiconductor layer.

According to an embodiment of the present disclosure, the insulating part includes an insulating photoresist layer.

As shown in fig. 2a to 2d and fig. 3a to 3d, the micro LED device 2 includes a micro LED chip array 60 and a driving substrate 50. The micro LED chip array 60 includes a first intermediate structure including a mesa structure 20 and a metal layer 108, the mesa structure 20 includes a plurality of mesas 21, each of the plurality of mesas includes a first semiconductor layer 104, a quantum well structure 105 and a second semiconductor layer 106 in this order, the metal layer 108 is disposed on the second semiconductor layer 106 and the exposed first semiconductor layer 104 of each mesa, and the micro LED chip array 60 further includes: an extinction layer disposed on the first intermediate structure and including a contact hole for exposing the metal layer; a metal block 211 disposed on the exposed metal layer, wherein the micro LED chip array 60 is flip-chip bonded to the driving substrate 50 through the metal block 211.

According to an embodiment of the present disclosure, the micro LED chip array 60 further includes a current spreading layer 107, the current spreading layer 107 is disposed on the second semiconductor layer 106 and the exposed first semiconductor layer 104 of each of the bosses, and the metal layer 108 is disposed on the current spreading layer 107.

According to the embodiment of the present disclosure, the extinction layer includes a second extinction portion 209, the second extinction portion 209 is disposed on the first intermediate structure, and a plurality of first contact holes 2091 and a plurality of second contact holes 2092 are opened on the second extinction portion 209 to expose the metal layer.

It is noted that any relevant description (including but not limited to technical features and their roles, explanations, etc.) regarding the structure of the micro LED device in the above-described method for manufacturing the micro LED device can be applied to the micro LED device of the present disclosure.

The present disclosure also provides a display device. The display device comprises the micro LED device. The display device can be applied to electronic equipment to realize technologies such as Augmented Reality (AR), virtual Reality (VR), extended Reality (XR), mixed Reality (MR), and the like. For example, the Display device may be a projection portion of an electronic apparatus, such as a projector, a Head Up Display (HUD), or the like; for another example, the display device may be a display portion of an electronic apparatus, and the electronic apparatus may include: any equipment with a display screen, such as a smart phone, a smart watch, a notebook computer, a tablet computer, a vehicle data recorder, a navigator, a head-mounted device and the like.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A micro LED device preparation method, wherein the method comprises the following steps:

providing a micro LED epitaxial wafer, wherein the micro LED epitaxial wafer sequentially comprises a first semiconductor layer, a multi-layer quantum well structure and a second semiconductor layer from bottom to top;

etching from the second semiconductor layer until the first semiconductor layer is exposed to obtain a mesa structure, wherein the mesa structure comprises a plurality of bosses;

providing a metal layer on the second semiconductor layer of each mesa and on the exposed first semiconductor layer, resulting in a first intermediate structure;

arranging a light extinction layer on the first intermediate structure, and forming a plurality of contact holes on the light extinction layer to expose the metal layer;

arranging a metal block on the exposed metal layer to obtain a micro LED chip array;

and inversely bonding the micro LED chip array and the driving substrate through the metal block to obtain the micro LED device.

2. The method of manufacturing a micro LED device according to claim 1, wherein the matte layer includes a first matte layer and an insulating layer, the matte layer is disposed on the first intermediate structure, and the opening of the plurality of contact holes on the matte layer to expose the metal layer includes:

arranging a first extinction part on the exposed first semiconductor layer to obtain a second intermediate structure;

an insulating portion is disposed on the second intermediate structure and a plurality of contact holes are opened in the insulating portion to expose the metal layer.

3. The method of manufacturing a micro LED device according to claim 2, wherein the first extinction portion includes a black color resist, and the disposing the first extinction portion on the exposed first semiconductor layer includes:

arranging the black photoresist on the first intermediate structure to cover the whole first intermediate structure;

and carrying out whole-surface etching on the black photoresist by dry etching to expose the metal layer.

4. The method for manufacturing a micro LED device according to claim 2, wherein the first extinction portion has a height that is flush with a height of the metal layer on the first semiconductor layer.

5. The method of fabricating a micro LED device according to claim 2, wherein the insulating portion comprises an insulating photoresist layer.

6. The method of manufacturing a micro LED device according to claim 1, wherein the matte layer includes a second matte portion, the matte layer is disposed on the first intermediate structure, and the opening of the plurality of contact holes on the matte layer to expose the metal layer includes:

and arranging a second extinction part on the first intermediate structure, and forming a plurality of contact holes on the second extinction part to expose the metal layer.

7. The method for manufacturing a micro LED device according to claim 1, wherein flip-chip bonding the array of micro LED chips and the driving substrate through the metal block to obtain the micro LED device comprises:

reflowing the metal block to form a metal bump;

and the miniature LED chip array is in flip-chip bonding with the driving substrate through the metal bumps.

8. The micro LED device manufacturing method according to any one of claims 1 to 7, wherein providing a metal layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer comprises:

providing a current spreading layer on the second semiconductor layer of each of the mesas and on the exposed first semiconductor layer;

disposing the metal layer on the current spreading layer.

9. A micro LED device, wherein the micro LED device comprises a micro LED chip array and a driving substrate,

wherein the micro LED chip array comprises a first intermediate structure, the first intermediate structure comprises a mesa structure and a metal layer, the mesa structure comprises a plurality of bosses, each boss of the plurality of bosses sequentially comprises a first semiconductor layer, a quantum well structure and a second semiconductor layer, the metal layer is arranged on the second semiconductor layer of each boss and the exposed first semiconductor layer,

and the micro LED chip array further comprises:

an extinction layer disposed on the first intermediate structure and including a contact hole for exposing the metal layer;

a metal block disposed on the exposed metal layer,

and the micro LED chip array is in flip bonding with the driving substrate through the metal block.

10. The micro LED device according to claim 7, wherein the extinction layer includes a first extinction part disposed on the exposed first semiconductor layer, and an insulation part disposed on the first intermediate structure provided with the first extinction part, and the insulation part has a plurality of contact holes opened thereon to expose the metal layer.

11. The micro LED device according to claim 7, wherein a height of the first extinction portion is flush with a height of the metal layer on the first semiconductor layer.

12. The micro LED device of claim 7, wherein the insulating portion comprises an insulating photoresist layer.

13. The micro LED device according to claim 7, wherein the extinction layer includes a second extinction portion disposed on the first intermediate structure, and a plurality of contact holes are opened on the second extinction portion to expose the metal layer.

14. The micro LED device of any one of claims 9 to 13, wherein the array of micro LED chips further comprises a current spreading layer disposed on the second semiconductor layer and on the exposed first semiconductor layer of each mesa, and the metal layer is disposed on the current spreading layer.

15. A display apparatus, wherein the display apparatus comprises the micro LED device of any one of claims 9 to 14.