WO2021017497A1

WO2021017497A1 - Display panel, display device and manufacturing method for display panel

Info

Publication number: WO2021017497A1
Application number: PCT/CN2020/080935
Authority: WO
Inventors: 杨婷慧; 王雪丹
Original assignee: 成都辰显光电有限公司
Priority date: 2019-07-31
Filing date: 2020-03-24
Publication date: 2021-02-04
Also published as: CN110416245A; CN110416245B; KR20220025850A

Abstract

A display panel, a display device and a manufacturing method for the display panel. The display panel comprises: at least one light-emitting diode chip (20), wherein the light-emitting diode chip (20) comprises a first electrode (21) and an LED epitaxial structure that are arranged in a stacked manner, and the LED epitaxial structure comprises a first semiconductor layer (22); and a conductive layer (30) is located on one side, away from the first electrode (21), of the light-emitting diode chip (20); the conductive layer (30) is in contact with the first semiconductor layer (22), and the conductive layer (30) comprises a hollow portion (31) and in the thickness direction of the first semiconductor layer (22), the projection of the hollow portion (31) on the conductive layer (30) is overlapped with the projection of the first electrode (21) on the conductive layer (30).

Description

Display panel, display device and manufacturing method of display panel

This application claims the priority of the Chinese patent application filed with the Chinese Patent Office with application number 201910702461.6 on July 31, 2019. The entire content of this application is incorporated into this application by reference.

Technical field

This application relates to the field of display technology, for example, to a display panel, a display device, and a manufacturing method of the display panel.

Background technique

The Micro Light Emitting Diode (micro-LED/μLED) display panel integrates Light Emitting Diode (LED) chips with a size of less than 100 microns on a substrate as display pixels to realize image display. Each display pixel can be addressed and individually driven to light up, so the Micro-LED display panel is a self-luminous display panel.

In the related art, the LED chip adopts a current conduction layer scheme to achieve common cathode connection, and the current conduction layer distributes current conduction to each LED chip (pixel) in the display area. However, this common cathode connection scheme has the problem of uneven current distribution and poor brightness uniformity of the display panel.

Summary of the invention

The present application provides a display panel, a display device and a manufacturing method of the display panel, so as to reduce the resistance of the current conducting layer and improve the brightness uniformity of the display panel.

A display panel including:

At least one light-emitting diode chip, the light-emitting diode chip comprising a first electrode and a first semiconductor layer arranged in a stack;

The conductive layer is located on the side of the light emitting diode chip away from the first electrode;

Wherein, the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow portion, and along the thickness direction of the first semiconductor layer, the projection of the hollow portion on the conductive layer overlaps with the projection of the first electrode on the conductive layer.

Correspondingly, the present application also provides a display device, including a display panel as provided in any embodiment of the present application.

The application also provides a manufacturing method of the display panel, including:

Provide a light emitting diode chip array, the light emitting diode chip array includes a plurality of light emitting diode chips, the light emitting diode chip includes a first electrode and a first semiconductor layer;

A conductive layer is fabricated on the side of the light-emitting diode chip away from the first electrode; the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow portion along the thickness direction of the first semiconductor layer, and the projection of the hollow portion on the conductive layer is the same as the first The projections of the electrodes on the conductive layer overlap.

In the display panel provided by the present application, a conductive layer is made on the side of the light-emitting diode chip away from the first electrode; the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow part along the thickness direction of the first semiconductor layer. The electrodes overlap. In the first aspect, the conductive layer of the display panel made by this application is in contact with the first semiconductor layer, so that both the conductive layer and the first semiconductor layer serve as the current conducting layer of the LED chip, reducing the resistance of the current conducting layer and improving The brightness uniformity of the display panel is improved. In the second aspect, the surface of the first semiconductor layer is flat, which facilitates the contact conduction between the entire surface of the conductive layer and the entire surface of the first semiconductor layer, thereby helping to avoid poor contact between the conductive layer and the first semiconductor layer, as well as avoiding due to alignment The inaccuracy leads to the problem of contact between the conductive layer and other film layers of the LED chip. Therefore, the present application improves the yield of the display panel, and the production of the conductive layer can be implemented based on the existing process, which has low process difficulty and is easy to implement. In the third aspect, the hollow part of the conductive layer overlaps the first electrode, that is, the hollow part of the conductive layer overlaps the LED chip, so that the light emitted by the LED chip can be emitted through the hollow part. Therefore, the present application is beneficial to reduce current conduction. The resistance of the pass layer does not affect the light extraction rate of the display panel. In summary, the present application achieves the effect of reducing the resistance of the current conducting layer with lower process difficulty on the basis of ensuring the light output rate of the display panel.

Description of the drawings

FIG. 1 is a schematic diagram of a top view structure of a first display panel provided by an embodiment of the application;

Fig. 2 is a schematic cross-sectional structure view along the A-A direction in Fig. 1;

3 is a schematic structural diagram of a display panel formed in each step of a method for manufacturing a display panel according to an embodiment of the application;

4 is a schematic diagram of a top view structure of a second display panel provided by an embodiment of the application;

FIG. 5 is a schematic diagram of a top view structure of a third display panel provided by an embodiment of the application;

6 is a schematic structural diagram of an LED chip array formed in each step of a method for manufacturing an LED chip array according to an embodiment of the application;

FIG. 7 is a schematic structural diagram of an LED chip array formed in each step of another method for manufacturing an LED chip array according to an embodiment of the application;

FIG. 8 is a schematic structural diagram of a second display panel provided by an embodiment of the application;

FIG. 9 is a schematic structural diagram of a third display panel provided by an embodiment of the application;

10 is a schematic structural diagram of a fourth display panel provided by an embodiment of the application;

FIG. 11 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the application.

Detailed ways

The application will be further described in detail below with reference to the drawings and embodiments. It is understandable that the specific embodiments described here are only used to explain the application, but not to limit the application. In addition, it should be noted that, for ease of description, the drawings only show a part of the structure related to the present application instead of all of the structure.

FIG. 1 is a schematic top view of the structure of a first display panel provided by an embodiment of the application, and FIG. 2 is a schematic view of the cross-sectional structure along the A-A direction in FIG. 1.

1 and 2, the display panel includes: at least one light emitting diode chip 20 and a conductive layer 30. The light emitting diode chip 20 includes a first electrode 21 and a first semiconductor layer 22 that are stacked. The conductive layer 30 is located on the side of the light emitting diode chip 20 away from the first electrode 21, and the conductive layer 30 is in contact with the first semiconductor layer 22. The conductive layer 30 includes a hollow portion 31, and along the thickness direction B of the first semiconductor layer 22, the hollow portion 31 and the projection of the first electrode 21 on the same plane overlap. That is, along the thickness direction B of the first semiconductor layer 22, the projection of the hollow portion 31 on the first semiconductor layer 22 overlaps with the projection of the first electrode 21 on the first semiconductor layer 22 or the hollow portion 31 is on the conductive layer 30 The projection of is overlapped with the projection of the first electrode 21 on the conductive layer 30.

Wherein, the light emitting diode chip 20 may be a pixel of a display panel. The structure of the light emitting diode chip 20, hereinafter referred to as the LED chip 20, for example, may include a first electrode 21 and an LED epitaxial structure. The first semiconductor layer 22 is a part of the LED epitaxial structure. The first semiconductor layer 22 may be, for example, N-type gallium nitride ( N-GaN); the LED epitaxial structure may also include a multiple quantum well layer 24 (MQW) and a second semiconductor layer 23, the second semiconductor layer 23 may be, for example, P-type gallium nitride (P-GaN). The first semiconductor layer 22 is a common layer of a plurality of LED chips 20, so as to facilitate the contact between the conductive layer 30 and the first semiconductor layer 22. The first semiconductor layer 22 and the conductive layer 30 constitute a current conducting layer of the LED chip 20, and the current conducting layer is the second electrode of the LED chip 20. In this application, the conductive layer 30 is arranged in contact with the first semiconductor layer 22, which is equivalent to increasing the thickness of the first semiconductor layer 22, thereby reducing the resistance of the first semiconductor layer 22; from another perspective, the conductive layer 30 is arranged in contact with the first semiconductor layer 22. The contact of the first semiconductor layer 22 is equivalent to an increase in the current flow path in terms of only providing the first semiconductor layer 22 as a current flow path, which is beneficial to more uniform currents at different positions on the first semiconductor layer 22. Therefore, providing the conductive layer 30 in contact with the first semiconductor layer 22 in the present application is beneficial to reduce the resistance of the current conducting layer.

Along the thickness direction B of the first semiconductor layer 22, the hollow portion 31 of the conductive layer 30 overlaps with the projection of the first electrode 21 on the same plane. Specifically, the hollow portion 31 of the conductive layer 30 is on the first semiconductor layer 22. The projection of the first electrode 21 overlaps the projection of the first electrode 21 on the first semiconductor layer 22, so the light emitted by the LED chip 20 can be emitted through the hollow portion 31. This arrangement in this application not only helps to reduce the resistance of the current conducting layer, but also does not affect the light output rate of the display panel.

The display panel includes at least one LED chip 20, and the at least one LED chip 20 can be one, two or more. Further, a plurality of LED chips 20 are arranged in an array. Optionally, a plurality of LED chips 20 are arranged in an array as an example.

3 is a schematic structural diagram of a display panel formed in each step of a method for manufacturing a display panel according to an embodiment of the application. Referring to FIG. 3, for example, a plurality of LED chips 20 are arranged on a substrate 10. The substrate 10 may be, for example, a driving backplane. The driving backplane includes a driving circuit for driving the LED chip 20 to emit light. The driving circuit may be, for example, CMOS drive circuit. Optionally, at least one of the substrate 10 and the LED chip 20 is provided with a pad 11 through which the substrate 10 and the first electrode 21 of the LED chip 20 are welded to achieve electrical connection between the substrate 10 and the LED chip 20.

The manufacturing method of the display panel includes the following steps.

S110. Provide a substrate 10 and an LED chip array.

The LED chip array includes a second substrate 40 and a plurality of LED chips 20 on the second substrate 40, and the LED chip 20 includes a first electrode 21 and a first semiconductor layer 22.

S120. Binding the substrate 10 and the LED chip array.

Wherein, for example, the method of binding the substrate 10 and the LED chip array is flip-chip bonding, so that the first electrode 21 and the substrate 10 are electrically connected.

S130. Remove the second substrate 40 of the LED chip array.

Among them, after the second substrate 40 is removed, the first semiconductor layer 22 is the farthest away from the base 10. There are many processes for removing the second substrate 40. For example, if the substrate is a sapphire substrate, the sapphire substrate can be removed by laser lift-off; if the substrate is a silicon substrate, the sapphire substrate can be removed by wet etching. The silicon substrate is removed.

S140, forming a conductive layer 30 on the side of the LED chip array away from the substrate 10.

The conductive layer 30 is in contact with the first semiconductor layer 22, and the conductive layer 30 includes a hollow portion 31. Along the thickness direction of the first semiconductor layer 22, the hollow portion 31 overlaps with the projection of the first electrode 21 on the first semiconductor layer 22. There are many methods for making the conductive layer 30. For example, the making of the conductive layer 30 includes: using an evaporation process or a sputtering process to make a conductive layer material on the side of the LED chip array away from the substrate 10; Coated with photoresist on one side; patterning the photoresist by using a photolithography process; using a dry etching process or a wet etching process to pattern the conductive layer material to form the conductive layer 30. For another example, the production of the conductive layer 30 includes: placing a fine metal mask between the evaporation source and the first semiconductor layer 22, and evaporating the conductive layer material onto the surface of the first semiconductor layer 22 to form a hollow portion 31 The conductive layer 30.

The conductive layer 30 of the present application is arranged on the side of the LED chip 20 away from the first electrode 21 and is in contact with the first semiconductor layer 22. The conductive layer 30 includes a hollow portion 31, and along the thickness direction of the first semiconductor layer 22, the hollow portion 31 overlaps with the projection of the first electrode 21 on the first semiconductor layer 22. In the first aspect, the conductive layer 30 is in contact with the first semiconductor layer 22, so that both the conductive layer 30 and the first semiconductor layer 22 serve as the current conducting layer of the LED chip 20, reducing the resistance of the current conducting layer and improving the display panel The brightness uniformity. In the second aspect, the surface of the first semiconductor layer 22 is flat, which facilitates the contact conduction between the entire surface of the conductive layer 30 and the entire surface of the first semiconductor layer 22, thereby avoiding poor contact between the conductive layer 30 and the first semiconductor layer 22, and avoiding The misalignment causes the conductive layer 30 to contact the other film layers of the LED chip 20. Therefore, the present application improves the yield of the display panel, and the fabrication of the conductive layer 30 can be realized based on related processes, which has low process difficulty and is easy to realize. In the third aspect, the hollow portion 31 of the conductive layer 30 overlaps with the projection of the first electrode 21 on the first semiconductor layer 22, that is, the hollow portion 31 of the conductive layer 30 overlaps the LED chip 20, so that the light emitted by the LED chip 20 It can be emitted through the hollow portion 31. Therefore, the present application is beneficial to reduce the resistance of the current conducting layer without affecting the light output rate of the display panel. In summary, on the basis of ensuring the light output rate of the display panel, the present application achieves the effect of reducing the resistance of the current conducting layer with a lower process difficulty.

It should be noted that the material of the conductive layer 30 provided in the present application can have a variety of choices, and can be set as required in practical applications. For example, the material of the conductive layer 30 can be selected from one or more of light transmissive materials such as indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and zinc aluminum oxide, and semi-transparent materials such as silver and silver alloys. One or more of light materials, or one or more of opaque materials such as aluminum, molybdenum, titanium, copper or alloys thereof.

Continuing to refer to FIGS. 1 and 2, optionally, the conductive layer 30 further includes a non-hollowed portion 32, and the non-hollowed portion 32 is opaque. In the present application, the hollow portion 31 and the projection of the first electrode 21 on the first semiconductor layer 22 are overlapped, and the non-hollow portion 32 is opaque, so that the conductive layer 30 can act as a black matrix. On the one hand, along the direction of the thickness of the first semiconductor layer 22, the light with a smaller angle emitted by the LED chip 20 can be emitted through the hollow portion 31, while the light with a larger angle emitted by the LED chip 20 cannot be emitted to the surface of the non-hollowed portion 32. It emits through the non-hollowed part 32, therefore, providing the non-hollowed part 32 to be opaque is beneficial to prevent the light crosstalk between the pixels. On the other hand, compared to transparent materials and semi-transparent materials, it is easier to select materials with better conductivity and lower resistance when the non-hollowed part 32 is opaque. Therefore, the non-hollowed part 32 is not transparent. It also helps to reduce the resistance of the current conducting layer.

Optionally, the conductive layer 30 is a metal conductive layer. Compared with non-metallic materials, metal materials have stronger conductivity. Therefore, providing the conductive layer 30 as a metal conductive layer is beneficial to further improve the conductivity of the current conducting layer. Optionally, the metal material may include at least one of aluminum, copper, titanium, or silver, for example. Compared with other metal materials, the metal materials provided in the embodiments of the present application are easy to process, which is beneficial to the contact between the metal materials and the first semiconductor layer 22 and reduces the process cost.

It should be noted that FIG. 1 exemplarily shows that along the thickness direction of the first semiconductor layer 22, the shape of the projection of the conductive layer 30 is a grid shape, which is not a limitation of the present application. Optionally, the shape of the conductive layer 30 It can also be set as a strip, ring or concentric ring, etc., which can be set as required in practical applications. Illustratively, referring to FIG. 4, the shape of the conductive layer 30 is a strip; referring to FIG. 5, the shape of the conductive layer 30 is a concentric ring. In this embodiment, the shape of the projection of the conductive layer 30 is grid-like. This is because the LED chips 20 on the display panel are generally arranged in an array, that is, the area where the LED chips 20 are arranged is the light-emitting area, and no LEDs are arranged on the same plane. The area of the chip 20 is a non-light-emitting area, and the shape formed by staggering the light-emitting area and the non-light-emitting area is a grid shape. Therefore, the shape of the projection of the conductive layer 30 is a grid shape to meet the requirements for setting around each LED chip 20 The non-hollowed portion 32 is beneficial to increase the area of the conductive layer 30 and further improve the conductivity of the current conducting layer.

FIG. 6 is a schematic structural diagram of an LED chip array formed in each step of a method for manufacturing an LED chip array provided by an embodiment of the application. Referring to FIG. 6, illustratively, the manufacturing method of the LED chip array includes the following steps.

S210, preparing an LED epitaxial wafer.

Wherein, the first semiconductor layer 22, the multiple quantum well material layer 44 and the second semiconductor material layer 43 are sequentially fabricated on the second substrate 40. The second substrate 40 may be, for example, a silicon substrate or a sapphire substrate. Optionally, before fabricating the first semiconductor layer 22, a buffer layer is fabricated on the second substrate 40, and the material of the buffer layer may be, for example, aluminum nitride (AlN) or gallium nitride (GaN). Providing a buffer layer between the first semiconductor layer 22 and the second substrate 40 is beneficial to improve the lattice matching between the first semiconductor layer 22 and the second substrate 40.

S220, etching the LED epitaxial wafer to form the LED epitaxial structure and the isolation groove 45. Among them, the process of etching the LED epitaxial wafer can be, for example, a photolithography and etching process, that is, first coat photoresist on the second semiconductor material layer 43, use a photolithography process to pattern the photoresist, and then use an etching process The semiconductor film layer between the LED epitaxial structures is removed, the etching isolation groove 45 stops at the first semiconductor layer 22, the etched part forms an isolation groove 45, and the isolation groove 45 is located between two adjacent LED chips 20.

The LED epitaxial structure includes: a first semiconductor layer 22, a multiple quantum well layer 24 formed after etching the multiple quantum well material layer 44, and a second semiconductor layer 23 formed after etching the second semiconductor material layer 43.

S230, filling the isolation trench 45 to form a second insulating layer 46.

Wherein, the process of filling the isolation trench 45 may use a physical or chemical vapor deposition process to fill an inorganic insulating material such as silicon dioxide, silicon nitride, or Bragg reflector (DBR).

Then use a chemical mechanical polishing (CMP) process to grind the second insulating layer 46 flat so that the height of the second insulating layer 46 is the same as the mesa of the LED epitaxial structure (that is, the upper surface of the second semiconductor layer 23 away from the second substrate 40). ) Maintain the same height. Optionally, the second insulating layer 46 is a Bragg reflective layer, and the Rager reflective layer has periodic reflection points. When the light of the LED chip 20 enters the Bragg reflective layer, the Bragg reflective layer will produce periodic reflections and block the LED. The light emitted by the chip 20 is emitted to the adjacent LED chip 20, thereby improving the light extraction efficiency of the LED chip 20 and reducing the light crosstalk between the LED chips 20, that is, reducing the light crosstalk between pixels.

S240, forming a first electrode 21 on the surface of the LED epitaxial structure on the side away from the second substrate 40 to form an LED chip array.

The manufacturing method of the LED chip array provided by this application has a feasible process and a high yield. Among them, S210, the step of preparing the LED epitaxial wafer can also be omitted, and the prepared epitaxial wafer can be directly purchased for the LED epitaxial wafer.

FIG. 7 is a schematic structural diagram of an LED chip array formed in each step of another method for manufacturing an LED chip array according to an embodiment of the application. Referring to FIG. 7, illustratively, the manufacturing method of the LED chip array includes the following steps.

S310, preparing an LED epitaxial wafer.

S320, etching the LED epitaxial wafer to form the LED epitaxial structure and the isolation groove 45.

S330, forming a first insulating layer 47 on the bottom surface and sidewall surface of the isolation trench 45 to form a second trench 48.

The manufacturing process of the first insulating layer 47 may be a chemical vapor deposition process to form a layer of inorganic insulating material such as silicon dioxide, silicon nitride, or Bragg reflector (DBR) on the bottom surface and sidewall surface of the isolation trench 45. The thickness of the first insulating layer 47 is smaller than the depth of the isolation trench 45 so that the first insulating layer 47 can form the second trench 48. The sidewall of the isolation groove 45 is the sidewall of the LED chip 20. Optionally, the first insulating layer 47 is a Bragg reflective layer. The Rager reflective layer has periodic reflection points. When the light from the LED chip 20 enters the Bragg reflection When layering, the Bragg reflective layer will produce periodic reflections, blocking the light emitted by the LED chip 20 from emitting to the adjacent LED chips 20, thereby improving the light extraction efficiency of the LED chips 20 and reducing the light crosstalk between the LED chips 20. That is to reduce the light crosstalk between pixels.

S340, forming a first electrode 21 on the surface of the LED epitaxial structure on the side away from the second substrate 40 to form an LED chip array.

Optionally, the isolation trench 45 is not filled in the present application, but an insulating layer is formed on the sidewall surface of the LED epitaxial structure, so that the structure of the isolation trench is retained. According to the present application, in the subsequent bonding process of the substrate 10 and the LED chip 20, the second groove 48 can contain the solder to be soldered, to prevent the short connection of the solder between adjacent solder joints, and to avoid the gap between the adjacent LED chips 20. The electrodes are shorted.

FIG. 8 is a schematic structural diagram of a second display panel provided by an embodiment of the application. Referring to FIG. 8, optionally, the display panel further includes a reflective layer 52, the light emitting diode chip 20 includes sidewalls, and the sidewalls of the light emitting diode chip 20 are the sidewalls of the LED epitaxial structure. The reflective layer 52 is located on the sidewall of the LED epitaxial structure. The sidewall surface of the LED epitaxial structure and the bottom surface of the isolation groove 45 form a first insulating layer 47. Wherein, the sidewall of the LED chip 20 is also the sidewall of the first trench 51. The reflective layer 52 is located on the side wall of the LED epitaxial structure. On the one hand, it can block the light emitted by the LED chip 20 from being emitted to the adjacent LED chip 20, thereby reducing the light crosstalk between the LED chips 20. On the other hand, the reflective layer 52 reflects the light emitted from the LED chip 20 to the reflective layer 52, which prevents the light from being emitted from the sidewall of the LED chip 20, which is beneficial for emitting more light from the LED chip 20 from the light-emitting surface. Thus, the light extraction efficiency of the LED chip 20 is improved.

FIG. 9 is a schematic structural diagram of a third display panel provided by an embodiment of the application. Referring to FIG. 9, optionally, the display panel further includes an isolation wall 50, the isolation wall 50 is disposed between adjacent LED chips 20, and a first trench 51 is formed between the LED chip 20 and the adjacent isolation wall 50. In the present application, an isolation wall 50 and a first trench 51 are provided between two adjacent LED chips 20, which facilitates the bonding process between the substrate 10 and the LED chip 20, and the solder blocking the solder joints is separated from the first groove on the side of the isolation wall 50. A groove 51 expands into the first groove 51 on the other side of the isolation wall 50, thereby blocking the lateral expansion of the solder, which is beneficial to prevent the short connection of the solder between adjacent solder joints, and avoids between adjacent LED chips 20 The short-circuit effect of the electrodes improves the bonding yield.

FIG. 10 is a schematic structural diagram of a fourth display panel provided by an embodiment of the application. Referring to FIG. 10, optionally, the display panel further includes a first insulating layer 47. The first insulating layer 47 on the mesa of the LED epitaxial structure is provided with openings. Along the thickness direction of the first semiconductor layer 22, the openings overlap with the first electrode 21, that is, along the thickness direction of the first semiconductor layer 22, the openings are The projection on the first insulating layer 47 overlaps with the projection of the first electrode 21 on the first insulating layer 47. The light emitting diode chip 20 includes a mesa and sidewalls; the mesas and sidewalls are the mesas and sidewalls of the LED epitaxial structure; the first electrode 21 covers the mesa and covers the part of the first insulating layer 47 on the sidewalls. In the present application, the first electrode 21 is provided to cover the mesa and the part of the first insulating layer 47 on the sidewall, so that the first electrode 21 not only functions as an electrode but also functions as a reflective layer. Therefore, the first electrode 21 can also block the LED chip. The light emitted by 20 is emitted to adjacent LED chips 20, which reduces the light crosstalk between the LED chips 20, and can prevent the light from being emitted from the side walls of the LED chip 20, which is beneficial to more light emitted by the LED chip 20. Surface emission, thereby improving the light emission efficiency of the LED chip 20. In addition, compared with the production of the first electrode 21 and the reflective layer separately, the present application reduces the manufacturing process of the reflective layer, thereby simplifying the process steps.

The application also provides a display device. The display device includes a display panel as provided in any embodiment of the present application, and the display device may be, for example, a mobile phone, a tablet computer, a computer, a television, or a smart wearable device. The display device includes the display panel provided by any embodiment of the present application, and its technical principles and technical effects are similar, and will not be repeated here.

The embodiment of the application also provides a manufacturing method of the display panel. FIG. 11 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the application. Referring to FIG. 11, the manufacturing method of the display panel includes the following steps.

S410. Provide an LED chip array, the LED chip array includes a plurality of LED chips, and the LED chip includes a first electrode and a first semiconductor layer.

S420. Fabricate a conductive layer on the side of the LED chip away from the first electrode; the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow part, and the hollow part and the first electrode are on the same plane along the thickness direction of the first semiconductor layer The projections overlap.

In this application, a conductive layer is fabricated on the side of the LED chip away from the first electrode; the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow part, and the hollow part overlaps the first electrode along the thickness direction of the first semiconductor layer. In the first aspect, the conductive layer of the display panel made by this application is in contact with the first semiconductor layer, so that both the conductive layer and the first semiconductor layer serve as the current conducting layer of the LED chip, reducing the resistance of the current conducting layer and improving The brightness uniformity of the display panel is improved. In the second aspect, the surface of the first semiconductor layer is flat, which facilitates the contact conduction between the entire surface of the conductive layer and the entire surface of the first semiconductor layer, thereby helping to avoid poor contact between the conductive layer and the first semiconductor layer, as well as avoiding due to alignment The inaccuracy causes the problem of contact between the conductive layer and other film layers of the LED chip. Therefore, the present application improves the yield of the display panel, and the production of the conductive layer can be implemented based on related processes, which has low process difficulty and is easy to implement. In the third aspect, the hollow part of the conductive layer overlaps the first electrode, that is, the hollow part of the conductive layer overlaps the LED chip, so that the light emitted by the LED chip can be emitted through the hollow part. Therefore, the present application is beneficial to reduce current conduction. The resistance of the pass layer does not affect the light extraction rate of the display panel. In summary, the present application achieves the effect of reducing the resistance of the current conducting layer with lower process difficulty on the basis of ensuring the light output rate of the display panel.

Claims

A display panel including:

At least one light-emitting diode chip, the light-emitting diode chip comprising a first electrode and a first semiconductor layer arranged in a stack;

A conductive layer located on the side of the light emitting diode chip away from the first electrode;

Wherein, the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow portion, and along the thickness direction of the first semiconductor layer, the projection of the hollow portion on the conductive layer is the same as that of the first semiconductor layer. The projection of an electrode on the conductive layer overlaps.
The display panel of claim 1, wherein along the thickness direction of the first semiconductor layer, the projection shape of the conductive layer is a grid, a strip, or a concentric ring.
2. The display panel of claim 1, wherein the conductive layer further comprises a non-hollowed part, and the non-hollowed part is opaque.
The display panel of claim 1, wherein the conductive layer is a metal conductive layer.
The display panel according to claim 4, wherein the material of the conductive layer includes at least one of aluminum, copper, titanium, or silver.
The display panel of claim 1, further comprising a reflective layer, the light emitting diode chip includes a side wall, and the reflective layer is located on the side wall of the light emitting diode chip.
The display panel according to claim 1, wherein the light-emitting diode chip further comprises a multiple quantum well layer and a second semiconductor layer stacked in sequence, and the multiple quantum well layer is located far from the first semiconductor layer. On one side of the conductive layer, the second semiconductor layer is located on the side of the multiple quantum well layer away from the first semiconductor layer.
8. The display panel of claim 7, wherein the first semiconductor layer is N-type gallium nitride, and the second semiconductor layer is P-type gallium nitride.
8. The display panel according to any one of claims 1 to 8, wherein the number of the light emitting diode chips is multiple;

The display panel further includes an isolation wall disposed between the adjacent light emitting diode chips, and a first trench is formed between the light emitting diode chip and the adjacent isolation wall.
The display panel of claim 9, wherein the first semiconductor layer is a common layer of a plurality of light emitting diode chips.
The display panel according to claim 9, further comprising: a first insulating layer, the first insulating layer includes an opening, and the opening is formed in the first insulating layer along the thickness direction of the first semiconductor layer. The projection on the overlap with the projection of the first electrode on the first insulating layer;

The light-emitting diode chip further includes a mesa;

The first electrode covers the mesa and covers the part of the first insulating layer on the sidewall.
A display device, comprising: the display panel according to any one of claims 1-11.
A manufacturing method of a display panel includes:

Provide a light-emitting diode chip array, the light-emitting diode chip array includes a plurality of light-emitting diode chips, the light-emitting diode chip includes a first electrode and a first semiconductor layer;

A conductive layer is fabricated on the side of the light emitting diode chip away from the first electrode; the conductive layer is in contact with the first semiconductor layer; the conductive layer includes a hollow portion along the thickness direction of the first semiconductor layer The projection of the hollow portion on the conductive layer overlaps with the projection of the first electrode on the conductive layer.
13. The method of manufacturing a display panel according to claim 13, wherein the LED chip array is provided with a substrate at the same time, the LED chip array further comprises a second substrate, and the plurality of LED chips are located at the same time. Mentioned on the second substrate.
14. The method for manufacturing a display panel according to claim 14, wherein after the substrate and the LED chip array are provided, the substrate and the LED chip array are bound; then the LED chip array is removed The second substrate.
15. The manufacturing method of the display panel according to claim 15, wherein the bonding method of the substrate and the LED chip array is flip-chip bonding, so that the first electrode is electrically connected to the substrate.
The method for manufacturing the display panel according to claim 14, 15 or 16, wherein the method for manufacturing the LED chip array comprises:

Preparation of light-emitting diode epitaxial wafers;

Etching the LED epitaxial wafer to form the LED epitaxial structure and isolation grooves;

Filling the isolation trench to form a second insulating layer;

A first electrode is fabricated on the surface of the LED epitaxial structure away from the second substrate to form the LED chip array.
18. The manufacturing method of the display panel according to claim 17, wherein the height of the second insulating layer is consistent with the height of the mesa of the light emitting diode epitaxial structure.
The method for manufacturing the display panel according to claim 14, 15 or 16, wherein the method for manufacturing the LED chip array comprises:

Preparation of light-emitting diode epitaxial wafers;

Etching the LED epitaxial wafer to form the LED epitaxial structure and isolation grooves;

Forming a first insulating layer on the bottom surface and sidewall surface of the isolation trench to form a second trench;

A first electrode is fabricated on the surface of the light-emitting diode epitaxial structure away from the second substrate to form a light-emitting diode chip array.
The method for manufacturing the display panel according to claim 19, wherein the thickness of the first insulating layer is smaller than the depth of the isolation trench, so that the first insulating layer can form the second trench.