CN116916525A - PCB with inner layer transmission line test structure and PCB manufacturing method - Google Patents
PCB with inner layer transmission line test structure and PCB manufacturing method Download PDFInfo
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- CN116916525A CN116916525A CN202311184011.5A CN202311184011A CN116916525A CN 116916525 A CN116916525 A CN 116916525A CN 202311184011 A CN202311184011 A CN 202311184011A CN 116916525 A CN116916525 A CN 116916525A
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- 238000012360 testing method Methods 0.000 title claims abstract description 155
- 230000005540 biological transmission Effects 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 238000012545 processing Methods 0.000 claims abstract description 20
- 239000003292 glue Substances 0.000 claims description 14
- 230000008054 signal transmission Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 238000005553 drilling Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000013461 design Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 9
- 238000003825 pressing Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000003801 milling Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 97
- 238000010586 diagram Methods 0.000 description 12
- 239000002344 surface layer Substances 0.000 description 6
- 238000005457 optimization Methods 0.000 description 4
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application provides a PCB with an inner layer transmission line test structure and a PCB manufacturing method, wherein the PCB with the inner layer transmission line test structure comprises a first outer layer core plate, a second outer layer core plate and an inner layer circuit arranged between the first outer layer core plate and the second outer layer core plate, and adjacent core plates are connected through prepregs; the inner layer circuit is provided with a plurality of inner bonding pads; the prepreg is provided with a test port for leaking the inner bonding pad; the first outer core plate or the second outer core plate is provided with a test channel communicated with the test port; the test channels are arranged in one-to-one correspondence with the test ports, after the inner layer circuit is manufactured and laminated, the inner layer transmission line test is directly performed through the inner layer circuit bonding pads by arranging the test channels, so that test deviation caused by the through holes in the outer layer test is removed, the accuracy of test results is improved, and meanwhile, after the test is completed, the test channels are filled with resin, and the processing and manufacturing of the subsequent outer layer circuit are not affected.
Description
Technical Field
The application relates to the technical field of printed circuit board manufacturing, in particular to a PCB with an inner layer transmission line test structure and a PCB manufacturing method.
Background
As signal transmission tends to be high-speed and high-frequency, the rise time of signals is shorter and shorter, and the signal transmission frequency and transmission rate in PCBs are also continuously increasing. Meanwhile, the transmission line effect is more serious due to the high speed and high frequency development of signal transmission, and the problems of crosstalk, reflection and the like are more likely to occur in the transmission process of signals, so that in order to keep the integrity of signal transmission, a targeted design is required to be made in the design and manufacturing process of a PCB.
The transmission line test of the PCB surface layer can be directly carried out through the bonding pads connected by the transmission line. And the PCB test inner layer transmission line needs to additionally pass through the surface layer test pad, and the metallized via hole is connected with the inner layer transmission line. The via hole can cause discontinuous impedance on the transmission line, so that signal reflection is caused, the equivalent impedance of the via hole is about 12% lower than that of the transmission line, parasitic capacitance, inductance and other problems can be generated in the via hole, 0.7dB loss can be generated in a conventional via hole, and inaccurate test results can be caused for a high-speed PCB.
In the existing production, after the inner layer circuit and the outer layer circuit of the whole board are manufactured, the inner layer transmission line of the PCB needs to be tested through a gold metallization via hole by a bonding pad on the surface layer of the whole board. In the operation mode, the test result is deviated from the actual test result, and the processing of the PCB is not optimized.
Disclosure of Invention
In order to overcome the problems in the related art, the application provides a PCB with an inner layer transmission line test structure and a PCB manufacturing method.
One of the purposes of the application is a PCB with an inner layer transmission line test structure, which comprises a first outer layer core board, a second outer layer core board and an inner layer circuit arranged between the first outer layer core board and the second outer layer core board, wherein adjacent core boards are connected through prepregs;
the inner layer circuit is provided with a plurality of inner bonding pads;
the prepreg is provided with a test port for leaking the inner bonding pad;
a test channel communicated with the test port is formed in the first outer core plate or the second outer core plate;
the test channels are arranged in one-to-one correspondence with the test ports.
In a preferred technical scheme of the application, the inside of the test channel is filled with resin;
the resin filled surface is provided with an outer bond pad that connects to an inner bond pad via a metallized via.
In a preferred technical scheme of the application, the inner layer circuit is arranged on the first outer layer core plate and/or the second outer layer core plate.
In a preferred technical scheme of the application, at least one inner core plate is arranged between the first outer core plate and the second outer core plate, and an inner circuit is arranged on the inner core plate.
In the preferred technical scheme of the application, the test port is reserved with a glue flow avoiding gap at the line side, and the distances between the other three sides of the test port and the bonding pad are larger than the glue avoiding gap.
In the preferred technical scheme of the application, the test channel is tangent to the bonding pad at the line side, the rest sides of the test channel are positioned at the inner side of the test port, and the distance between the rest sides of the test channel and the corresponding sides of the test port is not smaller than the glue flow avoiding gap.
The second object of the present application is to provide a method for manufacturing a PCB:
windowing the surface of the whole board, and leaking out an inner layer circuit bonding pad;
signal transmission test is carried out on the inner circuit through the inner circuit bonding pad;
filling up the windowed window after the test is completed;
manufacturing a through hole bonding pad at the filling part, wherein the through hole bonding pad is an inner layer circuit bonding pad communicated with the surface of the whole board;
and manufacturing an outer layer circuit.
In a preferred technical scheme of the application, the specific manufacturing steps are as follows:
s1, cutting: cutting a PCB core board with a required size;
s2, manufacturing an inner layer circuit: processing and manufacturing an inner layer circuit on the core plate
S3, milling grooves: slotting the joint part of the prepreg and the inner layer circuit bonding pad to leak the inner layer circuit bonding pad;
s4 lamination: stacking the core plates and the prepregs according to the design and then pressing to form a whole plate;
s5, uncovering: windowing on the surface of the whole board to leak out an inner layer circuit bonding pad;
s6, testing signals of the inner layer transmission line: performing signal transmission test on the inner layer transmission line through the inner layer line bonding pad;
s7, filling and curing: filling resin in the window and curing the filled resin;
s8, flattening: cutting the outer side surface of the resin to be flush with the base material of the outer core plate;
s9, drilling: drilling holes on the preset position of the whole board and the bonding pad part of the inner layer circuit;
s10, copper deposition electroplating: attaching a copper layer in the resin and the hole wall;
s11 grinding: polishing the copper surface of the outer side surface of the whole plate to be smooth;
s12, manufacturing an outer layer circuit: and processing and manufacturing an outer layer circuit on the whole plate.
In the preferred technical scheme of the application, in the step S3, a gummosis avoiding gap is reserved on the line side of the slotting, so that the gummosis of the prepreg on the line side is avoided, a test avoiding gap is reserved on the other three sides of the slotting, and the test avoiding gap is larger than the gummosis avoiding gap.
In the preferred technical scheme of the application, in the step S5, the laser is used for windowing, the windowing is tangential to the bonding pad at the line side, the windowing is positioned at the inner side of the test port at the other sides, and the distance between the other sides and the corresponding side surfaces of the slotting is not smaller than the gummosis avoiding gap.
The beneficial effects of the application are as follows:
the PCB with the inner layer transmission line testing structure is provided, after the inner layer circuit is manufactured and laminated, the inner layer transmission line can be tested by directly carrying out inner layer transmission line testing through the inner layer circuit bonding pad by arranging the testing channel, so that the testing deviation caused by the via hole in the outer layer testing process is removed, the accuracy of the testing result is improved, and meanwhile, after the testing is finished, the testing channel is filled with resin, and the processing and manufacturing of the subsequent outer layer circuit are not affected.
The PCB manufacturing method has the advantages that after the inner layer circuit is manufactured and laminated, the inner layer transmission line test is directly carried out through the inner layer circuit bonding pad through windowing, test deviation caused by the through holes when the inner layer transmission line test is carried out on the outer side after the whole board is manufactured can be avoided, the accuracy of test results is improved, meanwhile, after the test is finished, the windowing part is filled with resin, and the processing and manufacturing of the subsequent outer layer circuit are not affected. In the production process, the aperture can be reduced for subsequent PCB processing according to the test result, and loss optimization such as back drilling and the like can be reduced, so that the yield of products can be improved.
Drawings
Fig. 1 is a schematic diagram of a dual-layer PCB board structure with an inner layer transmission line test structure.
Fig. 2 is a schematic diagram of a multi-layer PCB board structure with an inner layer transmission line test structure.
FIG. 3 is a schematic diagram of a test port.
FIG. 4 is a schematic diagram of a test channel opening range.
Fig. 5 is a schematic view of the uncovering step.
FIG. 6 is a schematic diagram of an inner layer transmission line signal testing step.
Fig. 7 is a schematic diagram of a fill curing step.
Fig. 8 is a schematic diagram of a flattening step.
Fig. 9 is a schematic diagram of a drilling step.
Fig. 10 is a schematic diagram of a copper deposition electroplating step.
FIG. 11 is a schematic diagram of a milling step.
Fig. 12 is a data diagram of a conventional board-in-board transmission line test performed from outside the circuit board.
Fig. 13 is a data diagram of an inner layer transmission line test performed on a PCB having an inner layer transmission line test structure.
Reference numerals:
100. a first outer core plate; 200. a second outer core panel; 300. an inner layer circuit; 400. an inner bonding pad; 500. a test channel; 600. a resin; 700. a prepreg; 800. an inner core plate; 900. and a test port.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as information, and similarly, the information may also be referred to as first information, without departing from the scope of the application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
With the trend of high speed and high frequency of signal transmission, the rise time of signals is shorter and shorter, and the signal transmission frequency and transmission rate in the PCB are also continuously improved. Meanwhile, the transmission line effect is more serious due to the high speed and high frequency development of signal transmission, and the problems of crosstalk, reflection and the like are more likely to occur in the transmission process of signals, so that in order to keep the integrity of signal transmission, a targeted design is required to be made in the design and manufacturing process of a PCB.
The transmission line test of the PCB surface layer can be directly carried out through the bonding pads connected by the transmission line. And the PCB test inner layer transmission line needs to additionally pass through the surface layer test pad, and the metallized via hole is connected with the inner layer transmission line. The via hole can cause discontinuous impedance on the transmission line, so that signal reflection is caused, the equivalent impedance of the via hole is about 12% lower than that of the transmission line, parasitic capacitance, inductance and other problems can be generated in the via hole, 0.7dB loss can be generated in a conventional via hole, and inaccurate test results can be caused for a high-speed PCB.
In the existing production, after the inner layer circuit and the outer layer circuit of the whole board are manufactured, the inner layer transmission line of the PCB needs to be tested through a gold metallization via hole by a bonding pad on the surface layer of the whole board. In the operation mode, the test result is deviated from the actual test result, and the processing of the PCB is not optimized.
In view of the above-mentioned problems, the present embodiment provides a PCB with an inner layer transmission line testing structure, so as to remove the testing deviation caused by the via hole during the outer layer testing, and not to affect the processing of the outer layer line while improving the accuracy of the testing result. Through testing the inner layer transmission line, the aperture can be reduced for subsequent processing according to the test result, loss reduction optimization such as back drilling is realized, and the yield of products is improved.
As shown in fig. 1 to 4, a PCB having an inner transmission line testing structure includes a first outer core board 100, a second outer core board 200, and an inner circuit 300 disposed between the first outer core board 100 and the second outer core board 200, adjacent core boards being connected via a prepreg 700;
the inner layer circuit 300 has a plurality of inner pads 400;
the prepreg 700 is provided with a test port 900 for leaking the inner bonding pad 400;
the first outer core board 100 or the second outer core board 200 is provided with a test channel 500 which is communicated with the test port 900;
the test channels 500 are arranged in one-to-one correspondence with the test ports 900;
in this embodiment, the inside of the test channel 500 is filled with a resin 600;
the resin 600 filled surface is provided with outer pads that connect to the inner pads 400 via metallized vias.
In practical application, after the test is completed, the thermosetting resin 600 is adopted to fill the test channel 500 and the test port 900, and the thermosetting resin 600 is heated and pressurized to be cured and leveled, so that the filling of the thermosetting resin 600 is flush with the board surface.
The PCB with the inner layer transmission line test structure can be used for directly carrying out inner layer transmission line test through the bonding pad of the inner layer circuit 300 after the inner layer circuit 300 is manufactured and laminated, and the test channel 500 is formed, so that test deviation caused by the through hole in outer layer test is removed, the accuracy of test results is improved, and meanwhile, after the test is finished, the test channel 500 is filled with the resin 600, and the processing and manufacturing of the subsequent outer layer circuit are not affected.
In one embodiment, as shown in fig. 1, the PCB is designed as a double-layered board, and the inner layer wire 300 is disposed on the first outer core board 100 and/or the second outer core board.
In another embodiment, as shown in fig. 2, the PCB is designed as a multi-layer board, at least one inner core board 800 is disposed between the first and second outer core boards 100 and 200, and the inner core board 800 is provided with an inner circuit 300 thereon.
In this embodiment, the test port 900 reserves a glue flow avoiding gap at the line side, and when the laminated boards are pressed, the prepreg 700 will flow, and the reserved glue flow avoiding gap can avoid the prepreg 700 from flowing to a bonding pad, which affects the subsequent test; the distance between the remaining three sides of the test port 900 and the bonding pad is greater than the glue relief gap to provide room for subsequent testing.
In this embodiment, the test channel 500 is tangent to the bonding pad at the line side, the rest sides of the test channel 500 are located at the inner side of the test port 900, and the distance between the rest sides of the test channel 500 and the corresponding sides of the test port 900 is not smaller than the glue flow avoiding gap.
Example 2
This embodiment only describes the differences from embodiment 1, and the remaining technical features are the same as those of the above-described embodiment. Further, embodiment 2 provides a method for fabricating a PCB, the PCB fabricated by the method including the structure of embodiment 1.
The second object of the present application is to provide a method for manufacturing a PCB:
windowing the surface of the whole board, and leaking out the bonding pad of the inner layer circuit 300;
signal transmission test is carried out on the inner circuit through the bonding pad of the inner circuit 300;
filling up the windowed window after the test is completed;
the filling part is provided with a through hole bonding pad, and the bonding pad of the inner layer circuit 300 is communicated with the surface of the whole board;
and manufacturing an outer layer circuit.
According to the method, after the inner layer circuit 300 is manufactured and laminated, the inner layer transmission line test is directly carried out through the inner layer circuit 300 bonding pad through windowing, so that test deviation caused by the through holes when the inner layer transmission line test is carried out on the outer side after the whole board is manufactured can be avoided, the accuracy of a test result is improved, meanwhile, the windowing part is filled through the resin 600 after the test is completed, and the processing and manufacturing of the subsequent outer layer circuit are not affected. In the production process, the aperture can be reduced for subsequent PCB processing according to the test result, and loss optimization such as back drilling and the like can be reduced, so that the yield of products can be improved.
As shown in fig. 2 to 11, taking a 3-layer PCB as an example, the 3-layer PCB is formed by disposing an inner core board 800 between a first outer core board 100 and a second outer core board 200, and specific manufacturing steps of the 3-layer PCB are as follows:
s1, cutting: cutting out a PCB core board with a required size, wherein the PCB core board comprises a first outer core board 100, an inner core board 800 and a second outer core board 200;
s2, manufacturing an inner layer circuit 300: processing and manufacturing an inner layer circuit 300 on the inner layer core plate 800;
s3, milling grooves: a test port 900 is formed in the prepreg 700 at a position where the prepreg is attached to the bonding pad of the inner circuit 300 in a slotting manner so as to leak out the bonding pad of the inner circuit 300;
s4 lamination: sequentially stacking the first outer core plate 100, the semi-cured inner core plate 800, the semi-cured outer core plate 200 and the second outer core plate 200 according to the design, and then pressing to form a whole plate;
s5, uncovering: windowing on the whole surface of the board, and processing a test channel 500 to leak out the inner bonding pad 400 of the inner layer circuit 300;
s6, testing signals of the inner layer transmission line: signal transmission testing is performed on the inner layer transmission line through the inner pad 400 of the inner layer line 300;
s7, filling and curing: filling thermosetting resin 600 in the window, and performing heating and pressurizing curing treatment on the filled resin 600 to enable the resin 600 to be filled to be flush with the surface of the whole plate;
s8, flattening: cutting the outer side surface of the resin 600 to be flush with the base material of the outer core plate by laser;
s9, drilling: drilling holes on the preset position of the whole board and the bonding pad part of the inner layer circuit 300;
s10, copper deposition electroplating: attaching a copper layer to the inside of the resin 600 and the hole wall;
s11 grinding: polishing the copper surface of the outer side surface of the whole plate to be smooth so as to facilitate the subsequent outer layer circuit processing;
s12, manufacturing an outer layer circuit: and processing and manufacturing an outer layer circuit on the whole plate.
In the preferred technical scheme of the application, in step S3, a gummosis avoiding gap is reserved on the line side of the slotting, so that the gummosis of the line side prepreg 700 on a bonding pad is avoided, and the rest three sides of the slotting are reserved with a test avoiding gap which is larger than the gummosis avoiding gap. When the laminated plates are pressed, the prepreg 700 can generate gummosis, and the gummosis avoiding gap is reserved, so that the influence on the follow-up test caused by gummosis of the prepreg 700 can be avoided; the distance between the remaining three sides of the test port 900 and the bonding pad is greater than the glue relief gap to provide room for subsequent testing.
In the preferred technical scheme of the application, in step S5, the windowing is performed by using laser, the windowing is tangential to the bonding pad at the line side, the windowing is positioned at the inner side of the test port 900 at the other sides, and the distance between the other sides and the corresponding sides of the slotting is not smaller than the gummosis avoiding gap. The purpose of this design is to avoid the flow of prepreg 700, avoiding the connection of material to the flow of prepreg 700 when the material is removed after windowing.
In practical application, the gumming avoiding gap is determined according to gumming parameters of the adopted prepreg 700 during stacking and pressing, and the stacking and pressing are 0.6mm in the maximum gumming distance according to stacking and pressing parameters and the adopted non-gumming prepreg 700 property, so that the gumming avoiding gap is designed to be 0.6mm, the test avoiding gap is designed to be 3.1mm, the window is arranged to be tangent to the bonding pad at the line side, the window is positioned in the test port 900 at the other sides, and the distance between the window and the corresponding side of the slot is designed to be 2.5mm.
In practical application, the circuit on the core board between the bonding pad of the inner layer circuit 300 and the surface of the whole board needs to be designed in a avoidance way at the windowing part, and the avoidance design is specifically that the windowing part of the core board does not have an image circuit.
As shown in fig. 12-13, the inner layer transmission line test was performed on the same length transmission line using the existing PCB and the present design PCB, respectively. As can be seen by comparison, the upper graph in FIG. 12 shows that the loss value detected during testing is very large because the conventional PCB has a via structure, and the PCB in FIG. 13 shows that the PCB can be tested without passing through the via structure, and the detected loss value is very small. The lower graph in fig. 12 shows that the phase data detected by the via structure is very dispersed, and the lower graph in fig. 13 shows that the phase data detected by the inner layer of the PCB board of the present design is regularly changed. Therefore, the PCB board of the design is helpful to eliminate interference through the direct detection of the inner layer, and is beneficial to directly summarizing phenomena and rules according to the measured data. In the production process, the aperture can be reduced for subsequent PCB processing according to the test result, and loss optimization such as back drilling and the like can be reduced, so that the yield of products can be improved.
The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures. In the description of the present application, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "horizontal direction, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present application; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present application.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A PCB with an inner layer transmission line test structure comprises a first outer layer core plate, a second outer layer core plate and an inner layer circuit arranged between the first outer layer core plate and the second outer layer core plate, wherein adjacent core plates are connected through prepregs;
the method is characterized in that:
the inner layer circuit is provided with a plurality of inner bonding pads;
the prepreg is provided with a test port for leaking the inner bonding pad;
a test channel communicated with the test port is formed in the first outer core plate or the second outer core plate;
the test channels are arranged in one-to-one correspondence with the test ports.
2. The PCB with an inner layer transmission line test structure of claim 1, wherein:
the inside of the test channel is filled with resin;
the resin filled surface is provided with an outer bond pad that connects to an inner bond pad via a metallized via.
3. The PCB with an inner layer transmission line test structure of claim 1, wherein:
the inner layer circuit is arranged on the first outer layer core plate and/or the second outer layer core plate.
4. The PCB with an inner layer transmission line test structure of claim 1, wherein:
at least one inner core plate is arranged between the first outer core plate and the second outer core plate, and an inner circuit is arranged on the inner core plate.
5. The PCB with an inner layer transmission line test structure of claim 1, wherein:
and the distance between the other three sides of the test port and the bonding pad is greater than the glue avoiding gap.
6. The PCB with an inner layer transmission line test structure of claim 5, wherein:
the test channel is tangent to the bonding pad at the line side, the rest sides of the test channel are positioned at the inner side of the test port, and the distance between the rest sides of the test channel and the corresponding sides of the test port is not smaller than the glue flowing avoiding gap.
7. A PCB manufacturing method is characterized in that:
windowing the surface of the whole board, and leaking out an inner layer circuit bonding pad;
signal transmission test is carried out on the inner circuit through the inner circuit bonding pad;
filling up the windowed window after the test is completed;
manufacturing a through hole bonding pad at the filling part, wherein the through hole bonding pad is an inner layer circuit bonding pad communicated with the surface of the whole board;
and manufacturing an outer layer circuit.
8. The method for manufacturing a PCB according to claim 7, wherein:
the specific manufacturing steps are as follows:
s1, cutting: cutting a PCB core board with a required size;
s2, manufacturing an inner layer circuit: processing and manufacturing an inner layer circuit on the core plate
S3, milling grooves: slotting the joint part of the prepreg and the inner layer circuit bonding pad to leak the inner layer circuit bonding pad;
s4 lamination: stacking the core plates and the prepregs according to the design and then pressing to form a whole plate;
s5, uncovering: windowing on the surface of the whole board to leak out an inner layer circuit bonding pad;
s6, testing signals of the inner layer transmission line: performing signal transmission test on the inner layer transmission line through the inner layer line bonding pad;
s7, filling and curing: filling resin in the window and curing the filled resin;
s8, flattening: cutting the outer side surface of the resin to be flush with the base material of the outer core plate;
s9, drilling: drilling holes on the preset position of the whole board and the bonding pad part of the inner layer circuit;
s10, copper deposition electroplating: attaching a copper layer in the resin and the hole wall;
s11 grinding: polishing the copper surface of the outer side surface of the whole plate to be smooth;
s12, manufacturing an outer layer circuit: and processing and manufacturing an outer layer circuit on the whole plate.
9. The method for manufacturing a PCB according to claim 8, wherein:
in step S3, a glue flowing avoiding gap is reserved on the line side of the slot, so that the situation that a welding pad is arranged on the line side prepreg in a glue flowing mode is avoided, and test avoiding gaps are reserved on the other three sides of the slot, wherein the test avoiding gaps are larger than the glue avoiding gaps.
10. The method for manufacturing a PCB according to claim 8, wherein:
in step S5, the window is opened by using laser, the window is tangent to the bonding pad at the line side, the window is positioned at the inner side of the test port at the other sides, and the distance between the other sides and the corresponding side of the slot is not smaller than the glue flow avoiding gap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311184011.5A CN116916525A (en) | 2023-09-14 | 2023-09-14 | PCB with inner layer transmission line test structure and PCB manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311184011.5A CN116916525A (en) | 2023-09-14 | 2023-09-14 | PCB with inner layer transmission line test structure and PCB manufacturing method |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311184011.5A Pending CN116916525A (en) | 2023-09-14 | 2023-09-14 | PCB with inner layer transmission line test structure and PCB manufacturing method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030162310A1 (en) * | 2002-02-26 | 2003-08-28 | Mitsubishi Denki Kabushiki Kaisha | Characteristics evaluation of intermediate layer circuit |
| JP2005347292A (en) * | 2004-05-31 | 2005-12-15 | Shinko Electric Ind Co Ltd | Wiring board |
| JP2006114744A (en) * | 2004-10-15 | 2006-04-27 | Hitachi Chem Co Ltd | Resistive element mounting sheet and manufacturing method thereof, and manufacturing method of multilayer wiring board containing resistors using the same |
| US20080149382A1 (en) * | 2006-12-26 | 2008-06-26 | Kabushiki Kaisha Toshiba | Method of inspecting printed wiring board and printed wiring board |
| CN105744719A (en) * | 2014-10-31 | 2016-07-06 | 旺矽科技股份有限公司 | Multi-layer circuit board |
-
2023
- 2023-09-14 CN CN202311184011.5A patent/CN116916525A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030162310A1 (en) * | 2002-02-26 | 2003-08-28 | Mitsubishi Denki Kabushiki Kaisha | Characteristics evaluation of intermediate layer circuit |
| JP2005347292A (en) * | 2004-05-31 | 2005-12-15 | Shinko Electric Ind Co Ltd | Wiring board |
| JP2006114744A (en) * | 2004-10-15 | 2006-04-27 | Hitachi Chem Co Ltd | Resistive element mounting sheet and manufacturing method thereof, and manufacturing method of multilayer wiring board containing resistors using the same |
| US20080149382A1 (en) * | 2006-12-26 | 2008-06-26 | Kabushiki Kaisha Toshiba | Method of inspecting printed wiring board and printed wiring board |
| CN105744719A (en) * | 2014-10-31 | 2016-07-06 | 旺矽科技股份有限公司 | Multi-layer circuit board |
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