CN116913951A - Double-channel enhanced GaN HEMT device with P-type buried layer - Google Patents

Double-channel enhanced GaN HEMT device with P-type buried layer Download PDF

Info

Publication number
CN116913951A
CN116913951A CN202311063697.2A CN202311063697A CN116913951A CN 116913951 A CN116913951 A CN 116913951A CN 202311063697 A CN202311063697 A CN 202311063697A CN 116913951 A CN116913951 A CN 116913951A
Authority
CN
China
Prior art keywords
layer
gan
conductive material
channel
buried layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311063697.2A
Other languages
Chinese (zh)
Inventor
罗小蓉
骆成涛
杨铖
魏雨夕
赵智家
薛刚
邱金朋
沈竞宇
魏杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
China Resources Microelectronics Chongqing Ltd
Original Assignee
University of Electronic Science and Technology of China
China Resources Microelectronics Chongqing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China, China Resources Microelectronics Chongqing Ltd filed Critical University of Electronic Science and Technology of China
Priority to CN202311063697.2A priority Critical patent/CN116913951A/en
Publication of CN116913951A publication Critical patent/CN116913951A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a double-channel enhanced GaN HEMT device with a P-type buried layer. The structure has two layers of channel 2DEG, so that the on-resistance of the device can be obviously reduced, and the saturated output current of the device can be improved. The method is characterized in that: the p-GaN buried layer short-circuited with the source electrode potential has an auxiliary depletion effect on the 2DEG in the lower-layer channel, and the p-GaN buried layer and the MIS gate or the p-GaN gate are combined to have a depletion effect on the 2DEG below the gate, so that the enhancement of the device is realized; when the device is blocked in the forward direction, the p-GaN buried layer is favorable for expanding the width of the depletion region, the electric field peak value at the edge of the grid electrode is reduced, meanwhile, the p-GaN buried layer is used as a blocking layer, the leakage current passing through the buffer layer between the source electrode and the drain electrode is reduced, and the p-GaN buried layer and the blocking layer jointly improve the breakdown voltage of the device.

Description

Double-channel enhanced GaN HEMT device with P-type buried layer
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a double-channel enhanced GaN HEMT device with a P-type buried layer.
Background
The GaN material has the excellent characteristics of high critical breakdown electric field, high electron mobility, high electron saturation velocity, wider forbidden bandwidth and the like, so that the GaN power device has the advantages of high breakdown voltage, high switching speed, low conduction loss, small off-state leakage current, good high-temperature characteristic and the like, and is widely applied to the fields of high frequency, high voltage and high power. However, for AlGaN/GaN HEMT device applications, there are challenges: on the one hand, in the blocking state of the device, the device breaks down in advance due to the reasons of electric field peak, overlarge surface leakage current, overlarge substrate leakage current and the like existing on the side, close to the drain, of the edge of the grid, and the withstand voltage of the device is far less than the theoretical limit of a GaN material; on the other hand, due to the spontaneous polarization effect and the piezoelectric polarization effect, high-concentration two-dimensional electron gas (2 DEG) exists at the AlGaN/GaN heterojunction interface, and it is difficult to obtain an enhanced high-voltage device of high threshold voltage.
In order to overcome the above problems, researchers have proposed a back electrode structure to improve the electric field distribution of the conventional p-GaN HEMT, realizing a higher breakdown voltage, but having a higher on-resistance; there are researchers that adopt MIS groove gate structure to realize enhanced MIS HEMT on GaN double channel platform, but because of the influence of electric field concentration effect of gate edge, the breakdown voltage of device is lower, and the excellent characteristics of high critical breakdown electric field of GaN material can not be fully developed.
Disclosure of Invention
Aiming at the problems, the invention provides a double-channel enhanced GaN HEMT device with a P-type buried layer. The structure remarkably reduces the on-resistance of the device and improves the saturated output current of the device through the coupling effect of the 2DEG in the two layers of channels under low grid voltage and a double-channel conduction mechanism under higher grid voltage. The p-GaN buried layer in short circuit with the source electrode potential has an auxiliary depletion effect on the 2DEG in the lower-layer channel, and the device enhancement is realized by combining the depletion effect of the MIS gate or the p-GaN gate on the 2DEG below the gate, so that the threshold voltage of the device is improved; when the device is blocked in the forward direction, a reverse bias PN junction depletion region formed by the p-GaN buried layer and the underlying GaN channel expands, so that the electric field peak value at the edge of the grid electrode is reduced, meanwhile, the p-GaN buried layer is used as a blocking layer to effectively inhibit leakage current passing through the buffer layer between the source electrode and the drain electrode, and the breakdown voltage of the device is effectively improved.
The technical scheme of the invention is as follows:
a double-channel enhanced GaN HEMT device with a P-type buried layer comprises a substrate layer 1, a GaN buffer layer 2, a lower GaN channel layer 4, a first barrier layer 5, an upper GaN channel layer 6, a second barrier layer 7 and a passivation layer 8 which are sequentially stacked from bottom to top along the vertical direction of the device; there is a first conductive material 9, a gate structure and a third conductive material 11 in this order from left to right in the lateral direction. The leading-out end of the first conductive material 9 is a source electrode; the grid structure is separated from the first conductive material 9 and the third conductive material 11; the third conductive material 11 extends downwards from the surface into the lower GaN channel layer 4 along the vertical direction, and the leading-out end of the third conductive material is a drain electrode;
the method is characterized in that heterojunction is formed between the second barrier layer 7 and the upper GaN channel layer 6 and between the first barrier layer 5 and the lower GaN channel layer 4, and a 2DEG is generated at the heterojunction interface; the top of the GaN buffer layer 2 is provided with a P-type GaN buried layer 3 near one side of the first conductive material 9, the first conductive material 9 extends downwards from the surface to the upper surface of the P-type GaN buried layer 3 along the vertical direction, the top of the P-type GaN buried layer 3 contacts with the bottom of the first conductive material 9 along the vertical direction of the device, and the P-type GaN buried layer 3 extends rightwards along the horizontal direction and spans the right side of the gate along the transverse direction of the device.
Further, the top of the P-type GaN buried layer 3 is in contact with the bottom of the lower GaN channel layer 4.
Furthermore, a space exists between the P-type GaN buried layer 3 and the underlying GaN channel layer 4, and the size of the space needs to ensure that the device can realize enhancement.
Further, the gate structure is composed of a P-type GaN layer 12 on the second barrier layer 7 and a second conductive material 10 on the P-type GaN layer 12; the contact between the second conductive material 10 and the P-type GaN layer 12 is schottky contact, and the gate electrode is led out from the upper surface of the second conductive material 10.
Further, the gate structure is an MIS groove gate structure, wherein the side wall and the bottom of the groove are insulated gate dielectric 13, and the groove is filled with second conductive material 10; the MIS groove gate structure extends downwards from the surface into the upper GaN channel layer 6 along the vertical direction, the insulated gate dielectric 13 is in contact with the upper GaN channel layer 6, the second barrier layer 7 and the passivation layer 8, and the upper surface of the second conductive material 10 is led out of the gate electrode.
Furthermore, the first barrier layer 5 is made of AlN and needs a certain N-type doping; the second barrier layer 7 is made of one or a combination of a plurality of AlN, alGaN, inGaN, inAlN materials.
The invention has the beneficial effects that:
1. the structure obviously reduces the on-resistance of the device and improves the saturated output current of the device through the coupling action of the 2DEG in the two layers of channels under the low gate voltage and the double-channel conduction mechanism under the high gate voltage. When the grid voltage is low, the two layers of channels below the grid electrode generate a coupling effect, so that the electron concentration in the lower layer of channels is enhanced, but the conductivity of the upper layer of channels is weaker at the moment; when the gate voltage is higher, an electron accumulation layer is generated in an upper channel below the gate, the upper channel has stronger conductive capacity, and at the moment, both channels participate in conduction.
2. The P-type GaN buried layer 3 short-circuited with the source electrode potential in the structure has an auxiliary depletion effect on the 2DEG in the lower-layer channel, and the device enhancement effect is realized by combining the depletion effect of the MIS gate or the P-GaN gate on the 2DEG below the gate.
3. When the structure is blocked in the forward direction, the P-type GaN buried layer 3 is favorable for expanding a depletion region, the electric field peak value of the edge of a grid electrode is reduced, meanwhile, the P-type GaN buried layer 3 serves as a blocking layer, leakage current passing through the buffer layer 2 between a source electrode and a drain electrode is reduced, and the breakdown voltage of a device is effectively improved.
Drawings
Fig. 1 is a schematic structural view of embodiment 1;
fig. 2 is a schematic structural view of embodiment 2;
FIG. 3 is a schematic structural view of embodiment 3;
fig. 4 is a schematic structural view of embodiment 4;
fig. 5 is a schematic structural view of embodiment 5.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples:
example 1
As shown in fig. 1, a dual channel enhancement type GaN HEMT device with a P-type buried layer includes a substrate layer 1, a GaN buffer layer 2, a lower GaN channel layer 4, a first barrier layer 5, an upper GaN channel layer 6, a second barrier layer 7 and a passivation layer 8, which are sequentially stacked from bottom to top in a vertical direction of the device; there is a first conductive material 9, a gate structure and a third conductive material 11 in this order from left to right in the lateral direction. The leading-out end of the first conductive material 9 is a source electrode; the grid structure is formed by a P-type GaN layer 12 positioned on a second barrier layer 7 and a second conductive material 10 positioned on the P-type GaN layer 12, the contact between the second conductive material 10 and the P-type GaN layer 12 is Schottky contact, and a grid electrode is led out from the upper surface of the second conductive material 10; the third conductive material 11 extends downward from the surface into the underlying GaN channel layer 4 in the vertical direction, and the leading-out end thereof is a drain electrode. Heterojunction is formed between the second barrier layer 7 and the upper GaN channel layer 6 and between the first barrier layer 5 and the lower GaN channel layer 4, and a 2DEG is generated at the heterojunction interface; a P-type GaN buried layer 3 is arranged on one side, close to the first conductive material 9, of the top of the GaN buffer layer 2, the first conductive material 9 extends downwards from the surface to the upper surface of the P-type GaN buried layer 3 along the vertical direction, the top of the P-type GaN buried layer 3 is in contact with the lower GaN channel layer 4 and the bottom of the first conductive material 9 along the vertical direction of the device, and the P-type GaN buried layer 3 extends rightwards along the horizontal direction and spans the right side of the gate along the transverse direction of the device.
The invention provides a double-channel enhanced GaN HEMT device with a P-type buried layer. The structure obviously reduces the on-resistance of the device and improves the saturated output current of the device through the coupling action of the 2DEG in the two layers of channels under the low gate voltage and the double-channel conduction mechanism under the high gate voltage. When the grid voltage is low, the two layers of channels below the grid electrode generate a coupling effect, so that the electron concentration in the lower layer of channels is enhanced, but the conductivity of the upper layer of channels is weaker at the moment; when the gate voltage is higher, an electron accumulation layer is generated in an upper channel below the gate, the upper channel has stronger conductive capacity, and at the moment, both channels participate in conduction. Meanwhile, the P-type GaN buried layer 3 short-circuited with the source electrode potential in the structure has an auxiliary depletion effect on the 2DEG in the lower-layer channel, and the MIS gate or the P-GaN gate is combined to have a depletion effect on the 2DEG below the gate, so that the enhancement of the device is realized. In addition, when the structure is blocked in the forward direction, the P-type GaN buried layer 3 is favorable for expanding a depletion region, the electric field peak value of the edge of a grid electrode is reduced, meanwhile, the P-type GaN buried layer 3 serves as a blocking layer, leakage current passing through the buffer layer 2 between a source electrode and a drain electrode is reduced, and the breakdown voltage of the device is effectively improved.
Example 2
The difference between this example and embodiment 1 is that, in this example, there is a space between the P-type GaN buried layer 3 and the underlying GaN channel layer 4 of the dual-channel enhancement type GaN HEMT device with a P-type buried layer, and the size of the space needs to ensure that the enhancement type of the device can be achieved.
Example 3
The difference between this example and embodiment 1 is that the gate structure of the dual channel enhancement type GaN HEMT device with P-type buried layer in this example is a MIS groove gate structure, the gate structure is a MIS groove gate structure, wherein the sidewall and bottom of the groove are insulated gate dielectric 13, and the groove is filled with the second conductive material 10; the MIS groove gate structure extends downwards from the surface into the upper GaN channel layer 6 along the vertical direction, the insulated gate dielectric 13 is in contact with the upper GaN channel layer 6, the second barrier layer 7 and the passivation layer 8, and the upper surface of the second conductive material 10 is led out of the gate electrode. Compared with embodiment 1, the MIS recess gate structure has the advantages that the MIS recess gate structure has stronger depletion effect on the 2DEG in the lower-layer channel, the threshold voltage and the gate voltage swing of the device are improved, and meanwhile, the gate leakage current is reduced.
Example 4
The difference between the dual channel enhancement type GaN HEMT device with the P-type buried layer described in this example and the embodiment 1 is that, in the lateral direction of the device, the second conductive material 10 extends to the right along the surface to form a gate field plate structure; the third conductive material 11 extends to the left along the surface of the device, forming a drain field plate, and a space exists between the second conductive material 10 and the third conductive material 11. Compared with embodiment 1, the advantage of this embodiment is that the gate field plate and the drain field plate structure can effectively reduce the electric field peak at the edges of the gate and the drain, and avoid the device from breakdown in advance near the gate or the drain, thereby improving the breakdown voltage of the device.
Example 5
The difference between the dual channel enhancement type GaN HEMT device with the P-type buried layer and the embodiment 3 and the difference between the embodiment 4 and the embodiment 1 in this embodiment are identical, and are not repeated here.

Claims (6)

1. A double-channel enhanced GaN HEMT device with a P-type buried layer comprises a substrate layer (1), a GaN buffer layer (2), a lower GaN channel layer (4), a first barrier layer (5), an upper GaN channel layer (6), a second barrier layer (7) and a passivation layer (8) which are sequentially stacked from bottom to top along the vertical direction of the device; a first conductive material (9), a grid structure and a third conductive material (11) are sequentially arranged on the surface of the device from left to right along the transverse direction; the leading-out end of the first conductive material (9) is a source electrode; the grid structure is separated from the first conductive material (9) and the third conductive material (11); the third conductive material (11) extends downwards into the lower GaN channel layer (4) from the surface of the device along the vertical direction, and the leading-out end of the third conductive material is a drain electrode;
the device is characterized in that heterojunction is formed between the second barrier layer (7) and the upper GaN channel layer (6) and between the first barrier layer (5) and the lower GaN channel layer (4), and a two-dimensional electron gas is generated at the heterojunction interface; a P-type GaN buried layer (3) is arranged on one side, close to the first conductive material (9), of the top of the GaN buffer layer (2), the first conductive material (9) downwards extends to the upper surface of the P-type GaN buried layer (3) along the vertical direction from the surface of the device, the top of the P-type GaN buried layer (3) is in contact with the bottom of the first conductive material (9) along the vertical direction of the device, and the P-type GaN buried layer (3) rightwards extends along the horizontal direction and spans the right side of the gate along the transverse direction of the device.
2. The dual channel enhancement mode GaN HEMT device with a P-type buried layer of claim 1, wherein the top of the P-type GaN buried layer (3) is in contact with the bottom of the underlying GaN channel layer (4).
3. The dual-channel enhanced GaN HEMT device with the P-type buried layer according to claim 1, wherein a space exists between the P-type GaN buried layer (3) and the underlying GaN channel layer (4), and the size of the space satisfies the enhancement mode of the device.
4. The dual channel enhancement mode GaN HEMT device with P-type buried layer of claim 1, wherein said gate structure is comprised of a P-type GaN layer (12) over a second barrier layer (7) and a second conductive material (10) over the P-type GaN layer (12); the contact between the second conductive material (10) and the P-type GaN layer (12) is Schottky contact, and a gate electrode is led out of the upper surface of the second conductive material (10).
5. The dual-channel enhancement mode GaN HEMT device with the P-type buried layer according to claim 1, wherein the gate structure is a MIS groove gate structure, wherein the groove sidewall and bottom are insulated gate dielectric (13), and the groove is filled with a second conductive material (10); the MIS groove gate structure extends downwards from the surface into the upper GaN channel layer (6) along the vertical direction, the insulated gate medium (13) is in contact with the upper GaN channel layer (6), the second barrier layer (7) and the passivation layer (8), and the upper surface of the second conductive material (10) is led out of the gate electrode.
6. The dual-channel enhancement mode GaN HEMT device with a P-type buried layer according to claim 1, wherein the first barrier layer (5) is made of an N-type doped AlN; the second barrier layer (7) is made of one or a combination of a plurality of AlN, alGaN, inGaN, inAlN.
CN202311063697.2A 2023-08-22 2023-08-22 Double-channel enhanced GaN HEMT device with P-type buried layer Pending CN116913951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311063697.2A CN116913951A (en) 2023-08-22 2023-08-22 Double-channel enhanced GaN HEMT device with P-type buried layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311063697.2A CN116913951A (en) 2023-08-22 2023-08-22 Double-channel enhanced GaN HEMT device with P-type buried layer

Publications (1)

Publication Number Publication Date
CN116913951A true CN116913951A (en) 2023-10-20

Family

ID=88358456

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311063697.2A Pending CN116913951A (en) 2023-08-22 2023-08-22 Double-channel enhanced GaN HEMT device with P-type buried layer

Country Status (1)

Country Link
CN (1) CN116913951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117429677A (en) * 2023-12-19 2024-01-23 浙江名瑞智能装备科技股份有限公司 Vacuum packaging device and method for soft battery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117429677A (en) * 2023-12-19 2024-01-23 浙江名瑞智能装备科技股份有限公司 Vacuum packaging device and method for soft battery
CN117429677B (en) * 2023-12-19 2024-03-05 浙江名瑞智能装备科技股份有限公司 Vacuum packaging device and method for soft battery

Similar Documents

Publication Publication Date Title
CN107093628B (en) Polarization doping enhanced HEMT device
CN103022118B (en) Nitride semiconductor device
CN107482059B (en) Vertical reverse conducting field effect transistor of gaN heterojunction
CN106920844B (en) A kind of RESURF HEMT device with N-type floating buried layer
CN109817712A (en) A kind of enhanced HEMT device with more conducting channels and fin grid
CN105097911A (en) HEMT device with junction type semiconductor layer
CN113594248B (en) Double heterojunction GaN HEMT device with integrated freewheel diode
CN105845724A (en) Accumulation vertical HEMT device
CN114447102A (en) Gallium nitride heterojunction field effect transistor with compound semiconductor layer on substrate
CN116913951A (en) Double-channel enhanced GaN HEMT device with P-type buried layer
CN113675270B (en) GaN RC-HEMT with reverse conduction capability
CN113690311B (en) GaN HEMT device integrated with flywheel diode
CN102420247B (en) Group-III nitride HEM (High Electron Mobility Transistor) device
CN107393954B (en) A kind of GaN hetero-junctions vertical field effect pipe
CN102427085A (en) Group III nitride enhancement mode HEMT (High Electron Mobility Transistor) device
CN113611742B (en) GaN power device integrated with Schottky tube
CN111834450B (en) SOI LIGBT device integrated with Zener diode
CN114864687A (en) Gallium nitride power semiconductor device integrated with self-feedback gate control structure
CN113594243A (en) Gradient polarization doped enhanced GaN longitudinal field effect transistor
CN113782588A (en) Gallium nitride power device with high-voltage-resistance low-leakage grid electrode
CN114613856B (en) Double heterojunction GaN RC-HEMT device
CN113611741B (en) GaN HMET device with fin structure
CN214848638U (en) GaN heterojunction longitudinal semiconductor device with shielding gate electrode
CN114068677B (en) Enhancement mode high pressure gaN base vertical HFET device of AlGaN slot
CN113707727B (en) Perpendicular GaN diode with inverted trapezoidal groove

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination