CN113611741B - GaN HMET device with fin structure - Google Patents
GaN HMET device with fin structure Download PDFInfo
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- CN113611741B CN113611741B CN202110879949.3A CN202110879949A CN113611741B CN 113611741 B CN113611741 B CN 113611741B CN 202110879949 A CN202110879949 A CN 202110879949A CN 113611741 B CN113611741 B CN 113611741B
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- FFEARJCKVFRZRR-UHFFFAOYSA-N methionine Chemical compound CSCCC(N)C(O)=O FFEARJCKVFRZRR-UHFFFAOYSA-N 0.000 title claims description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims description 37
- 238000002161 passivation Methods 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000009825 accumulation Methods 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000004047 hole gas Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000010287 polarization Effects 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
The invention belongs to the technical field of power semiconductors, and relates to a GaN HMET (high electron mobility transistor) device with a multi-fin structure. The invention is mainly characterized in that: when the device is conducted, electron accumulation layers are arranged around the fin-shaped GaN layers which are intermittently distributed along the vertical direction of the device, and two-dimensional electron gas (2 DEG) with high concentration and high mobility exists at the heterogeneous interface of the GaN channel layer and the barrier layer along the transverse direction of the device, so that the conducting current of the device is improved, and the conducting resistance is reduced; two-dimensional hole gas (2 DHG) is introduced through a heterostructure formed by the fin-shaped GaN layer and the barrier layer, so that a conductive path in the vertical direction between the source electrode and the two-dimensional electron gas is cut off, and an enhanced GaN HMET device is realized; the device is different from the large transverse distance between the grid sources in the conventional GaN HMET, and the source is positioned at the top of the fin-shaped GaN, so that the area of the device is reduced; the terminal area at one side of the source gate structure can reduce the gate edge electric field peak and introduce new electric field peak, which is beneficial to improving the withstand voltage of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a GaN HMET device with a fin structure.
Background
Compared with the first generation of semiconductor material Si, the third generation of wide band gap semiconductor material GaN has more excellent physical properties of the material, and the physical parameters such as the band gap, the electron mobility, the electron saturation rate, the critical breakdown electric field, the thermal conductivity, the high/low frequency Baliga figure of merit and the like are far higher than those of the Si material. The GaN HEMT (high electron mobility transistor) device has wide application prospect in the application fields of high-current, low-power consumption and high-voltage switching devices.
The conventional GaN HEMT is a depletion mode device because of the strong spontaneous polarization and piezoelectric polarization in the AlGaN/GaN heterojunction, and the high-concentration two-dimensional electron gas (2 DEG) is spontaneously formed at the heterojunction interface. However, in practical circuit applications, a negative voltage power supply is required for the depletion type device to turn off the device, which increases not only the risk of incorrect turn-on of the circuit, but also the power consumption of the entire circuit and the design difficulty of the driving circuit. Therefore, the enhanced GaN HEMT device is more suitable for a power electronic circuit. Typical ways of implementing enhancements at present include: a recessed gate technology, a P-GaN technology, a Cascode technology, a fluorine ion implantation technology, a thin barrier technology, and the like.
In addition, although the GaN material has the advantage of high critical breakdown electric field, for AlGaN/GaN HEMT devices, the device breaks down in advance due to the existence of electric field spikes at the gate edge, excessive leakage current, and the like, and the withstand voltage of the GaN/GaN HEMT device is far from the theoretical limit of the GaN material. For this reason, various technical means are used to increase the breakdown voltage of the device, mainly including: field plate technology, fluorine ion implantation, termination technology, polarization superjunction technology, compensation doping technology, and the like.
Disclosure of Invention
The invention provides a GaN HMET device with a fin structure based on the application requirement of an HEMT device.
The technical scheme of the invention is as follows:
a GaN HMET device with fin structure comprises a substrate layer 1, a GaN buffer layer 2, a GaN channel layer 3, a barrier layer 4 and a passivation layer 5 which are sequentially stacked from bottom to top along the vertical direction of the device; along the transverse direction of the device, one end of the device is a source gate structure penetrating through the passivation layer 5 along the vertical direction of the device, and the other end of the device is a first conductive material 6 penetrating through the passivation layer 5 along the vertical direction of the device;
the first conductive material 6 is contacted with the upper surface of the barrier layer 4 along the vertical direction of the device, the contact is ohmic contact, and the upper surface is led out of the drain electrode;
the source gate structure is characterized by comprising a plurality of fin-shaped GaN layers 7, a source electrode and an insulated gate structure, wherein the fin-shaped GaN layers 7 are intermittently distributed along the longitudinal direction of the device; the fin-shaped GaN layer 7 is positioned above the barrier layer 4 along the vertical direction of the device and is contacted with the upper surface of the barrier layer 4; the source electrode is made of a second conductive material 8 and is contacted with the upper surface of the fin-shaped GaN layer 7, and the contact is ohmic contact; the insulated gate structure is composed of an insulated gate medium 9 and a third conductive material 10, wherein the insulated gate medium 9 is positioned above the barrier layer 4 along the vertical direction of the device, is contacted with the upper surface of the barrier layer 4, and covers the fin-shaped GaN layer 7 and the side wall of the second conductive material 8; the side wall and the bottom of the third conductive material 10 are in contact with the upper surface of the insulated gate dielectric 9 and are not in contact with the second conductive material 8; a grid electrode is led out of the upper surface of the third conductive material 10;
further, the barrier layer 4 is made of one or a combination of a plurality of AlN, alGaN, inGaN, inAlN.
According to the GaN HMET device with the multi-fin structure, when the device is conducted, the electron accumulation layers are arranged around the fin-shaped GaN layers which are intermittently distributed along the vertical direction of the device, and two-dimensional electron gas (2 DEG) with high concentration and high mobility exists at the heterogeneous interface of the GaN channel layer and the barrier layer along the transverse direction of the device, so that the conducting current of the device is improved, and the conducting resistance is reduced; two-dimensional hole gas (2 DHG) is introduced through a heterostructure formed by the fin-shaped GaN layer and the barrier layer, so that a conductive path in the vertical direction between the source electrode and the two-dimensional electron gas is cut off, and an enhanced GaN HMET device is realized; the device is different from the large transverse distance between the grid sources in the conventional GaN HMET, and the source is positioned at the top of the fin-shaped GaN, so that the area of the device is reduced; the terminal area at one side of the source gate structure can reduce the gate edge electric field peak and introduce new electric field peak, which is beneficial to improving the withstand voltage of the device.
Drawings
FIG. 1 is a schematic three-dimensional structure of example 1;
FIG. 2 is a cross-sectional view of the structure of example 1 taken along line AA';
FIG. 3 is a schematic three-dimensional structure of example 2;
FIG. 4 is a schematic three-dimensional structure of example 3;
FIG. 5 is a schematic three-dimensional structure of example 4;
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples:
example 1
As shown in fig. 1, the HEMT device of the present example includes a substrate layer 1, a GaN buffer layer 2, a GaN channel layer 3, a barrier layer 4, and a passivation layer 5, which are sequentially stacked from bottom to top in a vertical direction of the device; along the transverse direction of the device, one end of the device is a source gate structure penetrating through the passivation layer 5 along the vertical direction of the device, and the other end of the device is a first conductive material 6 penetrating through the passivation layer 5 along the vertical direction of the device;
the first conductive material 6 is contacted with the upper surface of the barrier layer 4 along the vertical direction of the device, the contact is ohmic contact, and the upper surface is led out of the drain electrode;
the source gate structure is characterized by comprising a plurality of fin-shaped GaN layers 7, a source electrode and an insulated gate structure, wherein the fin-shaped GaN layers 7 are intermittently distributed along the longitudinal direction of the device; the fin-shaped GaN layer 7 is positioned above the barrier layer 4 along the vertical direction of the device and is contacted with the upper surface of the barrier layer 4; the source electrode is made of a second conductive material 8 and is contacted with the upper surface of the fin-shaped GaN layer 7, and the contact is ohmic contact; the insulated gate structure is composed of an insulated gate medium 9 and a third conductive material 10, wherein the insulated gate medium 9 is positioned above the barrier layer 4 along the vertical direction of the device, is contacted with the upper surface of the barrier layer 4, and covers the fin-shaped GaN layer 7 and the side wall of the second conductive material 8; the side wall and the bottom of the third conductive material 10 are in contact with the upper surface of the insulated gate dielectric 9 and are not in contact with the second conductive material 8; a grid electrode is led out of the upper surface of the third conductive material 10;
compared with the traditional GaN HMET device, the GaN HMET device has the advantages of large on-state current, high breakdown voltage, smaller device area under the same voltage withstand level and the like.
Example 2
The difference between this example and embodiment 1 is that the third conductive material 10 in this example extends to the first conductive material 6 side along the device lateral direction and covers the passivation layer 5 to form the gate field plate 11, and the gate field plate 11 has a distance from the first conductive material 6; compared with embodiment 1, the advantage of this embodiment is that the gate field plate 11 further optimizes the electric field distribution of the device in withstand voltage, and improves the breakdown voltage of the device.
Example 3
The difference between this example and example 1 is that the passivation layer 5 in this example is embedded with the fluorine ion implantation terminal 12, and the fluorine ion implantation terminal 12 is not in contact with the barrier layer 4 in the vertical direction of the device; having a spacing from the first conductive material 6 in the device lateral direction; compared with embodiment 2, the fluorine ion implantation terminal 12 has the advantages that the withstand voltage of the device can be improved, and no additional parasitic capacitance is introduced, so that the dynamic performance of the device is degraded.
Example 4
The difference between this example and embodiment 1 is that, in this example, the barrier layer 4 between the source gate structure and the first conductive material 6 is recessed in the lateral direction of the device, and is not in contact with the lower surface of the barrier layer 4, and the passivation layer 5 covering the barrier layer 4 also forms a recess, so as to form a recess terminal, and the recess terminal, the first conductive material 6 and the source gate structure have a distance in the lateral direction of the device; compared with embodiment 3, the advantage of this embodiment is that the implementation process of the groove termination 13 is simple, the cost is low and no high temperature process exists.
Claims (5)
1. A GaN HMET device with a fin structure comprises a substrate layer (1), a GaN buffer layer (2), a GaN channel layer (3), a barrier layer (4) and a passivation layer (5) which are sequentially stacked from bottom to top along the vertical direction of the device; along the transverse direction of the device, one end of the device is a source gate structure penetrating through the passivation layer (5) along the vertical direction of the device, and the other end of the device is a first conductive material (6) penetrating through the passivation layer (5) along the vertical direction of the device;
the first conductive material (6) is contacted with the upper surface of the barrier layer (4) along the vertical direction of the device, the contact is ohmic contact, and the upper surface is led out of the drain electrode;
the source gate structure is characterized by comprising a plurality of fin-shaped GaN layers (7), a source electrode and an insulated gate structure, wherein the fin-shaped GaN layers are intermittently distributed along the longitudinal direction of the device; the fin-shaped GaN layer (7) is positioned above the barrier layer (4) along the vertical direction of the device and is in contact with the upper surface of the barrier layer (4); the source electrode is made of a second conductive material (8) and is contacted with the upper surface of the fin-shaped GaN layer (7), and the contact is ohmic contact; the insulated gate structure is composed of an insulated gate medium (9) and a third conductive material (10), wherein the insulated gate medium (9) is positioned above the barrier layer (4) along the vertical direction of the device, is contacted with the upper surface of the barrier layer (4), and covers the fin-shaped GaN layer (7) and the side wall of the second conductive material (8); the side wall and the bottom of the third conductive material (10) are in contact with the upper surface of the insulated gate dielectric (9) and are not in contact with the second conductive material (8); a grid electrode is led out of the upper surface of the third conductive material (10);
the longitudinal direction of the device is a third dimension direction which is perpendicular to both the transverse direction of the device and the vertical direction of the device.
2. A GaN HMET device with fin structure according to claim 1, characterized in that the third conductive material (10) extends in the lateral direction of the device to the side of the first conductive material (6) and covers the passivation layer (5), forming a gate field plate (11), and the gate field plate (11) is spaced from the first conductive material (6).
3. A GaN HMET device with fin structure according to claim 1, characterized in that the passivation layer (5) is embedded with a fluorine ion implantation terminal (12), and the fluorine ion implantation terminal (12) is not in contact with the barrier layer (4) along the vertical direction of the device; and a space is provided between the first conductive material (6) and the first conductive material along the transverse direction of the device.
4. A GaN HMET device with fin structure according to claim 1, characterized in that the barrier layer (4) between the source gate structure and the first conductive material (6) is recessed in the lateral direction of the device and is not in contact with the lower surface of the barrier layer (4), and the passivation layer (5) covering the barrier layer (4) also forms a recess, constituting a recess termination, which is spaced apart from the first conductive material (6) and the source gate structure in the lateral direction of the device.
5. A GaN HMET device with fin structure according to any of claims 1-4, characterized in that the barrier layer (4) is made of one or a combination of several of AlN, alGaN, inGaN, inAlN.
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| CN202110879949.3A CN113611741B (en) | 2021-08-02 | 2021-08-02 | GaN HMET device with fin structure |
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| CN202110879949.3A CN113611741B (en) | 2021-08-02 | 2021-08-02 | GaN HMET device with fin structure |
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| CN113611741B true CN113611741B (en) | 2023-04-28 |
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| JP2006253559A (en) * | 2005-03-14 | 2006-09-21 | Nichia Chem Ind Ltd | Field-effect transistor and its manufacturing method |
| CN102403347A (en) * | 2010-09-14 | 2012-04-04 | 三星Led株式会社 | Gallium nitride based semiconductor devices and methods of manufacturing the same |
| CN103681836A (en) * | 2012-09-21 | 2014-03-26 | 罗伯特·博世有限公司 | Vertical microelectronic component and corresponding production method |
| CN105810728A (en) * | 2016-05-06 | 2016-07-27 | 西安电子科技大学 | Enhanced fin-type insulated gate high-electronic mobility transistor |
| CN106611781A (en) * | 2015-10-27 | 2017-05-03 | 上海新昇半导体科技有限公司 | Quantum well device and forming method therefor |
| WO2019139624A1 (en) * | 2018-01-12 | 2019-07-18 | Intel Corporation | Vertical field effect transistors having extended drain regions and methods of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9099388B2 (en) * | 2011-10-21 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | III-V multi-channel FinFETs |
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- 2021-08-02 CN CN202110879949.3A patent/CN113611741B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253559A (en) * | 2005-03-14 | 2006-09-21 | Nichia Chem Ind Ltd | Field-effect transistor and its manufacturing method |
| CN102403347A (en) * | 2010-09-14 | 2012-04-04 | 三星Led株式会社 | Gallium nitride based semiconductor devices and methods of manufacturing the same |
| CN103681836A (en) * | 2012-09-21 | 2014-03-26 | 罗伯特·博世有限公司 | Vertical microelectronic component and corresponding production method |
| CN106611781A (en) * | 2015-10-27 | 2017-05-03 | 上海新昇半导体科技有限公司 | Quantum well device and forming method therefor |
| CN105810728A (en) * | 2016-05-06 | 2016-07-27 | 西安电子科技大学 | Enhanced fin-type insulated gate high-electronic mobility transistor |
| WO2019139624A1 (en) * | 2018-01-12 | 2019-07-18 | Intel Corporation | Vertical field effect transistors having extended drain regions and methods of manufacturing the same |
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