CN116895691A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN116895691A CN116895691A CN202310641261.0A CN202310641261A CN116895691A CN 116895691 A CN116895691 A CN 116895691A CN 202310641261 A CN202310641261 A CN 202310641261A CN 116895691 A CN116895691 A CN 116895691A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000000149 penetrating effect Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 159
- 239000002184 metal Substances 0.000 claims description 33
- 239000011229 interlayer Substances 0.000 claims description 26
- 238000005192 partition Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, comprising the following steps: a substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type provided between the first main surface and the second main surface; a well region layer of the second conductivity type provided on the first main surface side with respect to the drift layer; an emitter layer of a first conductivity type selectively provided on a first main surface side of the well region layer; the substrate is provided with a gate trench penetrating the well region layer and the emitter layer from the first main surface to reach the drift layer; a gate electrode and a shield electrode are arranged in the gate trench through a gate insulating film, the shield electrode being located on the second main surface side of the gate electrode; the thickness of the portion of the gate insulating film between the shielding electrode and the gate electrode is unchanged. The semiconductor device according to the embodiment of the invention not only can form a double-gate structure to reduce switching loss, but also can effectively inhibit leakage current between the shielding electrode and the gate electrode.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
In the semiconductor device of the related art, the gate electrode is formed as a double-gate structure on the basis of a single gate electrode, as shown in fig. 11, the gate electrode 2 and the gate electrode 3 are formed, the gate electrode 2 and the gate electrode 3 are insulated and isolated by an insulating film, the gate electrode 3 is connected with a gate metal to form an effective gate electrode, the gate electrode 2 is connected with an emitter metal to form a dummy gate electrode, cgc is formed between the drift layer and the gate electrode 3, and Cgc cannot be formed between the gate electrode 2 and the drift layer when the gate electrode 2 is connected with the emitter metal, and thus Cgc can be reduced.
However, since the gate electrode 2 is broken during etching of the insulating film 2 due to the processing in the related art, as shown in fig. 10, the thickness of the portion of the insulating film 4 between the gate electrode 2 and the gate electrode 3 is not uniform after the processing, the thickness of the portion of the insulating film 4 between the gate electrode 2 and the gate electrode 3, and the gate electrode 2 and the gate electrode 3 are liable to suffer from electric leakage.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to propose a semiconductor device which can not only form a double gate structure to reduce switching loss, but also effectively suppress leakage current between a shield electrode and a gate electrode.
The invention also provides a manufacturing method of the semiconductor device.
In order to achieve the above object, an embodiment according to a first aspect of the present invention provides a semiconductor device including: a base body having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type provided between the first main surface and the second main surface; a well region layer of a second conductivity type provided on the first main surface side with respect to the drift layer; an emitter layer of a first conductivity type selectively provided on the first main surface side of the well region layer; the substrate is provided with a gate trench penetrating the well region layer and the emitter layer from the first main surface to reach the drift layer; a gate electrode and a shield electrode are disposed in the gate trench with a gate insulating film interposed therebetween, the shield electrode being located on the second main surface side with respect to the gate electrode; the gate insulating film has a constant thickness at a portion between the shielding electrode and the gate electrode.
The semiconductor device according to the embodiment of the invention not only can form a double-gate structure to reduce switching loss, but also can effectively inhibit leakage current between the shielding electrode and the gate electrode.
According to some embodiments of the invention, the upper and lower surfaces of the partition are planar.
According to some embodiments of the invention, the gate electrode is closer to the second main face than the well region layer.
According to some embodiments of the invention, a lower end of the shield electrode is closer to the second main face than an upper surface of the drift layer.
According to some embodiments of the invention, the substrate is provided with a carrier storage layer having a higher impurity concentration of the first conductivity type than the drift layer between the drift layer and the well region layer.
According to some embodiments of the invention, the semiconductor device further comprises: an interlayer insulating film provided on the first main surface; an emitter metal layer provided on the front surface of the interlayer insulating film and electrically connected to the emitter layer, the well region layer, and the shield electrode through the interlayer insulating film, respectively; and a gate metal layer provided on the front surface of the interlayer insulating film and electrically connected to the gate electrode through the interlayer insulating film.
According to some embodiments of the invention, the semiconductor device further comprises: a field stop layer of a first conductivity type provided on the second main surface side of the drift layer and having an impurity concentration higher than that of the drift layer; a collector layer of a second conductivity type provided on the second main surface side with respect to the field stop layer; and a collector metal provided on the second main surface and electrically connected to the collector layer.
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including: providing a substrate having a drift layer of a first conductivity type, a well region layer of a second conductivity type, and an emitter layer of the first conductivity type; forming a gate trench on the substrate, the gate trench penetrating the well region layer and the emitter layer from the first main surface to reach the drift layer; growing an oxide layer on the inner wall of the grid groove to form a first insulating film; depositing a polycrystalline material on the first insulating film, and etching the polycrystalline material to form a shielding electrode; growing an oxide layer on the shielding electrode to form a second insulating film; removing a portion of the first insulating film beyond the front surface of the shielding electrode and the second insulating film; growing an oxide layer on the shielding electrode and the inner wall of the gate trench to form a third insulating film, wherein the first insulating film and the third insulating film jointly form a gate insulating film; depositing a polycrystalline material on the third insulating film to form a gate electrode; the gate insulating film has a constant thickness at a portion between the shielding electrode and the gate electrode.
The semiconductor device manufactured by the manufacturing method of the semiconductor device can not only form a double-gate structure to reduce switching loss, but also effectively inhibit leakage current between the shielding electrode and the gate electrode.
According to some embodiments of the invention, the upper and lower surfaces of the partition are prepared as planar surfaces.
According to some embodiments of the invention, the thickness of the second insulating film is not less than the thickness of the first insulating film.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 8 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 9 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 10 is a sectional view showing a state of a process of manufacturing a semiconductor device according to the related art.
Fig. 11 is a sectional view showing a state of a process of manufacturing a semiconductor device according to the related art.
Reference numerals:
a semiconductor device 1,
A substrate 100, a first main surface 101, a second main surface 102,
Drift layer 200, well layer 300, emitter layer 400,
A gate trench 500, a gate electrode 510, a shield electrode 520, a gate insulating film 530, a partition 531, a first insulating film 532, a second insulating film 533, a third insulating film 534,
A carrier storage layer 600,
Interlayer insulating film 700, emitter metal layer 710,
A field stop layer 800, a collector layer 810, and a collector metal 820.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present invention, "plurality" means two or more.
A semiconductor device 1 according to an embodiment of the present invention is described below with reference to the drawings. The semiconductor device 1 is, for example, an IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor). In the following description, n and p denote the conductivity type of the semiconductor, and in the present invention, the 1 st conductivity type is referred to as n-type and the 2 nd conductivity type is referred to as p-type. The conductivity type can be reversed.
As shown in fig. 1 to 9, a semiconductor device 1 according to an embodiment of the present invention includes a body 100, a drift layer 200 of a first conductivity type, a well region layer 300 of a second conductivity type, and an emitter layer 400 of the first conductivity type.
The body 100 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, the drift layer 200 is provided between the first main surface 101 and the second main surface 102, the well layer 300 is provided on the first main surface 101 side compared to the drift layer 200, and the emitter layer 400 is selectively provided on the first main surface 101 side of the well layer 300. The body 100 is provided with a gate trench 500 penetrating the well layer 300 and the emitter layer 400 from the first main surface 101 to the drift layer 200, a gate electrode 510 and a shield electrode 520 are arranged in the gate trench 500 with a gate insulating film 530 interposed therebetween, and the shield electrode 520 is located on the second main surface 102 side with respect to the gate electrode 510, wherein the gate insulating film 530 has a constant thickness at a portion located between the shield electrode 520 and the gate electrode 510, for example, the gate insulating film 530 has a partition 531, the partition 531 is located between the shield electrode 520 and the gate electrode 510, and the partition 531 has a constant thickness.
According to the semiconductor device 1 of the embodiment of the present invention, the gate trench 500 penetrating the well layer 300 and the emitter layer 400 from the first main surface 101 to reach the drift layer 200 is provided in the body 100, and the gate electrode 510 and the shield electrode 520 are disposed in the gate trench 500 through the gate insulating film 530, whereby the shield electrode 520 is located on the second main surface 102 side of the gate electrode 510.
In this way, since the semiconductor device 1 has a double-gate structure, i.e., the gate electrode 510 and the shield electrode 520, the gate electrode 510 is an effective gate, and the shield electrode 520 is a dummy gate, cgc is present between the gate electrode 510 and the drift layer 200, cgc is not present between the shield electrode 520 and the drift layer 200, and Cgc is reduced, whereby switching loss and on-voltage of the semiconductor device 1 can be reduced.
In addition, since the gate insulating film 530 has the partition 531, the partition 531 is located between the shield electrode 520 and the gate electrode 510, and the thickness of the partition 531 is the same, the conductivity between the shield electrode 520 and the gate electrode 510 is uniform, and the occurrence of the uneven thickness of the partition 531 can be avoided, so that the leakage current between the shield electrode 520 and the gate electrode 510 can be effectively suppressed, and the safety of the semiconductor device 1 can be improved.
As such, the semiconductor device 1 according to the embodiment of the present invention can not only form a double gate structure to reduce switching loss, but also can effectively suppress leakage current between the shielding electrode 520 and the gate electrode 510.
According to some embodiments of the present invention, as shown in fig. 7-9, the upper and lower surfaces of the partition 531 are planar. In this way, the relative area between the gate electrode 510 and the shielding electrode 520 is not increased, which is beneficial to ensuring that the electrical properties of each area between the gate electrode 510 and the shielding electrode 520 are the same, avoiding the occurrence of a sharp corner structure, and effectively inhibiting the leakage between the gate electrode 510 and the shielding electrode 520.
According to some embodiments of the present invention, as shown in fig. 8-9, the gate electrode 510 is closer to the second major face 102 than the well region layer 300. In this way, it is possible to ensure that the relative area between the gate electrode 510 and the drift layer 200 is large enough to ensure the electrical performance of the semiconductor device 1.
According to some embodiments of the present invention, as shown in fig. 1-9, the semiconductor device 1 further includes a field stop layer 800 (Inter Layer Dielectric, ILD) of a first conductivity type, a collector layer 810 of a second conductivity type, and a collector metal 820.
The field stop layer 800 is provided on the second main surface 102 side with respect to the drift layer 200, the impurity concentration of the field stop layer 800 is higher than that of the drift layer 200, the collector layer 810 is provided on the second main surface 102 side with respect to the field stop layer 800, and the collector metal 820 is provided on the second main surface 102 and electrically connected to the collector layer 810.
By providing the collector layer 810 and the collector metal 820, the semiconductor device 1 can be protected from direct exposure of the second main surface 102 of the substrate 100 to air, and the circuit safety can be improved. And, the collector metal 820 is used as a collector terminal of the semiconductor device 1 to ensure the reliability of electrical connection of the semiconductor device 1, facilitating the use of the semiconductor device 1.
According to some embodiments of the present invention, as shown in fig. 1 to 9, the body 100 is provided with a carrier storage layer 600 having a higher impurity concentration of the first conductivity type than the drift layer 200 between the drift layer 200 and the well region layer 300. By providing the carrier storage layer 600 (carrier stored layer, CS layer), holes supplied from the collector layer 810 at the time of energization are accumulated in the carrier storage layer 600. This reduces conductivity, reduces on-resistance, and reduces switching loss.
According to some embodiments of the present invention, as shown in fig. 1-9, the lower end of the shielding electrode 520 is closer to the second main surface 102 than the upper surface of the drift layer 200, and the upper surface of the drift layer 200 is closer to the second main surface 102 than the upper end of the shielding electrode 520. Thus, the shielding electrode 520 has a sufficient depth, and can effectively reduce Cgc and switching loss.
According to some embodiments of the present invention, as shown in fig. 9, the semiconductor device 1 further includes an interlayer insulating film 700, an emitter metal layer 710, and a gate metal layer (not shown).
The interlayer insulating film 700 is provided on the first main surface 101, the emitter metal layer 710 is provided on the front surface of the interlayer insulating film 700 and is electrically connected to the emitter layer 400, the well region layer 300, and the shield electrode 520 through the interlayer insulating film 700, and the gate metal layer is provided on the front surface of the interlayer insulating film 700 and is electrically connected to the gate electrode 510 through the interlayer insulating film 700.
The emitter metal layer 710 and the gate metal layer are disposed at intervals, so that a short circuit between the emitter metal layer 710 and the gate metal layer is avoided. Also, the interlayer insulating film 700 may be an oxide.
The provision of the interlayer insulating film 700 can protect the semiconductor device 1 from direct exposure to air on the first main surface 101 of the substrate 100, thereby improving circuit safety. And, the emitter metal layer 710 and the gate metal layer serve as an emitter terminal and a gate terminal of the semiconductor device 1 to ensure the reliability of electrical connection of the semiconductor device, facilitating the use of the semiconductor device 1.
A method of manufacturing a semiconductor device according to an embodiment of the present invention is described below with reference to the accompanying drawings, the method including:
as shown in fig. 1, there is provided a substrate 100 including a drift layer 200 of a first conductivity type, a well region layer 300 of a second conductivity type, and an emitter layer 400 of the first conductivity type, wherein a carrier storage layer 600 of the first conductivity type is provided between the drift layer 200 and the well region layer 300, the carrier storage layer 600 has an impurity concentration higher than that of the drift layer 200, the substrate 100 is further provided with a field stop layer 800 of the first conductivity type and a collector layer 810 of the second conductivity type, the field stop layer 800 is provided on the second main surface 102 side than the drift layer 200, the impurity concentration of the field stop layer 800 is higher than that of the drift layer 200, and the collector layer 810 is provided on the second main surface 102 side than the field stop layer 800;
as shown in fig. 2, a gate trench 500 is formed in the body 100, penetrating the well layer 300 and the emitter layer 400 from the first main surface 101, and reaching the drift layer 200;
as shown in fig. 3, an oxide layer is grown on the inner wall of the gate trench 500 to form a first insulating film 532, wherein the first insulating film 532 may be formed by thermal oxidation or deposition;
as shown in fig. 4, a polycrystalline material is deposited on the first insulating film 532 and etched to form a shielding electrode 520;
as shown in fig. 5, an oxide layer is grown on the shielding electrode 520 to form a second insulating film 533, wherein the first insulating film 532 may be formed by thermal oxidation or deposition;
as shown in fig. 6, the portion of the first insulating film 532 that exceeds the front surface of the shielding electrode 520 and the second insulating film 533 are removed, for example, the portion of the first insulating film 532 that exceeds the front surface of the shielding electrode 520 and the second insulating film 533 may be removed by etching;
as shown in fig. 7, an oxide layer is grown on the shielding electrode 520 and the inner wall of the gate trench 500 to form a third insulating film 534, and the first insulating film 532 and the third insulating film 534 together form a gate insulating film 530, wherein the first insulating film 532 may be formed by thermal oxidation or deposition;
as shown in fig. 8, a polycrystalline material is deposited on the third insulating film 534 to form the gate electrode 510, wherein the gate insulating film 530 has a partition 531, the partition 531 is located between the shielding electrode 520 and the gate electrode 510, and the thickness of the partition 531 is the same.
As shown in fig. 9, an interlayer insulating film 700, an emitter metal layer 710, and a gate metal layer (not shown) are provided on the first main surface 101 side of the base body 100, the interlayer insulating film 700 is provided on the first main surface 101, the emitter metal layer 710 is provided on the front surface of the interlayer insulating film 700 and electrically connected to the emitter layer 400, the well region layer 300, and the shield electrode 520 through the interlayer insulating film 700, respectively, and the gate metal layer is provided on the front surface of the interlayer insulating film 700 and electrically connected to the gate electrode 510 through the interlayer insulating film 700. Wherein the emitter metal layer 710 and the gate metal layer are disposed at intervals.
As shown in fig. 9, a collector metal 820 is provided on the second main surface 102 side of the base 100, and the collector metal 820 is electrically connected to the collector layer 810.
In the method for manufacturing a semiconductor device in the prior art, after the step shown in fig. 4 (i.e., depositing a polycrystalline material on the first insulating film 1 and etching the polycrystalline material to form the shielding electrode 2), the first insulating film 1 on the inner wall of the gate trench is directly etched, so that the structure shown in fig. 10 is formed, the top of the shielding electrode 2 protrudes, and when the third insulating film 4 and the gate electrode 3 are manufactured based on the structure shown in fig. 10, the structure shown in fig. 11 is formed, the third insulating film 4 on the top of the shielding electrode 2 protrudes the same as the top of the shielding electrode 2, the thickness of the protruding portion of the third insulating film 4 is inconsistent, and an acute corner is formed, and the relative area between the shielding electrode 2 and the gate electrode 3 is increased, so that the leakage current between the shielding electrode 2 and the gate electrode 3 is increased.
Compared with the method for manufacturing a semiconductor device in the prior art, the method for manufacturing a semiconductor device according to the embodiment of the invention can effectively suppress the leakage current between the shielding electrode 520 and the gate electrode 510 by adding step 9 shown in fig. 5 and 6, i.e., growing an oxide layer on the shielding electrode 520 to form the second insulating film 533, and removing the portion of the first insulating film 532 beyond the front surface of the shielding electrode 520 and the second insulating film 533, so that the thickness of the oxide layer between the shielding electrode 520 and the gate electrode 510 is uniform and no sharp corner is formed.
The semiconductor device 1 manufactured by the manufacturing method of the semiconductor device according to the embodiment of the invention can not only form a double gate structure to reduce switching loss, but also can effectively suppress leakage current between the shielding electrode 520 and the gate electrode 510.
According to some embodiments of the present invention, as shown in fig. 7 to 9, the upper and lower surfaces of the partition 531 are prepared as planes. In this way, the relative area between the gate electrode 510 and the shielding electrode 520 is not increased, which is beneficial to ensuring that the electrical properties of each area between the gate electrode 510 and the shielding electrode 520 are the same, avoiding the occurrence of a sharp corner structure, and effectively inhibiting the leakage between the gate electrode 510 and the shielding electrode 520.
According to some embodiments of the present invention, as shown in fig. 5, the thickness of the second insulating film 533 is not smaller than the thickness of the first insulating film 532. In this way, the thickness of the second insulating film 533 is sufficient, and damage to the shielding electrode 520 can be avoided and electrical performance can be ensured in the process of removing the portion of the first insulating film 532 beyond the front surface of the shielding electrode 520 and the second insulating film 533.
Other constructions and operations of the semiconductor device 1 according to the embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A semiconductor device, comprising:
a substrate having a first main surface and a second main surface opposite to the first main surface;
a drift layer of a first conductivity type provided between the first main surface and the second main surface;
a well region layer of a second conductivity type provided on the first main surface side with respect to the drift layer;
an emitter layer of a first conductivity type selectively provided on the first main surface side of the well region layer;
the substrate is provided with a gate trench penetrating the well region layer and the emitter layer from the first main surface to reach the drift layer;
a gate electrode and a shield electrode are disposed in the gate trench with a gate insulating film interposed therebetween, the shield electrode being located on the second main surface side with respect to the gate electrode;
the gate insulating film has a constant thickness at a portion between the shielding electrode and the gate electrode.
2. The semiconductor device according to claim 1, wherein an upper surface and a lower surface of the partition portion are planar.
3. The semiconductor device according to claim 1, wherein the gate electrode is closer to the second main surface than the well region layer.
4. The semiconductor device according to claim 1, wherein a lower end of the shield electrode is closer to the second main surface than an upper surface of the drift layer.
5. The semiconductor device according to claim 1, wherein the base body is provided with a carrier storage layer having an impurity concentration of the first conductivity type higher than that of the drift layer, between the drift layer and the well region layer.
6. The semiconductor device according to any one of claims 1 to 5, further comprising:
an interlayer insulating film provided on the first main surface;
an emitter metal layer provided on the front surface of the interlayer insulating film and electrically connected to the emitter layer, the well region layer, and the shield electrode through the interlayer insulating film, respectively;
and a gate metal layer provided on the front surface of the interlayer insulating film and electrically connected to the gate electrode through the interlayer insulating film.
7. The semiconductor device according to claim 6, further comprising:
a field stop layer of a first conductivity type provided on the second main surface side of the drift layer and having an impurity concentration higher than that of the drift layer;
a collector layer of a second conductivity type provided on the second main surface side with respect to the field stop layer;
and a collector metal provided on the second main surface and electrically connected to the collector layer.
8. A method of manufacturing a semiconductor device, comprising:
providing a substrate having a drift layer of a first conductivity type, a well region layer of a second conductivity type, and an emitter layer of the first conductivity type;
forming a gate trench on the substrate, the gate trench penetrating the well region layer and the emitter layer from the first main surface to reach the drift layer;
growing an oxide layer on the inner wall of the grid groove to form a first insulating film;
depositing a polycrystalline material on the first insulating film, and etching the polycrystalline material to form a shielding electrode;
growing an oxide layer on the shielding electrode to form a second insulating film;
removing a portion of the first insulating film beyond the front surface of the shielding electrode and the second insulating film;
growing an oxide layer on the shielding electrode and the inner wall of the gate trench to form a third insulating film, wherein the first insulating film and the third insulating film jointly form a gate insulating film;
depositing a polycrystalline material on the third insulating film to form a gate electrode;
the gate insulating film has a constant thickness at a portion between the shielding electrode and the gate electrode.
9. The method for manufacturing a semiconductor device according to claim 8, wherein an upper surface and a lower surface of the partition portion are prepared as planes.
10. The method according to claim 8, wherein a thickness of the second insulating film is not smaller than a thickness of the first insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310641261.0A CN116895691A (en) | 2023-05-31 | 2023-05-31 | Semiconductor device and method for manufacturing the same |
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| CN202310641261.0A CN116895691A (en) | 2023-05-31 | 2023-05-31 | Semiconductor device and method for manufacturing the same |
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| CN116895691A true CN116895691A (en) | 2023-10-17 |
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| CN202310641261.0A Pending CN116895691A (en) | 2023-05-31 | 2023-05-31 | Semiconductor device and method for manufacturing the same |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244374A (en) * | 2015-08-31 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of groove gate MOSFET possessing shielding gate |
| US20180315846A1 (en) * | 2017-04-26 | 2018-11-01 | Alpha And Omega Semiconductor (Cayman) Ltd. | Scalable sgt structure with improved fom |
| CN111244176A (en) * | 2019-12-30 | 2020-06-05 | 江苏长晶科技有限公司 | Shielding gate trench MOSFET (metal-oxide-semiconductor field effect transistor), preparation method thereof and electronic equipment |
| CN111446157A (en) * | 2020-04-07 | 2020-07-24 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor and method of forming the same |
| CN113767478A (en) * | 2019-04-23 | 2021-12-07 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
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2023
- 2023-05-31 CN CN202310641261.0A patent/CN116895691A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244374A (en) * | 2015-08-31 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of groove gate MOSFET possessing shielding gate |
| US20180315846A1 (en) * | 2017-04-26 | 2018-11-01 | Alpha And Omega Semiconductor (Cayman) Ltd. | Scalable sgt structure with improved fom |
| CN113767478A (en) * | 2019-04-23 | 2021-12-07 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
| CN111244176A (en) * | 2019-12-30 | 2020-06-05 | 江苏长晶科技有限公司 | Shielding gate trench MOSFET (metal-oxide-semiconductor field effect transistor), preparation method thereof and electronic equipment |
| CN111446157A (en) * | 2020-04-07 | 2020-07-24 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor and method of forming the same |
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