CN116884944A - Semiconductor packaging structure and packaging method - Google Patents

Abstract

The application discloses a semiconductor packaging structure and a packaging method, which relate to the field of chip packaging, and are characterized in that: the functional modules are positioned on one side of the rerouting structure, the functional modules are electrically coupled with the rerouting structure, the network units are positioned on the other side of the rerouting structure, and the network units are electrically coupled with the rerouting structure; the function module comprises a calculation module and an external power supply module for supplying power to the calculation module and the network unit; the network unit is internally provided with an on-chip network interconnection channel for realizing non-power signal routing and on-chip communication interconnection, and the functional modules are interconnected through the on-chip network interconnection channel and a rewiring structure of the network unit; a data interconnection structure and a power supply interconnection structure are arranged in the rewiring structure; the data interconnection structure and the power interconnection structure are isolated from each other. The chip of the system on a chip can be flexibly laid out, the functions of the system on a chip are enriched, and the power supply layout is reasonable.

Description

Semiconductor packaging structure and packaging method

Technical Field

The present application relates to the field of chip packaging, and in particular, to a semiconductor packaging structure and a packaging method.

Background

After the integrated circuit industry enters the late moore's law era, advanced integrated packaging technology is gradually becoming the wave tip of trend. The More than Moore uses advanced encapsulation to optimize the system at the system architecture level. The die-to-die interconnect technology is used to package multiple module chips with the underlying base chip to form a SiP chip model, such as EMIB and CoWoS technologies.

The prior system structure on a crystal mainly comprises the following schemes: firstly, a whole wafer taking a computing chip as a main body is used as a system, and the computing chips are interconnected through an on-chip interconnection interface to form a system on a chip (taking a U.S. patent with a patent publication number of US10923456B2 as an example); secondly, taking passive silicon as a wafer substrate, forming an interconnection system on a chip by flip chip bonding/hybrid bonding and other modes (taking paper with DOI number of 10.1109/hpca.2019.00042 as an example); thirdly, the InFO-SoW advanced packaging technology is used for reconstructing the computing chips into a wafer, interconnection among the chips is completed through reconstruction wiring, and a power module is connected with the computing chips on the reconstruction wafer in a flip-chip manner to form the whole system on a chip (DOI No. 10.1109/ecto32862.2020.00013).

In the scheme that the whole wafer is a system on a chip, the yield of a single chip is a key factor of manufacturing cost, and as the size of the single chip becomes larger, the yield of the single chip is inevitably reduced. As in the first solution, although the damaged chip may be bypassed by redundancy or the like, the cost becomes high, and different configurations of the on-chip system may be required. The second passive silicon wafer substrate solution described above can select KGD (know good die) the calculated core particles through testing, but has the problem of single chip type and single system function; in addition, in order to solve the problems of power supply, heat dissipation and the like of the whole wafer, a large amount of wafer area is wasted to configure VRM (Voltage Regulator Module) area to be 1/2 of that of a single system, and the utilization rate of the system is reduced. The third fan-out approach of InFO-SoW combines KGD chips into a wafer substrate, and flip-chip the power chip on the wafer substrate to achieve the power integrity requirement; however, there is a problem that the system on a chip is relatively single in use.

When the above schemes are analyzed, the problems causing the defects are found to be mainly two points: 1. computing chips are the main component of the system on a chip, and are in most cases used directly to form a monolithic structure, which results in all chips being reconfigured together to form a wafer-sized system. Under the condition, the reconstructed system chip layout has single fixing function and can not meet the requirements of different systems. 2. Similar to the scheme taking a passive silicon substrate as a support, different functional chips can be integrated and attached so as to achieve different application scenes of the system; there are system power configuration problems in that a large amount of area must be spent to optimize the power supply. Meanwhile, the layout of the rewiring layer is not flexible enough, and the superposition of a power line and a data line is easy to occur, so that the data line is disturbed.

Disclosure of Invention

In view of the above problems, one of the objects of the present application is to provide a semiconductor package structure, which is characterized in that network units are utilized to form a network on chip, so that routing communication between computing modules can be flexibly configured through the network on chip.

In one aspect, the application provides a semiconductor package structure, comprising a reconstituted wafer substrate and a plurality of functional modules, wherein the reconstituted wafer substrate comprises a rewiring structure and a plurality of network units; the plurality of functional modules are positioned on one side of the rewiring structure, the functional modules are electrically coupled with the rewiring structure, the plurality of network units are positioned on the other side of the rewiring structure, and the network units are electrically coupled with the rewiring structure; the function module comprises a calculation module and an external power supply module for supplying power to the calculation module and the network unit; the network unit is internally provided with an on-chip network interconnection channel for realizing non-power signal routing and on-chip communication interconnection, and the functional modules are interconnected through the on-chip network interconnection channel and a rewiring structure of the network unit; a data interconnection structure and a power supply interconnection structure are arranged in the rewiring structure; the data interconnection structure and the power interconnection structure are isolated from each other.

According to the technical scheme, the network units are used as the network-on-chip carriers of the system-on-chip, interconnection among the plurality of network-on-chip units is completed through a rewiring technology, and a computing module interface is provided, so that a plurality of computing modules can realize programmable logic interconnection through the network-on-chip constructed by the network units, and the computing modules and the network units can be flexibly laid out; the modules with different functions such as the calculation module and the like are arranged outside the reconstructed wafer substrate, so that the system on a wafer using the packaging structure can integrate different functional modules, and the functions are more abundant; a plurality of external power supply modules can be arranged on the on-chip system using the packaging structure in a dispersing way, so that the uniform distribution of the power supply network of the on-chip system is ensured; the paths of the power supply signals and the paths of the data signals in the rewiring structure are mutually isolated, so that the data signals are prevented from being interfered.

Optionally, the RDL interconnect metallization pattern of the data interconnect structure and the RDL interconnect metallization pattern of the power interconnect structure are located in different dielectric layers, respectively.

Preferably, the projection of the data interconnect structure in the vertical direction does not overlap with the projection of the power interconnect structure in the vertical direction at all.

Preferably, a region without a circuit is arranged between the projection region of the data interconnection structure in the vertical direction and the projection region of the power interconnection structure in the vertical direction.

Through the technical scheme, the direct distance between the data interconnection structure and the power interconnection structure is further, and the interference of the power signal on the data signal is better avoided.

Preferably, the computing module and the network unit are both provided with a data I/O area and a power I/O area; the data I/O area is electrically coupled with the data interconnection structure, and the power I/O area is electrically coupled with the power interconnection structure; the external power module is electrically coupled to the power interconnect structure.

Through the technical scheme, the data signal transmission and the power transmission are partitioned, and the interference problem between the signal transmission and the power transmission can be avoided.

Preferably, the external power supply module comprises a power supply interface, an external power supply board is inserted on the power supply interface, and the external power supply board comprises a power supply connector connected with the power supply interface and an external power supply management circuit for supplying power to the power supply interface; the external power management circuit includes an external voltage conversion circuit and a supporting circuit.

Preferably, the system can further comprise an on-chip power module for supplying power to surrounding network units and/or functional modules through the rewiring structure; the on-chip power supply module and the network unit are arranged on the same side of the rewiring structure, and the plastic package material encapsulates the on-chip power supply module; the on-chip power supply module is electrically coupled with the rewiring structure and the external power supply module through the rewiring structure, and is also electrically coupled with a plurality of network units and/or functional modules through the rewiring structure.

Preferably, the external power supply module is further provided with a kernel power supply management circuit for supplying power to a plurality of computing modules and/or network units arranged around the external power supply module, the input end of the kernel power supply management circuit is electrically coupled with the power supply interface, and the output end of the kernel power supply management circuit is electrically coupled with the computing modules and/or the network units through a power supply interconnection structure.

By means of the technical scheme, the power supply module is integrated on the reconstituted wafer substrate in a vertical interconnection mode and is supplied with power supply for different functional modules and/or network units in a certain area through the short-distance RDL on the rewiring structure.

Optionally, the computing module comprises a computing device with a computing function and/or a whole formed by plugging the computing device with the computing function with the socket; the functional module further comprises an I/O module for signal interaction with an external device and/or a storage module with a storage function; the I/O module comprises an I/O connector and/or a socket and the I/O connector are spliced to form a whole; the storage module comprises a storage device and/or a socket and the storage device which are spliced to form a whole.

Through the technical scheme, the socket is arranged, so that the functional device can be conveniently and quickly replaced when damaged, and the integral performance of the system on a chip using the packaging structure is prevented from being influenced by the damage of the single device.

Preferably, the external power supply module is further provided with an interface power supply circuit for supplying power to the I/O module, the input end of the interface power supply management circuit is electrically coupled with the power supply interface, and the output end of the interface power supply management circuit is electrically coupled with the I/O module through a power supply interconnection structure.

Through the technical scheme, the I/O module is independently powered, and the interface power supply configuration problem is solved.

In another aspect, the present application also provides a semiconductor packaging method, including the steps of:

preparing a temporary carrier plate, coating a temporary bonding material on the temporary carrier plate, and forming a rerouting structure with a data interconnection structure and a power supply interconnection structure which are isolated from each other on the temporary bonding material through a rerouting process;

mounting the network element patch on a rewiring structure, and encapsulating all network elements or the network elements and the rewiring structure by using a plastic packaging material in a wafer plastic packaging mode to form a reconstructed wafer substrate;

dismantling the temporary carrier plate and cleaning the reconstituted wafer substrate in a de-bonding mode which is suitable for the temporary bonding material to expose the interconnection welding spots on the rewiring structure;

the functional module with the conductive connecting piece is attached to the corresponding interconnection welding point, so that the data I/O area of the computing module and the network unit are electrically coupled with the data interconnection structure, the power I/O area of the computing module and the network unit are electrically coupled with the power interconnection structure, and the external power module is electrically coupled with the power interconnection structure.

Drawings

Fig. 1 is a schematic diagram of a package structure connected with an external power supply board according to embodiment 1;

FIG. 2 is a schematic diagram of a structure with a pillar interconnect structure according to embodiment 1;

fig. 3 is a structural diagram of a power supply system of embodiment 1;

fig. 4 is a structural diagram of a further power supply system of embodiment 1;

fig. 5 is a flowchart of the packaging method of embodiment 2.

Reference numerals: 1. reconstructing a wafer substrate; 11. a rewiring structure; 1111. Pillar interconnect bumps; 12. a network element; 131. A computing module; 1311. a computing device; 132. externally connecting a power module; 133. a storage module; 134. an I/O module; 135. a socket; 14. filling glue at the bottom; 141. a data interconnect structure; 142. a power supply interconnection structure; 16. Plastic packaging material; 17. a conductive connection; 4. An external power supply board; 41. a power supply connector; 42. a power chip; 43. a plate body; 9. a temporary carrier plate; 91. temporary bonding material.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. It should be noted that the words "front", "back", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "bottom" and "top", "inner" and "outer" refer to directions toward or away from, respectively, the geometric center of a particular component. These relative terms are for convenience of description only and do not require that the application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for ease of description, "first," "second," "third," etc. may be used herein to distinguish between different components of a figure or series of figures. The terms "first," "second," "third," and the like are not intended to describe corresponding components.

The application introduces FPGA/ASIC as network-on-chip carrier of system-on-chip, completes interconnection among hundreds of FPGA/ASIC network-on-chip units 12 through fan-out (RDL) technology and provides interfaces of computing modules 131, so that a plurality of computing modules 131 realize programmable logic interconnection among computing modules 131 through network-on-chip constructed by FPGA/ASIC. The above arrangement enables the routing communication between the computing modules 131 to be flexibly configured through the network on chip, and the chip of the system on chip using the package can be flexibly configured to freely match the module interfaces so as to realize different functions, and the functions are richer.

While external power supply will be provided by means of regional vertical interconnects, power modules can be integrated on the reconstituted wafer substrate 1 and supplied to the different module cores by means of short distance RDLs.

The power signal line and the data signal line in the system are separated from each other, so that interference is avoided.

The whole system on a chip realizes interconnection among different chips based on reconfigurable chips such as FPGA/ASIC, has expandability and is not limited to single chip application. And the application of the whole system on a crystal is more feasible through the optimization of a power supply system.

The above is the core idea of the application, and based on the embodiments of the application, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the application. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Example 1

The application provides a semiconductor packaging structure, as shown in fig. 1 and 2, which comprises a rewiring structure 11, a network unit 12 and a plurality of functional modules. The plurality of functional modules are located on one side of the rewiring structure 11 and electrically coupled to the rewiring structure 11, the network element 12 is located on the other side of the rewiring structure 11, and the network element 12 is electrically coupled to the rewiring structure 11.

The rewiring structure 11 comprises a plurality of interconnection structures for interconnecting the network units 12 and 12, the network units 12 and one or more of the functional modules, the functional modules and the functional modules to form an integrated circuit. The interconnect structure may be formed, for example, by creating a plurality of RDL interconnect metal patterns in a plurality of dielectric layers on a semiconductor substrate. The interconnect structure further includes a plurality of under bump metallization (not shown) for external connection to the redistribution structure 11. A plurality of conductive connections 17 may be formed on the under bump metal. The conductive connection 17 may also be formed on the functional side of the network element 12 and/or the functional module.

In some embodiments, as shown in FIG. 2, the interconnect structure may also include pillar interconnect bumps 1111 extending through the re-wiring structure 11, and the pillar interconnect bumps 1111 may be formed in a similar manner and from a similar material as the RDL interconnect metal patterns.

The plurality of functional modules mainly comprise a computing module 131 with a computing function and an external power module 132. Any functional module is mounted to the under bump metal by conductive connection 17 to achieve electrical coupling of the functional module to the rewiring structure 11. To protect the conductive connection 17 and the functional surface of the functional module, an underfill 14 may be filled in the gap between the functional module and the rewiring structure 11.

The computing module 131 may specifically include a computing device 1311 having a computing function, such as an image processing chip, a DSP chip, a neural network (AI) chip, a computing chip, and the like. These computing devices 1311 with computing capabilities may have SRAM or Flash storage integrated therein.

The functional modules may also include an I/O module 134, the I/O module 134 for signal interaction with external devices.

In some embodiments, the functional module may further include a memory module 133, the memory module 133 including, for example, an HMC device, an HBM device, a DDR device, or the like including a plurality of memory chips.

The interconnect structures within the rewiring structure 11 may include a data interconnect structure 141 and a power interconnect structure 142. The data interconnect structure 141 and the power interconnect structure 142 are isolated from each other. The functional modules including the calculation module 131, the storage module 133, and the I/O module 134 and the network unit 12 each have a functional surface, and the functional surfaces are configured with a data I/O area and a power I/O area. The data I/O region is electrically coupled to the data interconnect 141, and the power I/O region is electrically coupled to the power interconnect 142.

By the arrangement, the power supply line and the data line in the rewiring structure 11 can be separated, and the condition that the data signal is interfered is reduced; the data I/O area and the power I/O area are distinguished on the functional surfaces of the functional module and the network unit 12, so that the data signal transmission and the power transmission are partitioned, and the interference problem between the signal transmission and the power transmission can be avoided.

In order to further increase the decoupling degree of the data interconnect structure 141 and the power interconnect structure 142, it is configured that the RDL interconnect metallization pattern of the data interconnect structure 141 and the RDL interconnect metallization pattern of the power interconnect structure 142 are respectively located in different dielectric layers. Alternatively, the projection of the data interconnect structure 141 in the vertical direction does not overlap with the projection of the power interconnect structure 142 in the vertical direction at all. Preferably, as shown in fig. 2, a region without a line is disposed between the projection region of the data interconnect structure 141 in the vertical direction and the projection region of the power interconnect structure 142 in the vertical direction.

The network element 12 comprises an FPGA, ASIC, or the like. Network element 12 has network-on-chip interconnection channels formed therein, and the functional modules can be interconnected by non-power signal routing and on-chip communication through network element 12 and data interconnection structure 141 of rewiring structure 11. The network-on-chip interconnect channels of the network unit 12 are physically fixed and logically software defined according to application requirements for connecting the different computing modules 131 and/or storage modules 133 and/or I/O modules 134.

The network element 12 is connected to the under bump metallization by conductive connections 17 to achieve an electrical coupling of the network element 12 to the rewiring structure 11. To protect the functional surfaces of the network element 12 and the conductive connection 17, the gap between the network element 12 and the rewiring structure 11 is filled with an underfill 14.

Below the rewiring structure 11 a molding compound 16 is arranged for encapsulating the network element 12. In the vertical direction, the molding compound 16 and the sidewalls of the rewiring structure 11 may be coplanar or the sidewalls of the rewiring structure 11 may be covered by the molding compound 16. The overall body of the rewiring structure 11 and the network element 12 thereunder and the molding compound 16 for encapsulating the network element 12 is the reconstituted wafer substrate 1.

In this way, the network unit 12 is used as the network-on-chip carrier of the on-chip system, and interconnection among hundreds of network-on-chip units 12 is completed through a re-wiring technology, particularly a fan-out RDL technology, and an interface of the computing modules 131 is provided, so that a plurality of computing modules 131 can realize programmable logic interconnection through the network-on-chip constructed by the network unit 12, and therefore, the computing modules 131 and the network unit 12 can be flexibly laid out. The modules with different functions such as the computing module 131 are arranged outside the reconstructed wafer substrate 1, so that the on-chip system using the packaging structure can integrate different functional modules, and the functions are richer.

As shown in fig. 2, any external power module 132 is electrically coupled to the power interconnect structure 142 and provides power to the computing module 131 and the network unit 12 disposed around the external power module 132. The external power module 132 includes a power interface, on which an external power board 4 is plugged, where the external power board 4 includes a board body 43, and the board body 43 is provided with a power connector 41 for plugging with the power interface and an external power management circuit for supplying power to the power interface, including an external voltage conversion circuit and a matching circuit (such as a clock circuit, a reset circuit, etc.). The board body 43 of the external power supply board 4 may further be provided with a power chip 42, and the above external power management circuit may be partially or fully integrated in the power chip 42.

The external power module 132 is further provided with a core power management circuit for supplying power to the computing module 131 and/or the network unit 12, and the core power management circuit comprises a core voltage conversion circuit and a matching circuit (such as a clock circuit, a reset circuit, etc.). The input of the kernel power management circuit is electrically coupled to the power interface. The output of the core power management circuit is electrically coupled to the computing module 131 and/or the network element 12 via the power interconnect 142 according to a predetermined setting. If the functional module further includes a memory module 133, the kernel power management circuit is also used to supply power to the memory module 133. The output of the core power management circuit is electrically coupled to the memory module 133 through the power interconnect structure 142.

In some embodiments, the external power module 132 is electrically coupled to the I/O module 134 through a rewiring structure, and an interface power management circuit for supplying power to the I/O module 134 is further provided on the external power module 132, including an interface voltage conversion circuit and a supporting circuit (e.g., a clock circuit, a reset circuit, etc.). The input of the interface power management circuit is electrically coupled to the power interface. The output of the interface power management circuit is electrically coupled to the I/O module 134 via the power interconnect structure 142.

In this way, the on-chip system of the packaging structure is provided with a plurality of external power supply modules 132 in a scattered manner, so that the power supply network of the on-chip system is distributed uniformly. The whole power supply scheme of the system is realized by means of external vertical power supply and on-chip shunt power supply, the area of a power supply processing part on the system is reduced, and the whole utilization rate of the on-chip system using the packaging structure is increased.

As shown in fig. 3, the power supply system on the package structure includes a power supply bus and a power control bus, as an example.

The power signal flows into the external power supply board 4 from the power supply bus, is stabilized and divided by the external power management circuit on the external power supply board 4, and is transmitted to the external power supply module 132 through the power connector 41 and the power port. Then, the secondary voltage division and voltage stabilization are carried out by the kernel power management circuit on the external power supply module 132 and then transmitted to the calculation module 131 and/or the storage module 133 and/or the network unit 12; or the voltage is divided and stabilized twice by an interface power management circuit on the external power module 132 and then transmitted to the I/O module 134.

Specifically, the power input terminal of the external power supply board 4 is connected to the power supply bus, and receives a power signal from the power supply bus. The power signal is output from the power connector 41 to the power port of the external power module 132 after being subjected to voltage stabilization and voltage division by the external power management circuit.

As shown in fig. 3, after the power signal enters the external power module 132 from the power port, the power signal is subjected to secondary voltage division and voltage stabilization by the kernel power management circuit, and then is output to the power interconnection structure 142, and is transmitted to the computing module 1311 and/or the network unit 12 and/or the storage module 133 through the power interconnection structure 142.

As shown in fig. 4, the power interconnection structure 142 is connected with the I/O module 134, and after the power signal enters the external power module 132 from the power port, a part of the power signal is subjected to the secondary voltage division and stabilization treatment by the core power management circuit, and then is output to the power interconnection structure 142, and is transmitted to the computing module 1311 and/or the network unit 12 and/or the storage module 133 through the power interconnection structure 142. The other part is output to the I/O module 134 through the power supply interconnection structure 142 after the second voltage division and voltage stabilization process by the interface power management circuit.

The external power management circuit, the kernel power management circuit and the interface power management circuit are all connected to the power control bus and receive control signals from the power control bus. The control signals are generated by the upper control circuit. The upper control circuit can be integrated in one or more functional modules, and can also be integrated in a controller or a host outside the on-chip system, and the upper control circuit monitors and schedules the power supply of the whole on-chip system.

By respectively arranging the power control bus and the power supply bus, the power control signal of the on-chip system using the packaging structure is prevented from being interfered by the power signal, so that the power supply scheme is more reasonable and the packaging structure is suitable for practical use.

The functional module may be a chip with a corresponding function, or may be a combination of a chip with a corresponding function and the socket 135. The receptacle 135 is an electrical interface and a physical interface of the corresponding functional module.

Specifically, a user of the package structure may install the computing device 1311 in the socket 135 to form a fully functional computing module 131 or the I/O connector in the socket 135 to form a fully functional I/O module 134 or the memory device in the socket 135 to form a fully functional memory module 133.

The arrangement is convenient for completing quick replacement when the functional device is damaged, and the integral performance of the system on chip using the packaging structure is prevented from being influenced by the damage of the single device.

Example 2

As shown in fig. 5, the packaging method of the packaging structure of embodiment 1 includes the preparation of the reconstituted wafer substrate 1 and the mounting of the functional module.

The reconstituted wafer substrate 1 described above includes the rewiring structure 11 and the network unit 12 in the package structure of embodiment 1, and the molding compound 16 for encapsulating the network unit 12.

The preparation of the reconstituted wafer substrate 1 comprises the steps of:

a layer of temporary bonding material 91 is coated on the temporary carrier plate 9. The re-wiring structure 11 having the data interconnection structure 141 and the power interconnection structure 142 isolated from each other is formed on the temporary bonding material through a re-wiring process.

The network element 12 with the conductive connection 17 is flip-chip mounted onto the rewiring structure 11 such that the data I/O area of the network element is electrically coupled to the data interconnect structure 141 and the power I/O area of the network element is electrically coupled to the power interconnect structure 142.

After the mounting is completed, the underfill 14 may be filled in the gap between the network element 12 and the rewiring structure 11, and baked. After the mounting is completed, all the chips are reformed into a wafer shape of a whole piece by using a plastic package material 16 in a wafer plastic package mode, so as to form the reformed wafer substrate 1.

The temporary carrier 9 is removed and the reconstituted wafer is cleaned by means of de-bonding (which may be thermal or laser de-bonding) compatible with the temporary bonding material 91 so that the interconnect pads in the RDL interconnect metal pattern are exposed.

The mounting of the functional module comprises the following steps: the functional module with the conductive connections 17 is functionally face down mounted on the corresponding interconnect pads of the reconstituted wafer substrate 1. The data I/O area of the computing module 131 is electrically coupled to the data interconnect structure 141, the power I/O area of the computing module 131 is electrically coupled to the power interconnect structure 142, and the external power module 132 is electrically coupled to the power interconnect structure 142.

In some embodiments, an underfill 14 may be used in the gap between the functional module and the rewiring structure 11 after the mounting is completed.

It should be noted that the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same. While the application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements thereof without departing from the scope of the application, which is to be encompassed by the appended claims.

Claims (10)

1. A semiconductor packaging structure comprises a reconstituted wafer substrate and a plurality of functional modules, wherein the reconstituted wafer substrate comprises a rewiring structure and a plurality of network units; the method is characterized in that: the functional modules are positioned on one side of the rerouting structure, the functional modules are electrically coupled with the rerouting structure, the network units are positioned on the other side of the rerouting structure, and the network units are electrically coupled with the rerouting structure; the function module comprises a calculation module and an external power supply module for supplying power to the calculation module and the network unit; the network unit is internally provided with an on-chip network interconnection channel for realizing non-power signal routing and on-chip communication interconnection, and the functional modules are interconnected through the on-chip network interconnection channel and a rewiring structure of the network unit; a data interconnection structure and a power supply interconnection structure are arranged in the rewiring structure; the data interconnection structure and the power interconnection structure are isolated from each other.

2. The semiconductor package according to claim 1, wherein: the RDL interconnection metal pattern of the data interconnection structure and the RDL interconnection metal pattern of the power supply interconnection structure are respectively located in different dielectric layers.

3. A semiconductor package according to claim 1 or 2, wherein: the projection of the data interconnection structure in the vertical direction is completely non-overlapping with the projection of the power interconnection structure in the vertical direction.

4. A semiconductor package according to claim 3, wherein: a circuit-free area is arranged between the projection area of the data interconnection structure in the vertical direction and the projection area of the power supply interconnection structure in the vertical direction.

5. The semiconductor package according to claim 4, wherein: the computing module and the network unit are both provided with a data I/O area and a power I/O area; the data I/O region is electrically coupled to the data interconnect structure, and the power I/O region is electrically coupled to the power interconnect structure; the external power module is electrically coupled with the power supply interconnection structure.

6. The semiconductor package according to claim 1, wherein: the external power supply module comprises a power supply interface, an external power supply board is inserted on the power supply interface, and the external power supply board comprises a power supply connector connected with the power supply interface and an external power supply management circuit for outputting power supply signals to the power supply interface.

7. The semiconductor package according to claim 6, wherein: the external power supply module is also provided with a kernel power supply management circuit for supplying power to a plurality of computing modules and/or network units arranged around the external power supply module, the input end of the kernel power supply management circuit is electrically coupled with the power supply interface, and the output end of the kernel power supply management circuit is electrically coupled with the computing modules and/or the network units through a power supply interconnection structure.

8. A semiconductor package according to any one of claim 1, wherein: the computing module comprises a computing device with a computing function and/or a whole formed by plugging the computing device with the computing function and a socket; the functional module further comprises an I/O module for signal interaction with an external device and/or a storage module with a storage function; the I/O module comprises an I/O connector and/or a socket and the I/O connector are spliced to form a whole; the storage module comprises a storage device and/or a socket and the storage device which are spliced to form a whole.

9. The semiconductor package according to claim 8, wherein: the external power supply module is also provided with an interface power supply circuit for supplying power to the I/O module, the input end of the interface power supply management circuit is electrically coupled with the power supply interface, and the output end of the interface power supply management circuit is electrically coupled with the I/O module through a power supply internal connection structure.

10. A semiconductor packaging method for the semiconductor packaging structure according to any one of claims 1 to 9, comprising the steps of:

preparing a temporary carrier plate, coating a temporary bonding material on the temporary carrier plate, and forming a rerouting structure with a data interconnection structure and a power supply interconnection structure which are isolated from each other on the temporary bonding material through a rerouting process;

mounting the network element patch on a rewiring structure, and encapsulating all network elements or the network elements and the rewiring structure by using a plastic packaging material in a wafer plastic packaging mode to form a reconstructed wafer substrate;

dismantling the temporary carrier plate and cleaning the reconstituted wafer substrate in a de-bonding mode which is suitable for the temporary bonding material to expose the interconnection welding spots on the rewiring structure;

the functional module with the conductive connecting piece is attached to the corresponding interconnection welding point, so that the data I/O area of the computing module and the network unit are electrically coupled with the data interconnection structure, the power I/O area of the computing module and the network unit are electrically coupled with the power interconnection structure, and the external power module is electrically coupled with the power interconnection structure.