CN116387260A - Wafer-level integrated structure for heterogeneous chips - Google Patents

Wafer-level integrated structure for heterogeneous chips Download PDF

Info

Publication number
CN116387260A
CN116387260A CN202310539914.4A CN202310539914A CN116387260A CN 116387260 A CN116387260 A CN 116387260A CN 202310539914 A CN202310539914 A CN 202310539914A CN 116387260 A CN116387260 A CN 116387260A
Authority
CN
China
Prior art keywords
circuit board
chips
printed circuit
module
integrated structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310539914.4A
Other languages
Chinese (zh)
Inventor
姜申飞
潘岳
胡杨
王磊
李霞
朱小云
王立华
郝培霖
韩慧明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Shanghai AI Innovation Center
Original Assignee
Tsinghua University
Shanghai AI Innovation Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University, Shanghai AI Innovation Center filed Critical Tsinghua University
Priority to CN202310539914.4A priority Critical patent/CN116387260A/en
Publication of CN116387260A publication Critical patent/CN116387260A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to the technical field of semiconductor manufacturing, and provides a wafer-level integrated structure for heterogeneous chips, which comprises the following components: a printed circuit board; an interposer disposed on the printed circuit board; and a plurality of chips arranged on the interposer, wherein the chips include a plurality of heterogeneous chips including a computing chip and a memory chip and/or a plurality of bare chips. The heterogeneous chips are interconnected between high-speed chips through the adapter plate, so that the number of input/output channels for external connection is greatly reduced. The heterogeneous chip comprises a computing chip and a storage chip, and the computing chip and the storage chip are connected through the adapter plate, so that the length of a signal link can be reduced, and the number of connectors is reduced.

Description

Wafer-level integrated structure for heterogeneous chips
Technical Field
The present invention relates generally to the field of semiconductor manufacturing technology. In particular, the present invention relates to a wafer level integrated structure for heterogeneous chips.
Background
Wafer level packaging (WLP, wafer Level Package) refers to a packaging technique in which most or all of the packaging test procedures are performed directly on a wafer, and then dicing (sawing) is performed to form individual chip assemblies. Wafer level packages have the advantage of smaller package size and better electrical performance, and are now widely used for low-pin-count consumer integrated circuit (IC, integrated Circuit) packages.
In the prior art, chinese patent CN114823592a discloses a system-on-chip structure and a method for manufacturing the same, the structure comprising a wafer substrate, an integrated core, a system configuration board and a system heat dissipation module. The wafer substrate and the integrated core particle are connected through bonding of a wafer micro-bump array on the upper surface of the wafer substrate and a core particle micro-bump array on the lower surface of the integrated core particle; the wafer substrate and the system configuration plate are connected through bonding of a copper column array on the wafer substrate and a bonding pad on the lower surface of the system configuration plate; a plastic layer is arranged between the wafer substrate and the system configuration board, and the wafer substrate, the integrated core particle and the copper column array are subjected to plastic packaging; the integrated core grains are electrically connected through a rewiring layer arranged on the top of the wafer substrate; the system configuration board is electrically connected with the integrated core particle through the rewiring layer and the copper column array; the system heat dissipation module is attached to the lower surface of the wafer substrate.
However, the following problems still remain in the prior art: the number of connections between the plurality of wafer level chips is limited; the number of interconnect lines between wafer level chips is limited; bandwidth between wafer level chips is limited; the communication path between the wafer level chips is long, so that communication needs to be performed by means of an Interposer, a Substrate (submount) or a Printed Circuit Board (PCB), and the power supply path is long and the heat dissipation effect is poor.
Disclosure of Invention
To at least partially solve the above-mentioned problems in the prior art, the present invention proposes a wafer-level integrated structure for heterogeneous chips, comprising:
a printed circuit board;
an interposer disposed on the printed circuit board; and
and a plurality of chips arranged on the adapter plate, wherein the chips comprise a plurality of heterogeneous chips and/or a plurality of bare chips, and the heterogeneous chips comprise a computing chip and a storage chip.
In one embodiment of the invention, it is provided that the printed circuit board comprises a plurality of printed circuit board modules separated from one another, the printed circuit board modules comprising:
a plurality of first printed circuit board modules; and
a plurality of second printed circuit board modules disposed around the plurality of first printed circuit board modules.
In one embodiment of the invention, it is provided that a plurality of the first printed circuit board modules are connected on a first side to the adapter plate via a ball grid array.
In one embodiment of the present invention, it is provided that the wafer-level integrated structure for heterogeneous chips further includes:
an input/output connector disposed on a first face of at least a portion of a plurality of said second printed circuit board modules.
In one embodiment of the invention, it is provided that a plurality of said chips are interconnected by hybrid bonding.
In one embodiment of the present invention, it is provided that the wafer-level integrated structure for heterogeneous chips further includes:
a first heat dissipation module disposed on the plurality of chips, wherein the plurality of chips are connected to the first heat dissipation module through a thermally conductive layer;
a second heat dissipation module connecting the first heat dissipation module with the first face of the second printed circuit board module; and
and the third heat dissipation module is connected with the second surface of the second printed circuit board module.
In one embodiment of the invention, it is provided that the wafer-level integrated structure for heterogeneous chips further comprises a vertical power module comprising:
a DC input terminal;
the voltage regulating circuit board is connected with the direct current input end;
a power supply connector connected to the voltage regulation circuit board; and
and the secondary power supply module is connected with the power supply connector and the second surface of the first printed circuit board module.
In one embodiment of the invention, the voltage regulating circuit board is provided with a voltage regulating module and an inductance capacitance filtering module.
In one embodiment of the invention, the wafer-level integrated structure for heterogeneous chips comprises a plurality of vertical power supply modules, wherein each of the first printed circuit board modules is connected with one of the plurality of vertical power supply modules, and the plurality of vertical power supply modules is provided with a fourth heat dissipation module.
In one embodiment of the invention, it is provided that the second heat dissipating module, the third heat dissipating module and/or the fourth heat dissipating module are an integrated heat sink and mechanical support.
The invention has at least the following beneficial effects: the invention provides a wafer-level integrated structure for heterogeneous chips, wherein a plurality of heterogeneous chips are interconnected with each other at a high speed through an adapter plate (Interposer), so that the number of Input/Output (IO) channels for external connection is greatly reduced. The heterogeneous chip comprises a computing chip and a storage chip, and the computing chip and the storage chip are connected through the adapter plate, so that the length of a signal link can be reduced, and the number of connectors is reduced. The structure integrates the vertical power supply module, and functionally integrates devices for improving the integrity of a power supply besides the conventional chip function. The structure is provided with a plurality of heat dissipation modules, and can realize effective heat dissipation of the chip and the power supply module which exceed kilowatt power consumption. The structure provides the separated PCB, and the stress between the adapter plate and the PCB can be effectively reduced. In addition, the structure integrates the input/output connectors around the adapter plate, so that the IO channels which are fanned outwards can be separated from the power supply channels, and interconnection between systems is further facilitated.
Drawings
To further clarify the advantages and features present in various embodiments of the present invention, a more particular description of various embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
Fig. 1 illustrates a schematic plan view of a wafer level integrated structure for heterogeneous chips in accordance with one embodiment of the present invention.
Fig. 2 illustrates a schematic cross-sectional view of a wafer level integrated structure for heterogeneous chips in accordance with one embodiment of the present invention.
Detailed Description
It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale. In the drawings, identical or functionally identical components are provided with the same reference numerals.
In the present invention, unless specifically indicated otherwise, "disposed on …", "disposed over …" and "disposed over …" do not preclude the presence of an intermediate therebetween. Furthermore, "disposed on or above" … merely indicates the relative positional relationship between the two components, but may also be converted to "disposed under or below" …, and vice versa, under certain circumstances, such as after reversing the product direction.
In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.
In the present invention, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.
It should also be noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present invention. In addition, features of different embodiments of the invention may be combined with each other, unless otherwise specified. For example, a feature of the second embodiment may be substituted for a corresponding feature of the first embodiment, or may have the same or similar function, and the resulting embodiment would fall within the disclosure or scope of the disclosure.
It should also be noted herein that, within the scope of the present invention, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal". By analogy, in the present invention, the term "perpendicular", "parallel" and the like in the table direction also covers the meaning of "substantially perpendicular", "substantially parallel".
The numbers of the steps of the respective methods of the present invention are not limited to the order of execution of the steps of the methods. The method steps may be performed in a different order unless otherwise indicated.
The invention is further elucidated below in connection with the embodiments with reference to the drawings.
Fig. 1 illustrates a schematic plan view of a wafer level integrated structure for heterogeneous chips in accordance with one embodiment of the present invention. As shown in fig. 1, the wafer level integrated structure includes a Printed Circuit Board (PCB) 101, an Interposer (Interposer) 102, a chip (Die), and a Connector (Connector) 104. Wherein the interposer 102 and the plurality of connectors 104 are arranged on the printed circuit board 101, the plurality of connectors 104 are arranged around the interposer 102, and the plurality of chips are arranged on the interposer 102. The chips may be heterogeneous chips and/or bare chips of different functions that have been diced, tested, but not yet packaged, the heterogeneous chips may include a Compute Die 1031 and a memory Die (HBM or DDR) 1032, the Compute Die 1031 may be a qualified Die (Known Good Die), and the memory Die 1032 may be a dynamic random access memory Die (DRAM, dynamic Random Access Memory). The plurality of the computing chips 103 and the memory chip 1032 may be interconnected by Hybrid Bonding (Hybrid Bonding), wherein the term "Hybrid Bonding" refers to Bonding Cu electrodes and dielectric layers on the chip simultaneously, and Micro bumps (Micro bumps) may be omitted by Hybrid Bonding, and the interconnection pitch of Bonding may be reduced to 10 μm or less. The interconnection width and the Pitch (Pitch) are reduced, so that the interconnection density is greatly improved, and the interconnection bandwidth is improved.
Fig. 2 shows a schematic cross-sectional view of a wafer level integrated structure for heterogeneous chips in accordance with one embodiment of the present invention, which is further described below in conjunction with fig. 2. As shown in fig. 2, the printed circuit board 101 includes a plurality of printed circuit board modules separated from each other, and the printed circuit board modules include a first printed circuit board module 1011 and a second printed circuit board module 1012.
The first surfaces of the plurality of first printed circuit board modules 1011 that are separated from each other may be connected to the interposer 102 through a Ball Grid Array (BGA) 201, so that the problem of excessive stress between the printed circuit board and the interposer in the conventional wafer level package structure may be solved. The interposer 102 is provided with through silicon vias (TSV, through Silicon Via). A plurality of the second printed circuit board modules 1012 are arranged around a plurality of the first printed circuit board modules 1011, wherein the connectors 104 are arranged on a first face of at least a portion of the plurality of the second printed circuit board modules 1012, and the connectors 104 may be input/output connectors (IO connectors).
A plurality of heat dissipation modules may be disposed on the structure. Wherein the chip 103 may be connected to the first heat dissipation module (Top Thermal Module) 2031 by a thermally conductive layer 202, the thermally conductive layer 202 may be formed of a thermal interface material (TIM, thermal Interface Material). The first heat dissipation module 2031 may also be connected to a first side of the second printed circuit board module 1012 through a second heat dissipation module 2032, and a second side of the second printed circuit board module 1012 opposite to the first side is connected to a third heat dissipation module 2033. The second heat dissipation module 2032 and the third heat dissipation module 2033 may be an integrated heat sink and mechanical support (Integrated Radiator and Mechanical Support Components), that is, the second heat dissipation module 2032 and the third heat dissipation module 2033 may function as both heat dissipation and mechanical support.
Each of the first printed circuit board modules 1011 may be connected to a respective one of the vertical power supply modules. A fourth heat spreading module 2034 may be provided between a plurality of the vertical power supply modules, and the fourth heat spreading module 2034 may also be an integral heat sink and mechanical support. The vertical Power Module includes a direct current input (DC IN) 2041, a voltage regulation circuit board (VR PCB) 2042, a Power Connector (Power Connector) 2043, and a secondary Power Module (MCM) 2044.
The dc input 2041 is connected to the voltage control circuit board 2042. The voltage regulating circuit board 2042 has a voltage regulating module (VRM, voltage Regulator Module) and an LC filter module (LC) disposed thereon. The voltage regulating circuit board 2042 is connected to the power connector 2043, the power connector 2043 is connected to the secondary power module 2044, and the secondary power module 2044 is connected to the first printed circuit board module 1011.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. A wafer level integrated structure for heterogeneous chips, comprising:
a printed circuit board;
an interposer disposed on the printed circuit board; and
and a plurality of chips arranged on the adapter plate, wherein the chips comprise a plurality of heterogeneous chips and/or a plurality of bare chips, and the heterogeneous chips comprise a computing chip and a storage chip.
2. The wafer level integrated structure for heterogeneous chips of claim 1, wherein the printed circuit board comprises a plurality of printed circuit board modules separated from each other, the printed circuit board modules comprising:
a plurality of first printed circuit board modules; and
a plurality of second printed circuit board modules disposed around the plurality of first printed circuit board modules.
3. The wafer level integrated structure for heterogeneous chips of claim 2, wherein a plurality of first sides of the first printed circuit board modules are connected to the interposer through a ball grid array.
4. The wafer level integrated structure for heterogeneous chips of claim 2, further comprising:
an input/output connector disposed on a first face of at least a portion of a plurality of said second printed circuit board modules.
5. The wafer level integrated structure for heterogeneous chips of claim 1, wherein a plurality of said chips are interconnected by hybrid bonding.
6. The wafer level integrated structure for heterogeneous chips of claim 2, further comprising:
a first heat dissipation module disposed on the plurality of chips, wherein the plurality of chips are connected to the first heat dissipation module through a thermally conductive layer;
a second heat dissipation module connecting the first heat dissipation module with the first face of the second printed circuit board module; and
and the third heat dissipation module is connected with the second surface of the second printed circuit board module.
7. The wafer level integrated structure for heterogeneous chips of claim 6, further comprising a vertical power module comprising:
a DC input terminal;
the voltage regulating circuit board is connected with the direct current input end;
a power supply connector connected to the voltage regulation circuit board; and
and the secondary power supply module is connected with the power supply connector and the second surface of the first printed circuit board module.
8. The wafer level integrated structure for heterogeneous chips of claim 7, wherein the voltage regulation circuit board is provided with a voltage regulation module and an lc filter module.
9. The wafer level integrated structure for heterogeneous chips of claim 7, comprising a plurality of vertical power modules, wherein each of the first printed circuit board modules is connected to a respective one of the plurality of vertical power modules, and wherein the plurality of vertical power modules is arranged with a fourth heat dissipation module.
10. The wafer level integrated structure for heterogeneous chips of claim 9, wherein the second, third and/or fourth heat dissipating modules are integral heat sinks and mechanical supports.
CN202310539914.4A 2023-05-12 2023-05-12 Wafer-level integrated structure for heterogeneous chips Pending CN116387260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310539914.4A CN116387260A (en) 2023-05-12 2023-05-12 Wafer-level integrated structure for heterogeneous chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310539914.4A CN116387260A (en) 2023-05-12 2023-05-12 Wafer-level integrated structure for heterogeneous chips

Publications (1)

Publication Number Publication Date
CN116387260A true CN116387260A (en) 2023-07-04

Family

ID=86963572

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310539914.4A Pending CN116387260A (en) 2023-05-12 2023-05-12 Wafer-level integrated structure for heterogeneous chips

Country Status (1)

Country Link
CN (1) CN116387260A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117377327A (en) * 2023-12-05 2024-01-09 荣耀终端有限公司 Packaging structure, packaging chip and electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117377327A (en) * 2023-12-05 2024-01-09 荣耀终端有限公司 Packaging structure, packaging chip and electronic equipment

Similar Documents

Publication Publication Date Title
US7750459B2 (en) Integrated module for data processing system
US7230334B2 (en) Semiconductor integrated circuit chip packages having integrated microchannel cooling modules
US7611923B2 (en) Method and apparatus for forming stacked die and substrate structures for increased packing density
US7297574B2 (en) Multi-chip device and method for producing a multi-chip device
US8390109B2 (en) Chip package with plank stack of semiconductor dies
US20180040587A1 (en) Vertical Memory Module Enabled by Fan-Out Redistribution Layer
JP2014099591A (en) Multi-chip module connection by way of bridging blocks
US20040178502A1 (en) Semiconductor device
US11671010B2 (en) Power delivery for multi-chip-package using in-package voltage regulator
US8331094B2 (en) Thermal and power bus stacked package architecture
CN116387260A (en) Wafer-level integrated structure for heterogeneous chips
CN116544206A (en) Wafer level integrated structure with separated substrate
CN116544207A (en) System-level interconnection structure for multiple isomorphic chips
CN110544673B (en) Multilayer fused three-dimensional system integrated structure
US20240063129A1 (en) Semiconductor package
US20230230902A1 (en) Semiconductor package structure and manufacturing method thereof
CN113764396B (en) Semiconductor packaging structure based on rewiring layer and packaging method thereof
CN115394768A (en) Multilayer high-bandwidth memory and manufacturing method thereof
CN116387261A (en) Wafer-level integrated structure for isomorphic chips
CN112397475A (en) Fan-out type packaging chip structure and unit with fine-pitch through-silicon-via packaging
US20240055343A1 (en) Semiconductor package structure
CN220233193U (en) 2.5D packaging structure for improving power signal transmission
US20230326861A1 (en) Electronic package
US20230326889A1 (en) Electronic package
US20230261572A1 (en) Power delivery for multi-chip-package using in-package voltage regulator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination