CN116661579A

CN116661579A - Semiconductor device and structure of 3D heterogeneous programmable chip power supply network

Info

Publication number: CN116661579A
Application number: CN202310638536.5A
Authority: CN
Inventors: 武强; 余兴
Original assignee: Shanghai Xinfeng Microelectronics Co ltd
Current assignee: Shanghai Xinfeng Microelectronics Co ltd
Priority date: 2023-05-31
Filing date: 2023-05-31
Publication date: 2023-08-29

Abstract

The embodiment of the disclosure discloses a semiconductor device and a semiconductor structure, the control circuit includes: a central controller; the control circuit is coupled with the power conversion circuit and controls the power conversion circuit; the power conversion circuit comprises a power controller, a voltage converter and an analog-to-digital converter, wherein the voltage converter and the analog-to-digital converter are coupled with the power controller; the power controller is configured to control the voltage converter to convert and output a voltage; the digital-to-analog converter is configured to acquire an output signal of the voltage converter and convert the signal into a programming parameter; the power controller is configured to receive the programming parameters and send the programming parameters to the central controller; the central controller is configured to control the power controller according to the programming parameters; the semiconductor structure includes a 3D stacked architecture of the semiconductor device and other logic semiconductor devices and memory semiconductor devices.

Description

Semiconductor device and structure of 3D heterogeneous programmable chip power supply network

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a circuit architecture for supplying power to other various semiconductors by a semiconductor device in the advanced semiconductor 3D heterogeneous integration field and a 3D stacking structure of the semiconductors.

Background

With the increase of Chip density, current and power consumption, the design of On-Chip power supply network (On-Chip Power Distribution Network, PDN) of SoC Chip (System On a Chip) is more and more complex and difficult to meet the design requirements. Further shrinking of semiconductor fabrication process dimensions, further increasing of integration density, especially for use of 7nm and smaller 3nm processes, the supply voltage of some devices in the chip may be lower than 0.5V, and in order to maintain the power consumption of the devices in normal operation, the supply current needs to be increased, so that the power supply heat loss inside the chip increases, meanwhile, the interconnection lines (e.g., power supply leads) of the chip greatly increase, the heat consumption of the wires increases, resulting in an increase of the total power consumption of the SoC chip, and the performance decreases. How to solve the power supply of the high-integration density chip is a problem to be solved urgently.

Disclosure of Invention

In view of the foregoing, embodiments of the present disclosure provide a semiconductor device and a semiconductor structure. The power supply system is characterized by a novel on-chip power supply network, can perform on-chip voltage conversion, combination and real-time adjustment, and simultaneously provides a stacking framework of power supply semiconductor wafers and other types of semiconductors by combining a 3D stacking technology.

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor device including: a control circuit including a central controller; the control circuit is coupled with the power conversion circuit and controls the power conversion circuit;

the power conversion circuit comprises a power controller, a voltage converter and an analog-to-digital converter, wherein the voltage converter and the analog-to-digital converter are coupled with the power controller; the power controller is configured to control the voltage converter to convert and output a voltage;

the analog-to-digital converter is configured to collect an output signal of the voltage converter and convert the signal into a programming parameter;

the power controller is configured to receive the programming parameters and send the programming parameters to the central controller;

the central controller is configured to control the power controller according to the programming parameters.

In some embodiments, the voltage converter comprises: a DC-DC voltage converter.

In some embodiments, the power conversion circuit further comprises:

a first memory configured to store configuration information for the central controller to control the power controller according to the programming parameters.

In some embodiments, the power conversion circuit further comprises:

a temperature sensor coupled to the analog-to-digital converter; the temperature sensor is configured to acquire a temperature of the power conversion circuit.

In some embodiments, the power conversion circuit further comprises:

an output circuit coupled with the voltage converter and the power controller; wherein the output circuit includes a first terminal having a first switch, and a second terminal;

the power controller is further configured to control the first switch to be turned on and off;

the first terminal is configured to interconnect with other of the power conversion circuits; the first terminal is comprised of 1 or more switches controlled by the power controller.

The second terminal is configured to be coupled to an output of the power conversion circuit.

In some implementations, the number of first terminals is greater than or equal to 1.

In some embodiments, the control circuit further comprises:

a second memory coupled to the central controller and a first memory.

In some embodiments, the control circuit further comprises:

and a clock circuit coupled to the central controller, the clock circuit configured to generate a clock signal.

In some embodiments, the semiconductor device further comprises:

a clock signal line configured to transmit the clock signal between the control circuit and the power conversion circuit.

According to a second aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:

a first semiconductor device including the semiconductor device of any of the above embodiments, and a first bonding layer including a plurality of first bonding contacts;

a second semiconductor device including a logic circuit, a second bonding layer including a plurality of second bonding contacts; wherein the first bonding layer and the second bonding layer are bonded; the first semiconductor device supplies power to the second semiconductor device through the first bonding contact and the second bonding contact.

In some embodiments, the semiconductor structure further comprises:

a first conductive via (Through Silicon Via, TSV) extends through the first semiconductor device, the first conductive via being coupled with the second semiconductor device.

In some embodiments, the semiconductor structure further comprises:

a third semiconductor device including a memory device, a third bonding layer including a plurality of third bonding contacts; the third bonding layer is bonded with a fourth bonding layer of the second semiconductor device, the fourth bonding layer and the second bonding layer are located on two planes which are oppositely arranged, and the fourth bonding layer comprises a plurality of fourth bonding contacts; the third semiconductor device and the second semiconductor device are coupled through the third bonding contact and the fourth bonding contact.

In some embodiments, the semiconductor structure further comprises:

and a second conductive path extending through the second semiconductor device, the second conductive path being coupled to the third semiconductor device.

In some embodiments, the semiconductor structure further comprises:

and a package substrate coupled with the first semiconductor device.

The control circuit of the embodiment of the disclosure comprises a central controller; the control circuit is coupled with the power conversion circuit and controls the power conversion circuit; the power conversion circuit comprises a power controller, a voltage converter, a first memory and an analog-to-digital converter, wherein the voltage converter, the first memory and the analog-to-digital converter are coupled with the power controller; the power controller is configured to control the voltage converter to convert and output a voltage; an analog-to-digital converter configured to collect an output signal of the voltage converter and convert the signal into a programming parameter; the power controller is configured to send programming parameters to the central controller and control the voltage converter according to the parameters; the central controller is configured to control the power controller according to the programmed parameters. The central controller is programmed according to programming parameters, and controls different power conversion circuits to output different voltages or currents, so that the power supply stability is improved, and the power supply for different circuits is facilitated.

Drawings

FIG. 1 is a schematic diagram of a PDN circuit currently in common use, shown in accordance with an exemplary embodiment;

fig. 2 is a schematic diagram of a semiconductor device with an on-chip voltage converter, control circuitry, and PDN circuitry of the internet, shown in accordance with an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a circuit of a control module shown in accordance with an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a circuit of a power conversion module shown in accordance with an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a 3D semiconductor chip structure implementing PDNs and logic circuits on different wafers and then re-bonding, with PDN wafers at the lower end of the logic wafers, according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a 3D semiconductor chip structure semiconductor structure implementing PDN and logic circuits on different wafers and then re-bonded, with the PDN wafer on top of the logic wafer, according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a 3D semiconductor structure in which PDN, logic and DRAM circuits are implemented on different wafers, respectively, and then the wafers are bonded according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of a 3D semiconductor structure with PDN implemented on an active die substrate (active interconnect) and logic and DRAM circuits implemented on other wafers and then wafer bonded to the active die substrate, according to an embodiment of the disclosure.

Detailed Description

The technical scheme of the present disclosure is further elaborated below in conjunction with the drawings of the specification and the specific embodiments.

In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not for describing a particular sequential or chronological order.

In the embodiments of the present disclosure, the term "a contacts with B" includes the case where a contacts with B directly, or the case where a contacts with B indirectly with other members interposed therebetween A, B.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. Also, a layer may include a plurality of sub-layers.

It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

It should be noted that, although the present disclosure describes embodiments, not every embodiment includes only a single embodiment, and the description is for clarity only, and those skilled in the art should consider the disclosure as a whole, and the embodiments may be combined appropriately to form other embodiments that can be understood by those skilled in the art.

With the popularization of intelligent devices and the increasing computing power of computers, more and more functional devices are integrated on an integrated circuit, and taking an SoC chip (or SoC system) as an example, a general SoC may also be called a system-on-chip, also called a system-on-chip, is an integrated circuit with a special purpose, and includes a complete system and has the entire content of embedded software. It is also a technique to achieve the whole process from determining the system functions, to software/hardware partitioning, and to complete the design. The SoC chip can integrate a whole information processing system on a chip carrier, is simply a very large scale integrated circuit which can expand audio and video functions and special interfaces on the basis of a processor, and can be used as the brain of intelligent equipment. The application processor AP (Application Processor) is an integration of all compute chips in the SoC including the CPU. The smart phone SoC generally comprises an AP and a baseband processor BP, etc., where the AP is responsible for running an application program, and the BP is responsible for receiving and transmitting wireless signals.

With the development of semiconductor technology, the traditional MCU can not completely meet the requirements of intelligent terminals, and SoC has been developed, so that a single chip can complete a complete electronic system by virtue of the characteristics of strong performance, low power consumption and high flexibility. Socs are very popular in mobile computing (e.g., smartphones and tablet computers) and edge computing markets. They are also commonly used in embedded systems such as WiFi routers and the internet of things.

Currently, the SoC is the most functional hardware, and integrates various functional modules such as CPU, GPU, RAM, ADC (analog-to-digital converter), DAC (digital-to-analog converter), modem (Modem), high-speed DSP (digital signal processor), and the like, and part of the SoC also integrates a power management module and control modules of various external devices, and meanwhile, needs to consider the distribution and utilization of various buses.

The current further shrinking of semiconductor fabrication process dimensions to facilitate the integration of more functional devices on SoC chips, the exposure dimensions of photolithography approaches the physical limits of silicon atoms, and moore's law of semiconductors is difficult to keep pace, and the proposition of 3D stacked heterogeneous integrated architectures (e.g., HBM, HMC chips) is an effective approach to keep SoC chip density and performance continually increasing in the latter molar era. Whether planar-latitude integrated circuit layout or stacked heterogeneous integrated architecture, in a single-use integrated circuit package unit, including but not limited to SoC, the power requirements of PDN are increasing with increasing integration density and integration complexity.

Fig. 1 shows a block schematic diagram of an exemplary semiconductor device of the present disclosure including a power supply network (PDN). The power supply network (PDN) shown in fig. 1 is fabricated on the same wafer (or Die) as the functional circuits of the semiconductor device, such as logic, analog, and digital circuits. Fig. 1 shows a number of functional blocks (cores), including but not limited to: registers, logic circuits, computing units, communication ports, clock circuits, dynamic random access memories, flash memories, and the like. The solid line in the figure is the power supply line of the PDN, the broken line in the figure is the communication signal connection between the functional devices, and the communication between cores is generally signal interconnection through a Network On Chip (NOC). Each Core is coupled with a low dropout voltage regulator (LDO), the voltage on the power supply line of the PDN is firstly connected into the LDO, the LDO subtracts excessive voltage from the applied input voltage, and the regulated rated output voltage is output to the corresponding Core, so that the stability of the circuit and the system is improved.

In some embodiments, with continued reference to fig. 1, the PDN may also include a direct current-to-direct current voltage converter (DC-to-DC voltage converter) that precludes the use of LDOs to reduce power consumption caused by LDOs direct current voltage drops. In some specific examples, external 1-12V power is provided to the off-chip DC-DC. The off-chip DC-DC converts the input voltage to a 0.5-1V output voltage or lower DC voltage required by the cores directly to the PDN supply lines, which deliver DC low voltages to the respective cores. It will be appreciated that in this case, although there is no voltage drop loss of the LDO, there is a certain voltage drop when the current is transmitted on the PDN power supply line, and this loss is very large in power consumption in the case of a large current.

It can be understood that when the functional devices such as the PDN and the logic circuit are integrated on the same wafer, the PDN and the logic circuit limit the device area mutually, which is not beneficial to the layout design of the PDN and the logic circuit, especially when the logic circuit is powered by the advanced process (less than or equal to 14 nm) involving low feature size and high integration, the device area of the PDN cannot be reduced along with the advanced system Cheng Xiangying, so that the cost of the PDN part in the advanced system process is greatly increased. Meanwhile, as PDN is added on the same wafer, the area of the wafer is increased, and the power supply line of the PDN is prolonged, so that the power transmission heat loss is increased.

Embodiments of the present disclosure propose to provide a logic wafer with a PDN with another wafer, or referred to as an auxiliary wafer, while replacing the original LDO with DC-DC in the on-chip PDN, thereby eliminating the voltage drop power consumption of the LDO. Meanwhile, the voltage on the PDN is increased, so that the current on a power input network of the PDN is reduced, the current on the PDN input network is reduced, the heat loss on a power supply line is reduced, and the PDN provided by the disclosure is formed by connecting PDN unit modules together through a network by utilizing an on-chip distributed DC-DC converter and is uniformly controlled through a central control module. Meanwhile, the DC-DC converter nodes in the PDN can be split and combined according to the power requirement of the Core. Splitting, combining, dynamic control and monitoring of the DC-DC nodes is done by the control network of the PDN.

In some exemplary embodiments, PDN may be designed on a silicon interposer on a package substrate, inside the package substrate, or separately designed on an auxiliary wafer for each functional chip, and then stacked with a bump (bump) electrical connection or a bond Bonding (Hybrid Bonding) connection method and a logic wafer, so as to achieve power supply for each functional Core of the logic chip, thereby forming a novel 3D semiconductor chip heterogeneous integrated architecture of logic plus PDN. The auxiliary wafer is used for supplying power to the logic circuit wafer of the advanced process by utilizing the 3D heterogeneous integration method, so that the technical problem of reducing the integration level of PDN (public data network) constructed on the same wafer can be solved, the method has obvious efficacy advantage, and the method is one of main ways for solving the problem of designing the high-integration-level chip in the latter molar age.

The disclosed embodiments further include a programmable PDN circuit, which can be programmed according to the voltage, current, clock frequency and other parameter requirements of the functional chip or the functional device, to provide better and more stable power supply for the functional chip or the functional device, to improve the universality of the PDN, to complete the topology change of the PDN through programming control, to perform the tuning of the voltage converter on the power supply node and to configure the output combination switch (fig. 4, the plurality of first switches 1261 in the output circuit 126), and to monitor and protect the various operating parameters of the PDN, so as to adapt to the power requirements of the plurality of cores of the logic chip.

Fig. 2 shows a schematic diagram of a semiconductor device (PDN circuit 100) of an embodiment of the present disclosure. Referring to fig. 2, the PDN circuit 100 includes a control circuit 110, and a power conversion circuit 120 coupled to the control circuit 110. Fig. 2 shows, as an example, a plurality of power conversion circuits 120 coupled to one control circuit 110, one control circuit 110 controlling a plurality of power conversion circuits 120, and in other examples, a plurality of power conversion circuits 120 may have other coupling configurations, such as a parallel access to the control circuit 110. The present disclosure is not limited to the number of control circuits 110, power conversion circuits 120, and the manner of coupling.

The power conversion circuits 120 can obtain input power through the power supply lines 140, and perform communication interconnection and clock signal transmission through the communication bus 130. The power supply line 140 may include a plurality of conductive lines, such as an output line, an input line, and further lines not shown in fig. 2, among others. It will be appreciated that in an actual semiconductor device fabrication process, the power supply line 140 may include multiple levels or multiple branch circuit layers on the physical device level, and the constituent materials of the circuit layers may include: conductive materials such as copper, gold, silver, tungsten, aluminum, nickel, chromium, or titanium. As shown in fig. 2, the positive and negative outputs 150 and 160 of the power conversion module 120 are power output terminals that supply power to the cores. Each power conversion module may have multiple pairs of power output terminals as shown in fig. 4.

The communication bus 130 is further coupled to the control circuit 110, and the control circuit 110 monitors and controls the power conversion circuit 120 through the communication bus 130 to perform functions such as state control, voltage control, and cell interconnection. The communication bus 130 is used for transmitting control signals and clock signals. This clock provides the required clock signal for the switching DC-DC converter on the power device.

A semiconductor device (PDN circuit 100) is described in detail with reference to fig. 3 and 4, and includes:

referring to fig. 3, the control circuit 110 includes a central controller 111; the control circuit 110 is coupled to the power conversion circuit 120 and controls the power conversion circuit 120;

referring to fig. 4, the power conversion circuit 120 includes a power controller 121, and a voltage converter 122, a first memory 123, and an analog-to-digital converter 124 coupled thereto; the power controller 121 is configured to control the voltage converter 122 to convert and output a voltage;

analog-to-digital converter 124 is configured to collect the output signal of voltage converter 122 and convert the signal to a programming parameter;

the power controller 121 is configured to receive the programming parameters and transmit the programming parameters to the central controller 111;

the central controller 111 is configured to control the power controller 121 according to programmed parameters.

In some embodiments, referring to fig. 4, the power conversion circuit 120 further includes:

a first memory 123, said first memory 123 being configured to store configuration information for the central controller 111 to control the power controller 121 according to programming parameters. The first memory 123 may be a one-time read only memory (OTP), or otp+sram.

In some embodiments, the voltage converter 122 may be a DC-DC voltage converter, i.e., a direct current-direct current voltage converter.

Specifically, the power conversion circuit 120 shown in fig. 4 is a power input and output functional module of the entire PDN circuit, and its main function includes voltage conversion of an externally input high-voltage dc power supply, voltage stabilization control after voltage reduction, and output of the converted dc power supply to each Core module for power consumption. The voltage converter 122 in the figure may include: a capacitive-switching or inductive DC-DC converter or a combination thereof. It should be noted that the voltage converter 122 in the embodiments of the present disclosure may be inputted with a higher voltage, and the voltage converter 122 may be powered with a higher input voltage, which may reduce heat loss of the input wires, reduce the external power supply line 140, the first conductive via 211 (TSV), the second conductive via 221 (TSV), and the number and width of the leads 250.

The power controller 121 is a control part of the power conversion circuit 120, controls each functional component in the power conversion circuit 120, and is in communication interconnection with the central controller 111 in the control circuit 110, and transmits the programming parameters to be programmed and calculated in the power conversion circuit 120 to the central controller 111, and receives the instruction of the central controller 111, so as to modulate the output voltage of the power conversion circuit 120, so as to achieve more accurate and stable voltage output. In the PDN circuit with multiple power conversion circuits, the central controller 111 may receive the programming parameters from the multiple power controllers 121, coordinate the voltage outputs of the multiple power conversion circuits 120, flexibly allocate the power supply load of the power conversion circuits 120 according to the power supply requirement of the power consumption device, reduce the overload of one power conversion circuit 120 and idle of other power conversion circuits 120, and improve the power supply stability. For a heavy load Core, the central controller 110 may arrange a plurality of power conversion circuits 120 in parallel to power the heavy load Core.

In some embodiments, the power controller 121 may be configured to monitor the voltage converter 122, regulate the output voltage of the DC-DC voltage converter 122, and also control the output switch (the first switch 1261) in the power conversion circuit 120, so as to complete the topology control of the power conversion circuit 120 and the PDN circuit, which is beneficial to the allocation and optimization of the power supply. In this way, the design of the PDN circuit can be simplified, and according to the power consumption requirements of different logic circuits or other power consumption modules, the number of power conversion circuits 120 and the PDN arrangement required by a Core are changed by adjusting the connection of the switches in the output circuit 126, so as to complete the adjustment of the topology structure of the PDN circuit and the optimal power allocation among the cores. When the method is applied to 3D heterogeneous integration, the positions of PDN wafers can be flexibly arranged for different logic wafers or other functional wafers (such as memory wafers), and then the power supply of each part is realized by coupling and interconnection through a TSV technology, as shown in fig. 7 and 8.

The power conversion circuit 120 also includes an analog-to-digital converter 124 (ADC) configured to monitor the real-time operating state of the voltage converter 122. For example, the ADC is coupled to the output circuit 126 of the voltage converter 122, and the ADC is further coupled to the power controller 121, where the ADC captures dynamic and static changes of the output voltage/current of the voltage converter 122, and converts the analog signal into a digital signal specified by the communication protocol for transmission to the power controller 121, and the power controller 121 can process the signal by itself or transmit the signal to the central controller 111 on the control circuit 110 for processing. The digital signal produced by the ADC includes programming parameters including, but not limited to: voltage conversion ratio of DC-DC, output voltage, overvoltage threshold (highest voltage peak), temperature threshold, output switch setting, etc. After the power controller 121 and the central controller 111 receive the programming parameters, they calculate the programming parameters, and then output the configuration parameters to each voltage converter 122 to adjust the voltage conversion ratio and output parameters such as voltage value.

In some embodiments, the programming parameters may be stored in the first memory 123 before the power controller 121 transmits the programming parameters to the central controller 111 to free up communication bandwidth between the central controller 111 and the power controller 121. In other embodiments, after the central controller 111 receives the programming parameters, it may confirm that if they do not match the preset power supply parameters, it will program and debug them, and the debugged configuration parameters will be written into the first memory 123 for quick start and stable power supply of the power conversion circuit 120. By way of example, the first memory 123 may include an OTP memory. The preset power supply parameters may include parameters such as system firmware, upgrade procedure, power on information, power supply voltage range, power supply current range, operating temperature range, voltage conversion frequency, etc., which may be stored in the second memory 112 of the control circuit 110 for the central controller 111 to access and read.

In some embodiments, referring to fig. 3, the control circuit 110 further includes:

a third memory 113 and a second memory 112 coupled to the central controller 111.

The third memory 113 may include a DRAM memory or an SRAM memory, and the second memory 112 may include an OTP memory, for example. The third memory 113 may be used to store control commands from an external host, and may also be used to store programming parameters sent by the power controller 121. The preset power supply parameters may be stored in the second memory 112 or the SRAM memory.

In some embodiments, after the central controller 111 performs programming calculation on the programming parameters, the number of power conversion circuits 120 connected to each power supply node and the output voltage and current of each power conversion circuit 120 can be configured, and each power supply node is coupled with one or more power utilization devices, so that a variable mode of power on a plurality of power supply nodes is realized, the power supply load of each power supply node is adjustable, the increase of the power supply nodes is facilitated, and the flexibility and the universality of the whole PDN circuit are improved.

a temperature sensor 125 coupled to the analog-to-digital converter 124; the temperature sensor 125 is configured to acquire the temperature of the power conversion circuit 120.

The temperature sensor 125 collects real-time temperature of the power conversion circuit 120 and transmits the data to the analog-to-digital converter 124, and the analog-to-digital converter 124 transmits the temperature data and other programming parameters to the power controller 121 for the central controller 111 to perform programming and deployment.

an output circuit 126 coupled to the voltage converter 122 and the power controller 121; wherein the output circuit 126 includes a first terminal 1262 having a first switch 1261, and a second terminal 1263;

the power controller 121 is further configured to control the opening and closing of the first switch 1261;

the first terminal 1262 is configured to interconnect with other power conversion circuits 120;

the second terminal 1263 is configured to be coupled to an output of the output power conversion circuit 120.

In some embodiments, the number of first terminals 1262 is greater than or equal to 1.

In this embodiment, 5 terminals are shown, including 4 first terminals 1262 and one second terminal 1263; each first terminal 1262 has a first switch 1261, the output of the first terminal 1262 is controlled by the on/off of the first switch 1261, the first switches 1261 form multiple switches of the output circuit 126, and the second terminal 1263 may also have a switch. In some embodiments, the output circuit 126 may not include a multi-way switch, which may be integrated in the voltage converter 122, e.g., the second terminal 1262 in fig. 4 may not be coupled to a switch, controlled by a switch in the voltage converter 122. These first terminals 1262 and first switches 1261 provide power-allocating connection architecture for the PDN to flexible the PDN, making dynamic control of the PDN of the chip easy.

The output circuit 126 is coupled to an output terminal of the voltage converter 122, and is used for outputting the voltage modulated by the voltage converter 122, the output circuit 126 is also coupled to the power controller 121, and the power controller 121 controls the voltage output of the output circuit 126 and the switch setting. The output circuit 126 may also be coupled to an ADC that captures configuration parameters of the output circuit 126, such as output switch setting parameters, and converts the configuration parameters into programming parameters for programming by the central controller 111.

As shown in connection with fig. 2, in the PDN circuit to which the plurality of power conversion circuits 120 are coupled, the VDD terminal and GND terminal of each power conversion circuit 120 are coupled to the power supply line 140 and constitute a power supply network. The power supply network also includes an interconnection of clock signals, which are generated by the control circuit 110 and transmitted to the respective power conversion circuits 120 via clock signal lines.

In some embodiments, the control circuit 110 further comprises:

a clock circuit 114 coupled to the central controller 111, the clock circuit 114 configured to generate a clock signal.

In some embodiments, the semiconductor device further comprises:

a clock signal line configured to transmit a clock signal between the control circuit 110 and the power conversion circuit 120.

Referring to fig. 3, in the control circuit 110, the Clock circuit 114 may include a Phase Locked Loop (PLL), an oscillating circuit, etc., and generates a Clock signal of the power conversion circuit 120 according to an instruction of the central controller 111, and transmits the Clock signal to a Clock signal line (Clock Bus) of the power control circuit 110 in fig. 4 through its own Clock signal line (Clock Bus), so as to complete the transmission of the Clock signal. The clock signal output may be multiple paths, each of which may be at a different frequency. The clock signal lines between the control circuit 110 and the power conversion circuit 120 are connected through the communication clock bus 130 shown in fig. 2; the control circuit 110 and the power conversion circuit 120 further include a communication interface (I/O interface), which is also connected through the communication clock bus 130 shown in fig. 2, and is used for transmitting control signals, so as to implement dynamic control (DVFS) of the voltage and frequency of the power conversion circuit 120 in the PDN circuit. By way of example, the communication interface may include a serial two-wire interface (I2C, SPI), while the clock interface may be a single-ended connection.

In some embodiments, referring to fig. 2, the communication interface of the power conversion circuit 120 or the control circuit 110 may be further coupled to an external controller, and the external controller may debug the PDN circuit formed by the control circuit 110 and the power conversion circuit 120 through the communication interface to meet the design criteria. The debugging method is applicable to production tests.

A PDN circuit according to an embodiment of the present disclosure provides a power conversion circuit 120 that may include a communication clock interface, a power controller 121, a voltage converter 122, an ADC, a multi-way switch, a temperature sensor 125, and a first memory 123; through the voltage conversion ratio of ADC conversion, the output voltage, the overvoltage threshold, the temperature threshold, the output switch setting and other programming parameters, and the power controller 121 transmits the programming parameters to the central controller 111 of the control circuit 110, the conversion from high input voltage to low output voltage is completed, the output voltage (current) is detected and regulated, and the stability of power supply is improved. The control circuit 110 receives the programming parameters, changes the number and arrangement modes of the power conversion circuits 120 according to the power consumption requirements of different logic circuits or other power consumption modules, adapts to the topology structures of various PDN circuits, improves the power supply universality of PDNs for the various circuit structures, and simplifies the design of PDNs.

The PDN circuit provided by the embodiments of the present disclosure may be applied to 3D heterogeneous integration, may flexibly arrange the location of the PDN wafer for different logic wafers or other functional wafers (memory wafers),

according to some aspects of embodiments of the present disclosure, there is provided a semiconductor structure, as shown with reference to fig. 5, comprising:

a first semiconductor device 210, the semiconductor device shown in fig. 2, and a first bonding layer including a plurality of first bonding contacts;

a second semiconductor device 220 including a logic circuit, a second bonding layer including a plurality of second bonding contacts; wherein the first bonding layer and the second bonding layer are bonded; the first semiconductor device 210 supplies power to the second semiconductor device 220 through the first bonding contact and the second bonding contact. The first bonding layer and the second bonding layer form a first bonding surface 231 between the first semiconductor device 210 and the second semiconductor device 220 after bonding.

The first semiconductor device 210 includes the PDN circuit 100 shown in fig. 2, which is formed by coupling the control circuit 110 of fig. 3 and the power conversion circuit 120 of fig. 4. The second semiconductor device 220 includes logic circuits or any other functional device requiring power. The control circuit 110 of the PDN may be disposed at the center or at the edge of the first semiconductor device 210.

In some embodiments, a first wafer including a plurality of first semiconductor devices 210 and a second wafer including a plurality of second semiconductor devices 220 may be bonded while bonding. Bonding may include hybrid bonding, the bonding layer including bonding contacts, and an insulating dielectric layer, electrical signal interconnection between the two wafers through the conductive bonding contacts, the insulating dielectric layer providing electrical isolation and a larger bonding surface, improving bonding adhesion. Communication signals of the first semiconductor device 210 and the second semiconductor device 220 are led out to bonding contacts to realize communication interconnection, and voltage of a voltage output terminal (a second terminal 1263 in fig. 4) of the PDN in the first semiconductor device 210 is led out to the first bonding contacts, and power is supplied to the second semiconductor device 220 through the second bonding contacts of the bonding contacts.

In some embodiments, with continued reference to fig. 5, the semiconductor structure further includes:

the first conductive path 211 penetrates the first semiconductor device 210, and the first conductive path 211 is coupled with the second semiconductor device 220.

The first semiconductor device 210 is disposed on the package substrate 200 and coupled to the package substrate 200 through the first conductive balls 241. The second semiconductor device 220 is stacked on the first semiconductor device 210, and a first conductive via 211 (TSV) penetrating the first semiconductor device 210 is provided, and the first conductive via 211 is coupled with the first bonding contact, so that an electrical signal of the second semiconductor device 220 is led out to the first conductive ball 241 to be coupled with the package substrate 200. The package substrate 200 is provided with the second conductive balls 242 on a side where the first semiconductor device 210 is not provided for coupling with an external integrated circuit board. The first semiconductor device 210 may be a PDN wafer and the second semiconductor device 220 may be a logic wafer, with the PDN wafer at the lower end of the logic wafer.

In other embodiments, when the first semiconductor device 210 has stacked multi-layer conductive structures, the first conductive channel 211 may be further coupled to each layer of conductive structures, and each layer of conductive structures may be correspondingly coupled to the output terminals of the plurality of power conversion circuits 120 in the first semiconductor device 210, so as to achieve stable power supply of different voltages of different circuits of the second semiconductor device 220.

In some embodiments, referring to fig. 6, the semiconductor structure further includes a second conductive via 221 (TSV) penetrating the second semiconductor structure, an end of the second conductive via 221 near the first bonding surface 231 is coupled with the second bonding contact, and an end of the second conductive via 221 remote from the first bonding surface 231 is coupled with the package substrate 200 through a wire 250. The first semiconductor device 210 may be a logic wafer and the second semiconductor device may be a PDN wafer, which is on top of the logic wafer.

In some embodiments, referring to fig. 7, the semiconductor structure further comprises:

a third semiconductor device 260 comprising a memory device, a third bonding layer comprising a plurality of third bonding contacts; wherein the third bonding layer is bonded to a fourth bonding layer of the second semiconductor device 220, the fourth bonding layer and the second bonding layer are located in two planes disposed opposite to each other, and the fourth bonding layer includes a plurality of fourth bonding contacts; the third semiconductor device 260 and the second semiconductor device 220 are coupled through a third bonding contact and a fourth bonding contact. The third bonding layer is bonded to the fourth bonding layer to form a second bonding surface 232 between the second semiconductor device 220 and the third semiconductor device 260.

Exemplary memory devices may include, but are not limited to: NAND memory, NOR memory, DRAM memory, SRAM memory, phase change memory, resistance change memory, or the like. For example, the third semiconductor device 260 may be a DRAM wafer, the second semiconductor device 220 may be a logic wafer, and the first semiconductor device 210 may be a PDN wafer.

a second conductive via 221 (TSV), extending through the second semiconductor device 220, the second conductive via 221 (TSV) is coupled to a third semiconductor device 260.

The third semiconductor device 260 is stacked on the second semiconductor device 220, coupled by bonding layer hybrid bonding, and the first semiconductor device 210 is powered by the conductive via TSV and bonding pair to the third semiconductor device 260. It should be noted that the control circuit 110 in the PDN circuit of the first semiconductor device 210 according to the embodiment of the present disclosure may control the different power conversion circuits 120 to supply power to the second semiconductor device 220 and the third semiconductor device 260, respectively. The voltages of the second semiconductor device 220 and the third semiconductor device 260 may be different, and the logic circuits in the second semiconductor device 220 may implement electrical signal interconnection through the bonding surface, thereby implementing access and control to the third semiconductor device 260.

In some embodiments, a plurality of second semiconductor devices 220 may be bonded and coupled to the first semiconductor device 210, and two second semiconductor devices 220 shown in fig. 8 are only examples. In other embodiments, a plurality of third semiconductor devices 260 may also be bonded and coupled to the second semiconductor device 220, which is not limited by the present disclosure.

In some embodiments, the semiconductor structure may further include a third conductive via TSV extending through the third semiconductor device 260, and a fourth semiconductor device may be further bonded on the third semiconductor device 260, the third semiconductor via being used for electrical signal interconnection of the third semiconductor device 260 and the fourth semiconductor device.

The PDN circuit in the first semiconductor device 210 provided in the embodiment of the present disclosure separately supplies power to the second semiconductor device 220 and the third semiconductor device 260 that are stacked, and controls the power conversion circuit 120 to output different clock signals, different voltages and different currents through the control circuit 110 programming of the PDN circuit, so as to adapt to the power supply requirements of different high-density integrated functional devices, improve the universality of the PDN, and improve the device integration level.

In some embodiments, the semiconductor structure further comprises:

a package substrate 200, the package substrate 200 being coupled with the first semiconductor device 210.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, comprising:

a control circuit including a central controller; the control circuit is coupled with the power conversion circuit and controls the power conversion circuit;

2. The semiconductor device according to claim 1, wherein the voltage converter includes: a DC-DC voltage converter.

3. The semiconductor device according to claim 1, wherein the power conversion circuit further comprises:

4. The semiconductor device according to claim 1, wherein the power conversion circuit further comprises:

5. The semiconductor device according to claim 1, wherein the power conversion circuit further comprises:

an output circuit coupled with the voltage converter and the power controller; wherein the output circuit comprises a first terminal having a first switch,

a second terminal;

the first terminal is configured to interconnect with other of the power conversion circuits;

6. The semiconductor device according to claim 5, wherein the number of the first terminals is 1 or more.

7. The semiconductor device according to claim 1, wherein the control circuit further comprises:

a second memory and a third memory coupled to the central controller.

8. The semiconductor device according to claim 1, wherein the control circuit further comprises:

a clock circuit is coupled to the central controller, the clock circuit configured to generate a clock signal.

9. The semiconductor device according to claim 8, wherein the semiconductor device further comprises:

10. A semiconductor structure, comprising:

a first semiconductor device comprising the semiconductor device of any one of the preceding claims 1 to 9, and a first bonding layer comprising a plurality of first bonding contacts;

11. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises:

and a first conductive path extending through the first semiconductor device, the first conductive path being coupled to the second semiconductor device.

12. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises:

13. The semiconductor structure of claim 12, wherein the semiconductor structure further comprises:

14. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises:

and a package substrate coupled with the first semiconductor device.