CN115719739A

CN115719739A - Semiconductor packaging structure and packaging method

Info

Publication number: CN115719739A
Application number: CN202211581601.7A
Authority: CN
Inventors: 刘军; 郝沁汾; 缪富军
Original assignee: Wuxi Core Optical Interconnect Technology Research Institute Co ltd
Current assignee: Wuxi Core Optical Interconnect Technology Research Institute Co ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-02-28

Abstract

The invention discloses a semiconductor packaging structure and a packaging method, which relate to the field of chip packaging, and the technical scheme is as follows: the reconfigurable wafer substrate comprises a reconfigurable wafer substrate and a plurality of functional modules, wherein the reconfigurable wafer substrate comprises a rewiring structure and a plurality of network units; the plurality of functional modules are positioned on one side of the rewiring structure and electrically coupled with the rewiring structure, the plurality of network units are positioned on the other side of the rewiring structure and electrically coupled with the rewiring structure; the functional module comprises a computing module and an external power supply module for supplying power to the computing module and the network unit; the outer sides of the plurality of network units are also provided with plastic packaging materials for packaging the network units; the network unit is internally provided with an on-chip network interconnection channel for realizing non-power signal routing and on-chip communication interconnection, and the functional modules are interconnected through the on-chip network interconnection channel and the rewiring structure of the network unit. The chip of the on-chip system can be flexibly distributed, and the functions of the on-chip system are enriched.

Description

Semiconductor packaging structure and packaging method

Technical Field

The invention relates to the field of chip packaging, in particular to a semiconductor packaging structure and a packaging method.

Background

After the integrated circuit industry enters the post moore's law era, the advanced integrated packaging technology gradually becomes the wave tip of the trend. More than Moore optimizes the system at the system architecture level with advanced encapsulation. A plurality of module chips and an underlying base chip are packaged together by using die-to-die internal interconnection technology to form an SiP chip mode, such as EMIB, coWOS and other technologies. In 2021, the System integration is further expanded to the Wafer by station power accumulation, the on-Wafer System technology of InFO _ SoW (Integrated Fan Out _ System on Wafer) is released, and the WSE (Wafer scale engine) and Tesla products of the United states are released by SoW technology for high-performance artificial intelligence computing systems respectively by Cerebras and Tesla.

The existing on-wafer system structure mainly comprises the following schemes: firstly, a whole wafer with computing chips as a main body is used as a system, and the computing chips are interconnected through an interconnection interface on the wafer to form an on-wafer system (for example, U.S. Pat. No. US10923456B 2); secondly, passive silicon is used as a wafer substrate, and a computing/memory chip is formed into an interconnected system on a wafer through flip chip bonding/hybrid bonding and other modes (taking a paper with DOI number of 10.1109/hpca.2019.00042 as an example); thirdly, the computing chips are reconstructed into a wafer by using the InFO-SoW advanced packaging technology, the interconnection among the chips is completed through reconstruction wiring, and a power supply device and the computing chips are interconnected in a flip-chip mode on the reconstructed wafer to form the whole system on chip (with DOI number being 10.1109/ecc32862.2020.00013).

In the case of the system-on-a-wafer approach, the yield of a single chip is a critical factor of the manufacturing cost, and as the size of the single chip increases, the yield of the single chip is necessarily reduced. Although the damaged chip can be bypassed by redundancy, the cost is high, and different configurations of different systems on a chip are needed. Although the second passive silicon wafer substrate scheme can select KGD (knock-out die) from the calculated core grains through testing, the second passive silicon wafer substrate scheme has the problems of single chip type and single system function; in addition, in order to solve the problems of power supply and heat dissipation of the whole wafer, a large amount of wafer area must be wasted to allocate the VRM (Voltage Regulator Module) area to 1/2 of that of a single system, thereby reducing the utilization rate of the system. Although the third fan-out InFO-SoW solution combines KGD chip integration as a wafer substrate, and flip chip of power supply is mounted on the wafer substrate to meet the requirement of power supply integrity; however, there is a problem that the use of the system on the wafer is relatively simple.

When the above schemes are analyzed, the following two main problems are found to cause the above defects: 1. computing chips, which are a major component of on-chip systems, are mostly used directly to form monolithic structures, which results in all chips being reconstructed together to form a wafer-sized system. In this case, the reconstructed system chip layout has a single fixing function, and cannot meet the requirements of different systems. 2. Similar to the scheme of taking a passive silicon substrate as a support, different application scenes of the system can be achieved by integrally mounting different functional chips; but there are also system power supply configuration problems and a large amount of area must be spent to optimize the power supply.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a semiconductor package structure, which is characterized in that a network-on-chip is formed by network units, so that routing communication between computing modules can be flexibly configured through the network-on-chip, chips of a system-on-chip of the package can be flexibly arranged, chips with different functions can be integrated, and the functions are richer.

In one aspect, the invention provides a semiconductor package structure, which comprises a reconstituted wafer substrate and a plurality of functional modules, wherein the reconstituted wafer substrate comprises a rewiring structure and a plurality of network units; the plurality of functional modules are positioned on one side of the rewiring structure and electrically coupled with the rewiring structure, the plurality of network units are positioned on the other side of the rewiring structure and electrically coupled with the rewiring structure, and plastic package materials are encapsulated outside the plurality of network units; the functional module comprises a computing module and an external power supply module used for supplying power to the computing module and the network unit; the network unit is internally provided with an on-chip network interconnection channel for realizing non-power signal routing and on-chip communication interconnection, and the functional modules are interconnected through the on-chip network interconnection channel and the rewiring structure of the network unit.

By the technical scheme, the network unit is used as a network-on-chip carrier of the system-on-chip, the interconnection among a plurality of network-on-chip units is completed by a rewiring technology, and a computing module interface is provided, so that a plurality of computing modules can realize programmable logic interconnection through a network-on-chip constructed by the network unit, and the computing module and the network unit can be flexibly arranged; modules with different functions, such as a computing module and the like, are arranged outside the reconstructed wafer substrate, so that different functional modules can be integrated by an on-chip system using the packaging structure, and the functions are richer; the on-chip system using the packaging structure can be dispersedly provided with a plurality of external power supply modules, so that the power supply network of the on-chip system is ensured to be uniformly distributed.

Preferably, the external power module comprises a power interface, an external power supply board is inserted into the power interface, and the external power supply board comprises a power connector connected with the power interface and an external power management circuit used for supplying power to the power interface; the external power supply module is also provided with a kernel power supply management circuit used for supplying power to a plurality of computing modules and/or network units arranged around the external power supply module.

Through the technical scheme, the power supply module is integrated on the reconstituted wafer substrate in a vertical interconnection mode and supplies power to different function modules and/or network units in a certain area through short-distance RDL supply on the rewiring structure.

Optionally, the computing module includes a computing device with a computing function and/or a computing device with a computing function and a socket which are inserted into each other to form a whole; the external power supply module comprises a power supply device and/or a whole formed by the power supply device and a socket; the function module also comprises an I/O module used for signal interaction with an external device or a storage module with a storage function; the I/O module comprises an I/O connector and/or a socket and an I/O connector which are plugged into a whole; the memory module comprises a memory device and/or a socket which is integrally formed by splicing the memory device and the socket.

Through the technical scheme, the socket is arranged, so that the quick replacement can be conveniently completed when the functional device is damaged, and the influence on the overall performance of the on-chip system using the packaging structure due to the damage of a single device is avoided.

Preferably, the gap between the network element and the rewiring structure and/or the gap between the functional module and the rewiring structure is filled with an underfill.

Through the technical scheme, for protecting the conductive connecting piece between the rewiring structure and the network unit and/or the functional module and protecting the functional surface of the network unit and/or the functional module, the underfill is filled in the gap between the network unit and/or the functional module and the rewiring structure.

Preferably, the redistribution structure includes a plurality of interconnection structures for interconnecting one or more of the network units and the network units, the network units and the function modules, and the function modules to form the integrated circuit.

Optionally, the interconnect structure includes a pillar interconnect bump penetrating the redistribution structure.

Through the technical scheme, the interconnection structure can comprise multiple forms, and the freedom degree of the circuit layout in the rewiring structure is increased.

Preferably, a plurality of reinforcing ribs for reinforcing the functional module are further arranged; a plurality of through holes are formed in the reconstructed wafer substrate, and the reinforcing ribs penetrate through the through holes and clamp and fix the functional modules.

Through the technical scheme, the reinforcing ribs are arranged to strengthen the fixed connection between the functional devices or the sockets on the functional module and the reconstituted wafer substrate.

In another aspect, the present invention further provides a semiconductor packaging method, including the following steps:

preparing a temporary carrier plate, coating a temporary bonding material on the temporary carrier plate, and forming a rewiring structure on the temporary bonding material through a rewiring process;

mounting the network unit patches on the rewiring structure, and encapsulating all the network units or the network units and the rewiring structure by using a plastic package material in a wafer plastic package mode to form a reconstructed wafer substrate;

removing the temporary carrier plate in a bonding removal mode corresponding to the temporary bonding material, and cleaning the reconstructed wafer substrate to expose the interconnection welding spots on the rewiring structure;

mounting the functional module with the conductive connecting piece on the corresponding interconnection welding points;

the functional module comprises a computing module and an external power supply module.

Preferably, a through hole is formed in a wireless circuit area of the reconstituted wafer substrate; and enabling the reinforcing ribs to penetrate through the through holes and clamping and fixing the computing device and/or the I/O connector and/or the storage device and/or the power supply device and the reconstituted wafer substrate.

Preferably, a through hole is formed in a wireless circuit area of the reconstituted wafer substrate; and enabling the reinforcing ribs to penetrate through the through holes and clamping and fixing the socket and the reconstituted wafer substrate or the functional device and the reconstituted wafer substrate.

Through the technical scheme, the reinforcing ribs are arranged to strengthen the fixed connection between the functional device or the socket on the functional module and the reconstructed wafer substrate.

Drawings

Fig. 1 is a schematic view of a package structure of embodiment 1;

fig. 2 is a schematic view of a package structure with a pillar interconnect structure in embodiment 1;

FIG. 3 is a schematic view showing a structure of embodiment 1 to which an external power supply board is connected;

fig. 4 is a schematic view of a package structure with a stiffener according to embodiment 1;

FIG. 5 is a flowchart of a packaging method of embodiment 2;

fig. 6 is a flowchart of a method of installing reinforcing bars according to embodiment 2.

Reference numerals: 1. reconstructing the wafer substrate; 11. rewiring structures; 111. an interconnecting structure; 1111. a pillar interconnect bump; 12. a network unit; 13. a functional module; 131. a calculation module; 1311. a computing device; 132. connecting the power module; 133. a storage module; 134. an I/O module; 135. a socket; 14. underfill adhesive; 16. plastic packaging material; 17. a conductive connecting member; 18. a through hole; 3. reinforcing ribs; 31. a bolt; 32. a nut; 33. a support member; 4. an external power supply board; 41. a power supply connector; 42. a power supply chip; 43. a plate body; 9. a temporary carrier plate; 91. a temporary bonding material.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. It should be noted that the terms "front," "back," "left," "right," "upper" and "lower" used in the following description refer to directions in the drawings, and the terms "bottom" and "top," "inner" and "outer" refer to directions toward and away from, respectively, the geometric center of a particular component. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

The invention introduces the FPGA/ASIC as a network-on-chip carrier of a system-on-chip, completes the interconnection among hundreds of FPGA/ASIC network-on-chip units 12 by a fan-out (fan-out) Rewiring (RDL) technology and provides an interface of a calculation module 131, so that a plurality of calculation modules 131 realize the programmable logic interconnection among the calculation modules 131 through the network-on-chip constructed by the FPGA/ASIC. The above arrangement enables the routing communication among the computing modules 131 to be flexibly configured through the network on chip, and the chip of the system on chip using the package can be flexibly arranged to freely arrange the module interfaces, thereby realizing different functions and enriching the functions.

While the external power supply will be provided by local vertical interconnects, the power modules may be integrated on the reconstituted wafer substrate 1 and supplied to the different module dies by short-range RDL.

In order to improve the warpage of the whole system and enhance the structural strength of the system, a through hole 18 is added on the reconstructed wafer substrate 1 in a region without a circuit, and a functional device or a socket 135 on the functional surface of the reconstructed wafer substrate 1 is reinforced by a reinforcing rib 3 penetrating through the through hole 18.

The whole on-chip system realizes interconnection among different chips based on reconfigurable chips such as FPGA/ASIC, has expandability and is not limited to single chip application. And the application of the whole on-chip system is more feasible through the optimization of a power supply system.

The above is the core idea of the present application, and based on the embodiments in the present application, a person skilled in the art can obtain all other embodiments without making creative efforts, which belong to the protection scope of the present application. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Example 1

The invention provides a semiconductor packaging structure which comprises a rewiring structure 11, a network unit 12 and a plurality of functional modules 13. The functional modules 13 are located on one side of the rewiring structure 11 and electrically coupled to the rewiring structure 11, the network units 12 are located on the other side of the rewiring structure 11, and the network units 12 are electrically coupled to the rewiring structure 11. As shown in fig. 1, the functional module 13, the rewiring structure 11 and the network unit 12 are sequentially included from top to bottom in the vertical direction.

Specifically, the redistribution structure 11 includes a plurality of interconnect structures 111 for interconnecting one or more of the network unit 12 and the network unit 12, the network unit 12 and the function module 13, and the function module 13 to form an integrated circuit. Interconnect structure 111 may be formed, for example, by creating a plurality of RDL interconnect metal patterns in a plurality of dielectric layers on a semiconductor substrate. The interconnect structure 111 further includes a plurality of under bump metallurgy (not shown) for making external connection to the redistribution structure 11. Therefore, the under bump metallurgy is connected to the network unit 12 or the functional module 13. The underbump metallization may be formed in a similar manner and from a similar material as the RDL interconnect metal pattern. A plurality of conductive connections 17 may be formed on the underbump metallization. The conductive connections 17 may be ball grid array connections, solder balls, metal pillars, controlled collapse die attach bumps, micro bumps, bumps formed by electroless nickel palladium immersion gold techniques, and the like. The conductive connection 17 may also be formed on the functional side of the network element 12 and/or the functional module 13.

In some embodiments, as shown in fig. 2, the interconnect structure 111 may also include a pillar interconnect bump 1111 that extends through the rewiring structure 11, and the pillar interconnect bump 1111 may be formed in a similar manner and from a similar material as the RDL interconnect metal pattern.

The functional modules 13 mainly include a computing module 131 with computing function and an external power module 132. Any of the functional modules 13 is mounted to the under bump metallurgy by the conductive connection member 17 to achieve the electrical coupling of the functional module 13 with the rewiring structure 11. To protect the conductive connection member 17 and the functional surface of the functional module 13, an underfill 14 may be filled in the gap between the functional module 13 and the rewiring structure 11.

The computing module 131 may specifically include a computing device 1311 having a computing function, such as an image processing chip, a DSP chip, a neural network (AI) chip, and a computing chip. These computing devices 1311 with computing capabilities may have SRAM or Flash memory integrated into them.

Functional module 13 may also include an I/O module 134, I/O module 134 for interfacing with external device signals.

In some embodiments, the functional module 13 may further include a memory module 133 having a memory function, and the memory module 133 includes, for example, an HMC device, an HBM device, a DDR device, or the like including a plurality of memory chips. The network element 12 includes an FPGA, an ASIC, and the like. On-chip network interconnection channels are formed in the network unit 12, and the functional modules 13 can realize non-power signal routing and on-chip communication interconnection through the network unit 12 and the data interconnection structure 141 of the rewiring structure 11. The network-on-chip interconnection channel of the network unit 12 is physically fixed and logically software-defined according to application requirements, so as to connect different computing modules 131 and/or storage modules 133 and/or I/O modules 134.

The network elements 12 are connected to the under bump metallization by conductive connections 17 to electrically couple the network elements 12 to the redistribution structure 11. To protect the conductive connections 17 and the functional side of the network elements 12, the gap between the network elements 12 and the redistribution structure 11 is filled with an underfill 14.

A molding compound 16 for encapsulating the network elements 12 is disposed below the rewiring structure 11. In the vertical direction, the molding compound 16 and the sidewall of the redistribution structure 11 may be coplanar or the sidewall of the redistribution structure 11 may be covered by the molding compound 16. The redistribution structure 11, the network unit 12 therebelow, and the molding compound 16 for encapsulating the network unit 12 form a whole, which is the reconstituted wafer substrate 1.

With the network unit 12 as the on-chip network carrier of the system on chip, the interconnection among hundreds of on-chip network units 12 is completed through the rewiring technology, particularly the fan-out RDL technology, and the interface of the calculation module 131 is provided, so that the plurality of calculation modules 131 can realize programmable logic interconnection through the on-chip network constructed by the network unit 12, and the calculation module 131 and the network unit 12 can be flexibly arranged. Modules with different functions, such as the computing module 131, are arranged outside the reconstituted wafer substrate 1, so that different functional modules 13 can be integrated by the on-chip system using the packaging structure, and the functions are richer.

As shown in fig. 3, any external power module 132 is used to supply power to the computing module 131 and the network unit 12 disposed around the external power module 132. The external power module 132 includes a power interface, an external power board 4 is inserted into the power interface, the external power board 4 includes a board 43, and the board 43 is provided with a power connector 41 inserted into the power interface and an external power management circuit for supplying power to the power interface, including an external voltage conversion circuit and a matching circuit (such as a clock circuit and a reset circuit). The plate body 43 of the external power supply plate 4 may further be provided with a power chip 42, and the external power management circuit may be partially or completely integrated in the power chip 42.

The external power module 132 is further provided with a core power management circuit for supplying power to the computing module 131 and/or the network unit 12, including a core voltage conversion circuit and a supporting circuit (such as a clock circuit and a reset circuit). If the functional module 13 further includes the memory module 133, the core power management circuit is also used to supply power to the memory module 133.

The external power module 132 is further provided with an interface power management circuit for supplying power to the I/O module 134, including an interface voltage conversion circuit and supporting circuits (such as a clock circuit and a reset circuit).

The external power module 132 is provided with a power device, and the core power management circuit and the interface power management circuit can be partially or completely integrated in the power device.

In this way, the on-chip system of the package structure is provided with a plurality of external power modules 132 in a distributed manner, so that the power network of the on-chip system is distributed uniformly. The whole power supply scheme of the system is realized by external vertical power supply and on-chip shunt power supply, the area of a power supply processing part on the system is reduced, and the whole utilization rate of the on-chip system using the packaging structure is increased.

The functional module 13 may be a functional device having a corresponding function, or may be a combination of the functional device having a corresponding function and the socket 135. The socket 135 is an electrical interface and a physical interface of the corresponding functional module 13. Specifically, a user of the package structure may install the computing device 1311 in the socket 135 to form a fully functional computing module 131 or an I/O connector in the socket 135 to form a fully functional I/O module 134 or a memory device in the socket 135 to form a fully functional memory module 133. The external power module 132 may also include a power device or an integral part of the power device and the socket 135.

By the arrangement, the rapid replacement of the functional device can be conveniently completed when the functional device is damaged, and the influence on the overall performance of the on-chip system using the packaging structure due to the damage of the single device is avoided.

As shown in fig. 4, a plurality of reinforcing ribs 3 for reinforcing the package structure are further disposed on the package structure, so as to improve the warpage of the whole system and enhance the structural strength of the system. In order to provide the reinforcing ribs 3, a plurality of through holes 18 are formed in the reconstituted wafer substrate 1, and the through holes 18 are distributed in a wireless circuit area on the reconstituted wafer substrate 1. The reinforcing bar 3 may include a bolt 31, a nut 32, and a support member 33, the bolt 31 passing through the through-hole 18, and the nut 32 threadedly coupled to both ends of the bolt 31. The reinforcing ribs 3 can also be other similar mechanical structures which can play a role in clamping and fixing.

Specifically, the reinforcing ribs 3 penetrate through the through holes 18 and are used for reinforcing the functional modules 13 on the wafer substrate 1. The supporting member 33 is disposed between the nut 32 at one end of the bolt 31 and the functional module 13, and the nut 32 at the other end of the bolt 31 abuts against the non-functional surface of the reconstituted wafer substrate 1.

In some embodiments, as shown in fig. 4, the function module 13 includes a device with corresponding function and a socket 135, the stiffener 3 is used to reinforce the socket 135 of the function module 13, the support 33 is disposed between the nut 32 at one end of the bolt 31 and the socket 135, and the nut 32 at the other end of the bolt 31 is abutted against the non-functional surface of the reconstituted wafer substrate 1. As shown in fig. 6, the rib 3 may also be used to reinforce a functional device on the socket 135, the support 33 is disposed between the nut 32 at one end of the bolt 31 and the socket 135, and the nut 32 at the other end of the bolt 31 abuts against the non-functional surface of the reconstituted wafer substrate 1.

Example 2

As shown in fig. 5, the packaging method of the package structure of embodiment 1 includes manufacturing the reconstituted wafer substrate 1, mounting the functional module 13, and mounting the stiffener 3.

The reconstituted wafer substrate 1 comprises the rewiring structure 11 and the network units 12 in the packaging structure of embodiment 1 and a molding compound 16 for encapsulating the network units 12.

The manufacturing of the reconstituted wafer substrate 1 comprises the following steps:

preparation of the rewiring structure 11: a layer of temporary bonding material 91 is applied on the temporary carrier 9. The temporary carrier 9 is typically a silicon wafer or a glass material with a similar coefficient of thermal expansion to silicon, and the temporary bonding material 91 used when using glass as a carrier requires a temporary bonding material that is debonded using a laser of a specific wavelength. The rewiring structure 11 is formed on the temporary bonding material through a rewiring process, specifically, coating, exposing and developing of an organic dielectric layer is performed on the temporary bonding material 91, a required image is obtained, and procedures such as seed layer deposition and electroplating are arranged to obtain an RDL interconnection metal pattern. The RDL interconnection metal pattern has a function of connecting adjacent chips in addition to a function of redistributing signals in the insulating layer.

Encapsulation and reconfiguration network unit 12: and flip-chip mounting the network units 12 with the conductive connecting pieces 17 on the rewiring structure 11 with the RDL interconnection metal patterns, wherein the interconnection between the network units 12 is realized through the RDL interconnection metal patterns, and after the mounting is finished, the underfill 14 can be filled in the gap between the network units 12 and the rewiring structure 11 and dried. After mounting, all the chips are reformed into a whole wafer shape by using a plastic package material 16 in a wafer plastic package manner, so as to form a reformed wafer substrate 1.

Considering the requirements of chip heat dissipation and overall flatness, the reconstituted wafer substrate 1 is thinned and polished to expose the silicon-based non-functional surface of the network unit 12, and a heat conduction interface is formed on the non-functional surface of the reconstituted wafer substrate 1 by sputtering, wherein the heat conduction interface can be a metal layer, and the metal can be high-ductility and high-reliability interface metal such as gold/silver.

Removing the temporary carrier plate 9: the temporary carrier 9 is removed by debonding (which may be thermal or laser debonding) in conformity with the temporary bonding material 91 and the reconstituted wafer is cleaned such that the interconnection pads in the RDL interconnection metal pattern are exposed.

The mounting function module 13 specifically includes the following steps: and the functional module 13 with the conductive connecting piece 17 is attached to the corresponding interconnection welding point of the reconstituted wafer substrate 1 in a functional surface-down mode. In some embodiments, an underfill 14 may be applied to the gap between the functional module 13 and the rewiring structure 11 after mounting.

As shown in fig. 6, the installation of the reinforcing bars 3 specifically includes the following steps: a through hole 18 is formed in the non-circuit area of the reconstituted wafer substrate 1, and the reinforcing rib 3 is inserted through the through hole 18 to clamp and fix the functional module 13 and the reconstituted wafer substrate 1. If the stiffener 3 includes the bolt 31, the nut 32, and the support member 33 as described in embodiment 1, the bolt 31 is made to pass through the through hole 18 and the threads at both ends of the bolt 31 are exposed, the nut 32 is screwed onto one end of the bolt 31 away from the functional module 13, the support member 33 is sleeved on the bolt 31 at the side of the functional module 13, the nut 32 is screwed onto one end of the bolt 31 close to the functional module 13 until the support member 33 abuts against the functional module 13, and the nut 32 at the other end is screwed so that the nut 32 abuts against the reconstituted wafer substrate 1.

In some embodiments, the functional module 13 includes a combination of a functional device and a socket 135, and the mounting of the functional module 13 specifically includes the following steps: the sockets 135 with the conductive connectors 17 are attached to corresponding interconnection pads of the reconstituted wafer substrate 1 and the functional devices are inserted into the sockets 135. To better fix the socket 135, the reinforcing bars 3 are installed after the socket 135 is installed, and the supporting members 33 are abutted against the socket 135. To better secure the functional device, the reinforcing bar 3 is installed after the functional device is inserted into the socket 135, and the supporting member 33 abuts against the functional device.

It should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention.

Claims

1. A semiconductor packaging structure comprises a reconstructed wafer substrate and a plurality of functional modules, wherein the reconstructed wafer substrate comprises a rewiring structure and a plurality of network units; the method is characterized in that: the plurality of functional modules are positioned on one side of the rewiring structure and electrically coupled with the rewiring structure, the plurality of network units are positioned on the other side of the rewiring structure and electrically coupled with the rewiring structure, and plastic package materials are encapsulated outside the plurality of network units; the functional module comprises a computing module and an external power supply module for supplying power to the computing module and the network unit; the network unit is internally provided with an on-chip network interconnection channel for realizing non-power signal routing and on-chip communication interconnection, and the functional modules are interconnected through the on-chip network interconnection channel and the rewiring structure of the network unit.

2. The semiconductor package structure of claim 1, wherein: the external power supply module comprises a power supply interface, an external power supply board is inserted into the power supply interface, and the external power supply board comprises a power supply connector connected with the power supply interface and an external power supply management circuit used for supplying power to the power supply interface; and the external power supply module is also provided with a kernel power supply management circuit for supplying power to a plurality of computing modules and/or network units arranged around the external power supply module.

3. The semiconductor package structure of claim 2, wherein: the computing module comprises a computing device with a computing function and/or a whole formed by splicing the computing device with the computing function and a socket; the external power supply module comprises a power supply device and/or a whole formed by the power supply device and a socket; the functional module also comprises an I/O module used for signal interaction with an external device or a storage module with a storage function; the I/O module comprises an I/O connector and/or a socket and an I/O connector which are plugged into a whole; the storage module comprises a storage device and/or a socket and the storage device are/is connected into a whole in a plugging mode.

4. The semiconductor package structure of claim 1, wherein: and underfill is filled in the gap between the network unit and the rewiring structure and/or the gap between the functional module and the rewiring structure.

5. The semiconductor package structure of claim 1, wherein: the rewiring structure comprises a plurality of interconnection structures which interconnect one or more of the network units and the network units, the network units and the function modules, and the function modules to form the integrated circuit.

6. The semiconductor package structure of claim 5, wherein: the interconnection structure includes a pillar-shaped interconnection bump penetrating the redistribution structure.

7. The semiconductor package structure according to any one of claims 1 to 6, wherein: a plurality of reinforcing ribs for reinforcing the functional module are also arranged; and a plurality of through holes are formed in the reconstructed wafer substrate, and the reinforcing ribs penetrate through the through holes and clamp and fix the functional modules.

8. A semiconductor packaging method for the semiconductor package structure of claims 1-7, comprising the steps of:

removing the temporary carrier plate in a bonding removal mode suitable for the temporary bonding material, and cleaning the reconstructed wafer substrate to expose the interconnection welding spots on the rewiring structure;

and pasting the functional module with the conductive connecting piece on the corresponding interconnection welding points.

9. The semiconductor packaging method according to claim 8, further comprising the steps of:

forming a through hole in a wireless circuit area of the reconstructed wafer substrate;

and enabling the reinforcing ribs to penetrate through the through holes and clamping and fixing the functional module and the reconstructed wafer substrate.

10. A semiconductor packaging method according to claim 9, wherein: further comprising the steps of:

and enabling the reinforcing ribs to penetrate through the through holes and clamping and fixing the socket and the reconstituted wafer substrate or the functional device and the reconstituted wafer substrate.