CN117331422A - Crystal system and power state configuration, feedback and control method thereof - Google Patents

Crystal system and power state configuration, feedback and control method thereof Download PDF

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Publication number
CN117331422A
CN117331422A CN202311134904.9A CN202311134904A CN117331422A CN 117331422 A CN117331422 A CN 117331422A CN 202311134904 A CN202311134904 A CN 202311134904A CN 117331422 A CN117331422 A CN 117331422A
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power state
controller
data
state configuration
slave
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王潇南
丁奕心
郝沁汾
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1443—Transmit or communication errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17318—Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all

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  • Theoretical Computer Science (AREA)
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  • Mathematical Physics (AREA)
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  • Computer Security & Cryptography (AREA)
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Abstract

The invention discloses a system on a crystal and a power state configuration, feedback and control method thereof, which relate to the field of wafer-level processors and have the technical scheme that: the system comprises a main controller and a plurality of slave controllers which are arranged in one-to-one correspondence with the module groups, wherein the main controller is used for acquiring power state configuration data of each module group through an external interface which is in communication connection with the main controller and sending the power state configuration data to the corresponding slave controller, or is used for receiving power state feedback data and sending the power state feedback data through the external interface; the slave controller is used for sending the power state configuration information to the corresponding core particle or receiving the power state feedback information uploaded by the core particle; and the core particle is used for setting the power state according to the power state configuration information or uploading power state feedback information to the slave controller. The method is characterized by being capable of accurately controlling the power state of each core particle of the system on the chip and completing state feedback, safe and convenient, saving the hardware resource expenditure, reducing the system power consumption and improving the efficiency of power state configuration.

Description

Crystal system and power state configuration, feedback and control method thereof
Technical Field
The invention relates to the field of wafer-level processors, in particular to a system on a chip and a power state configuration, feedback and control method thereof.
Background
At present, the number of transistors which can be accommodated in a unit area of a chip is increased, the yield is controlled more and more difficultly, the power consumption problem is more and more prominent, the manufacturing and design cost is exponentially and rapidly increased, and the performance improvement of a single chip is approaching to the extreme. In order to break the boundary condition constraint of the existing large-scale infrastructure system, solve the dilemma of stacking development of the current large-scale infrastructure, and maintain sustainable development of the integrated circuit field in the post-molar age, the system on chip SoC (System on Chip) liter is gradually changed into a research hotspot of the integrated circuit field from the system on chip SoW (System on Wafer) of wafer-level heterogeneous integrated technology.
The on-chip system needs to adapt to different application scenarios, such as: high performance computing, artificial intelligence, data communications, signal processing. The on-chip system components of these application scenarios can be broadly divided into two classes, one class including general-purpose processors such as high-performance computing, artificial intelligence; the other class does not include general purpose processors such as data communication and signal processing. Therefore, core grains with different structures are integrated on a round silicon substrate in a large scale to meet different application scenes. Compared with the traditional single-core or small-scale-level core integration, the basic problems generated by the large-scale core integration are as follows: 1. the large-scale core particles are integrated on the same wafer (the system on the wafer generally contains hundreds of core particles), if the system on the wafer is not controlled, all the power-on starting is performed at the same time, the circuit structure is easily damaged by the surge to generate a short circuit, and therefore all or part of the core particles cannot work normally; 2. the on-chip system can be suitable for different application scenes, so that the required functions are different in different scenes, and if all the core particles are operated at one time each time on the premise of ensuring safe power-on operation, the power consumption is increased without any reason to cause energy waste and performance loss; 3. if the control protocol for the interactive use of the configuration data adopts the traditional IIC, SPI and other bus protocols, the control protocol can face the problems of huge bus quantity and dense bus connection, and when all the core grains are configured by using the traditional bus, each core grain needs to send the configuration signal one by one according to the address, because the quantity of the core grains needing to be configured is large, and the bus transmission rate is low, so that the mode is too low in efficiency. If the JTAG daisy chain bus protocol is adopted, the whole link cannot be controlled correctly once one node in the daisy chain fails due to the influence of the core particle and the yield of the internal circuits of the silicon substrate.
Disclosure of Invention
The first object of the present invention is to provide a system on a chip, which is characterized in that the power state of each core particle of the system on a chip can be precisely controlled and the state feedback can be completed, so that the system is safe and convenient, the hardware resource overhead is saved, the system power consumption is reduced, and the efficiency of power state configuration is improved.
In order to achieve the above purpose, the invention adopts the following technical scheme: a system on a crystal comprises a plurality of module groups and a power supply control component, wherein the module groups comprise a plurality of core grains with the same function; the power supply control assembly comprises a main controller and a plurality of slave controllers which are arranged in one-to-one correspondence with the module groups, wherein the main controller is in communication connection with the plurality of slave controllers through a first communication bus, and each slave controller is in communication connection with each core particle in the corresponding module group; the master controller is used for acquiring power state configuration data of each module group through an external interface in communication connection with the master controller and sending the power state configuration data to a corresponding slave controller, or is used for receiving power state feedback data uploaded by the slave controller of each module group and sending the power state feedback data through the external interface; the slave controller is used for receiving the power state configuration data, acquiring power state configuration information of each core particle in the corresponding module group from the power state configuration data, sending the power state configuration information to the corresponding core particle, or receiving power state feedback information uploaded by the core particle and generating power state feedback data for sending, and uploading the power state feedback data to the master controller; and the core particle is used for receiving the power state configuration information and setting a power state according to the power state configuration information or uploading power state feedback information to the slave controller according to an instruction of the slave controller.
Preferably, the power state configuration information of each core particle in the corresponding module group is compared with the power state feedback information of each core particle one by one from the controller, or the power state configuration information of each core particle in the corresponding module group is compared with the power state configuration information acquired in the previous time one by one, so as to obtain the core particle with the power state needing to be adjusted, and the corresponding power state configuration information is sent to the core particle with the power state needing to be adjusted.
Preferably, the main controller compares the power state configuration data of each module group with the power state configuration data acquired in the previous time one by one, or compares the power state configuration data of each module group with the power state feedback data of each module group one by one, so as to obtain a module group needing to adjust the power state; and the master controller sends corresponding power state configuration data to the slave controllers corresponding to the module groups needing to be adjusted in power state.
Preferably, the first communication bus protocol includes a start bit, a destination address, a read-write flag, a response bit, a data field, a check field and a stop bit, and is used for taking charge of data communication between the master controller and each slave controller; the target address comprises a slave controller address, and the data field comprises power state configuration data or power state feedback data; each of the slave controllers has a unique slave controller address.
The invention further aims to provide a power state configuration method in the system on chip, which is characterized by being capable of completing independent configuration of power states of all cores of the system on chip, being safe and convenient, and improving efficiency of power state configuration.
In order to achieve the above purpose, the invention adopts the following technical scheme: a power state configuration method in a system on a chip is used for configuring the power state of a core particle in the system on a chip, and comprises the following steps: the main controller receives a power state configuration message from an external interface; the main controller analyzes the power state configuration message to obtain power state configuration data; the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; obtaining power state configuration information of core grains in the corresponding module group from the power state configuration data by the controller; transmitting power state configuration information from the controller to the corresponding core particle; the core particle receives the power state configuration information sent from the controller and sets a power state according to the power state configuration information.
Specifically, the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; the method comprises the steps that a master controller sends a start bit and sends target addresses to a slave controller in a serial mode through a first communication bus according to a set sequence; receiving a target address from the controller through the first communication bus, comparing the target address with the local address and sending a response bit; the main controller receives the correct response bit and then prepares to write data, and the main controller writes the power state configuration data into the first communication bus in bit series; the slave controller receives the power state feedback data and transmits a response bit, if the master controller does not receive the correct response bit, the data is retransmitted, if the master controller receives the correct response bit, the master controller calculates a check value and transmits the check value as a check field, and the slave controller calculates the check value, compares the check value with the received check field and transmits the response bit; if the main controller receives the wrong response bit, the data is retransmitted, and if the main controller receives the correct response bit, the main controller sends a stop signal and switches the target address to be sent to the slave controller address corresponding to the next module group; repeating the steps until all the slave controllers in the set sequence receive the power state configuration data.
Specifically, the slave controller obtains the power state configuration information of the core grains in the corresponding module group from the power state configuration data, and the method comprises the following steps: the binary valid portion of the power state configuration data corresponds bit by bit to the power state configuration information of each core in the modular group, and the power state configuration data is parsed bit by bit from the controller to extract the power state configuration information.
The invention also aims to provide a power state feedback method in the system on a chip, which is characterized by being capable of completing feedback of the power state of each core particle of the system on the chip, providing an external object for analysis and decision, being safe and convenient, and improving the efficiency of power state configuration.
In order to achieve the above purpose, the invention adopts the following technical scheme: a power state feedback method in a crystal on system is used for feeding back the power state of a core particle in the crystal on system, and comprises the following steps: uploading power supply state feedback information to the slave controller by the core particle according to the instruction of the slave controller; receiving power state feedback information uploaded by the core particles from the controller; the slave controller generates power state feedback data according to the power state feedback information and stores the power state feedback data into a register; the slave controller uploads the power state feedback data to the master controller, and the master controller receives the power state feedback data uploaded by the slave controllers of the module groups; and the main controller packages the power state feedback data to generate a power state feedback message, and sends the power state feedback message through an external interface according to an external instruction.
Specifically, the slave controller receives the power state feedback information uploaded by the core grains, generates power state feedback data according to the power state feedback information, and stores the power state feedback data in a register, and the slave controller combines the power state feedback information of the core grains in the current module group into the power state feedback data according to a mode that each core grain corresponds to a binary effective part of the power state feedback data bit by bit, and writes the power state feedback data into the register of the slave controller.
Specifically, the slave controller uploads the power state feedback data to the master controller, and the master controller receives the power state feedback data uploaded by the slave controllers of each module group, and specifically includes: the master controller sends a start bit and sends a target address to the slave controller in a serial manner through a first communication bus; receiving a target address from the controller through the first communication bus, comparing the target address with the local address and sending a response bit; the method comprises the steps that after a correct response bit is received by a main controller, data are ready to be read, a slave controller reads power state feedback data in a register, the power state feedback data are written into a first communication bus in series, the main controller receives the power state feedback data and sends the response bit, if the correct response bit is not received by the slave controller, the data are retransmitted, if the correct response bit is received by the slave controller, a check value is calculated by the slave controller and is taken as a check field to be sent, and the check value is calculated by the main controller and is compared with the received check field to send the response bit; the master controller sends a stop signal and switches to the address of the slave controller in the next module group; repeating the steps until all the slave controllers corresponding to the module groups send the power state feedback data according to the set sequence.
The invention further aims to provide a power state control method in the system on a chip, which is characterized by being capable of accurately controlling the power state of each core particle of the system on the chip and completing state feedback, and the method is safe, convenient, saves hardware resource expenditure, reduces system power consumption and improves the efficiency of power state configuration.
In order to achieve the above purpose, the invention adopts the following technical scheme: the power state control method in the on-chip system is used for controlling the power state of the core grain in the on-chip system, and comprises the power state configuration method and the feedback method in the on-chip system, and further comprises the following steps: the main controller receives the power state configuration message, analyzes the power state configuration message to obtain power state configuration data of each module group, and then compares the power state configuration data with the power state configuration data of each module group obtained in the previous time to obtain the power state configuration data of the module group needing to change the power state in the module group; the master controller sends the power state configuration data of the module group needing to change the power state to the corresponding slave controller, and the slave controller receives the power state configuration data; obtaining power state configuration information of core grains in the corresponding module group from the power state configuration data by the controller; transmitting power state configuration information from the controller to the corresponding core particle; the core particle receives the power state configuration information sent from the controller and sets a power state according to the power state configuration information.
Specifically, the power state configuration data is received from the controller, after the power state configuration data is analyzed to obtain the power state configuration information of each core particle, the power state configuration information is compared with the power state configuration information of each core particle obtained in the previous time, and the power state configuration information of the core particle needing to change the power state in the module group is obtained.
The invention has the advantages that (1) the invention can realize the control of the power state of the core particle of the system on the crystal according to the pre-configuration, and the core particle is started not all at once and simultaneously, but is started according to the issued system configuration scheme by taking the module group as a unit. Therefore, the data processing of the power supply state is clearer and easier to encode, meanwhile, the circuit structure is damaged by large current brought by the simultaneous power-on and starting of large-scale core particles can be avoided, the configuration difficulty is reduced, and the method is safe and convenient. (2) The core grain applicable or the core grain not applicable in the scene can be started or closed according to the functional configuration, so that the system on the crystal can provide the best performance with the lowest power consumption, the hardware resource expenditure is saved, and the system power consumption is reduced. (3) The self-defined bus communication mode is introduced in the invention, the data is interacted only between the module group and the main controller in a serial mode, and the communication between the core particles is interacted in the module group in a parallel mode, thereby solving the problems of high line connection density and high processing difficulty caused by dense wiring due to the traditional bus connection and configuration of all the core particles, and simultaneously avoiding the signal crosstalk caused by dense lines. (4) By adding a checking mechanism and a retransmission mechanism in the protocol, the reliability of data transmission is further ensured, and the situation that the configuration result is different from the expected result due to signal inversion caused by transmission line problems or other reasons is avoided. Therefore, the invention provides an efficient and reliable system-on-chip core power state control mode.
Drawings
FIG. 1 is a schematic diagram of a system on a chip according to the present invention;
FIG. 2 is a schematic diagram of a module group of the system on a chip according to the present invention;
FIG. 3 is a first communication bus protocol diagram of the present invention;
FIG. 4 is a flow chart of a power state configuration method of the present invention;
FIG. 5 is a flowchart of step 103 of the power state configuration method of the present invention;
FIG. 6 is a flow chart of a power state feedback method of the present invention;
FIG. 7 is a flowchart of step 304 of the power state feedback method of the present invention;
FIG. 8 is a flow chart of a power state control method of the present invention;
FIG. 9 is a slave controller address list format of the present invention;
FIG. 10 is a table format of a list of addresses of the core in accordance with an embodiment of the present invention;
FIG. 11 is a schematic diagram of a system on a chip according to an embodiment of the invention;
FIG. 12 is a first communication bus protocol diagram according to an embodiment of the present invention;
FIG. 13 is a state machine diagram of a master controller according to an embodiment of the present invention;
FIG. 14 is a timing diagram of a first communication bus according to an embodiment of the present invention;
FIG. 15 is a slave controller state machine diagram of an embodiment of the present invention;
FIG. 16 is a table of addresses of the core particles according to an embodiment of the present invention;
FIG. 17 is a list of slave controller addresses in accordance with an embodiment of the present invention;
FIG. 18 is a schematic diagram showing a power state of the system on chip according to an embodiment of the present invention.
Description of the embodiments
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. It should be noted that the words "front", "back", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "bottom" and "top", "inner" and "outer" refer to directions toward or away from, respectively, the geometric center of a particular component.
The invention provides a system on a crystal, which comprises a plurality of module groups and a power supply control component, as shown in figures 1 and 2, wherein the module groups comprise a plurality of core grains with the same functions. Specifically, each core has a unique core address. The same module group is distributed with the core particles with the same function, so that the efficiency of power management is improved, and the communication processing among the isomorphic core particles is simpler, the data processing is more efficient, and the communication among the heterogeneous core particles does not have the advantage. And the encoding work of the main controller on the power control data can be simplified. And in most cases, the operation mode of the system on a chip is switched (i.e. the power state of each core particle is controlled), one or more types of core particles are always turned on at the same time, or one or more types of core particles are turned off at the same time, i.e. the power of the core particles is controlled according to the types, and only a few cases control part of the similar core particles to be turned on or off.
The power supply control assembly comprises a main controller and a plurality of slave controllers which are arranged in one-to-one correspondence with the module groups, wherein the main controller is in communication connection with the plurality of slave controllers through a first communication bus, and each slave controller is in communication connection with each core particle in the corresponding module group; wherein,
The master controller is used for acquiring the power state configuration data of each module group through an external interface in communication connection with the master controller and sending the power state configuration data to the corresponding slave controller, or is used for receiving the power state feedback data uploaded by the slave controller of each module group and sending the power state feedback data through the external interface. Specifically, the power state configuration data of each module group includes power state configuration information of each core in the module group, and the power state feedback data of each module group includes power state feedback information of each core in the module group. Typically, the on-chip system is equipped with a power supply PCB on which a master control device is provided, which may be built in. The main control equipment is also provided with an external interface which is in communication connection with the main controller, so that the communication between the main controller and an external control host can be realized. Alternatively, the external interface may be connected to an external control host, including but not limited to a proximal serial port or a distal TCP network port. The external application object can input a power state configuration file containing power state configuration data on the external control host, and can display power state feedback data through the external control host to obtain the power state of each module group and the internal core particle thereof in the on-chip system.
It should be noted that, the external use object in the present invention includes, but is not limited to, a user and a computing system. The second communication bus includes a target address, which is a core address of the target core or an address of the slave controller, and an information field including power state configuration information or power state feedback information.
The slave controller is used for receiving the power state configuration data of the corresponding module group, acquiring the power state configuration information of each core particle in the corresponding module group, and sending the power state configuration information to the corresponding core particle, or receiving the power state feedback information uploaded by the core particle, generating power state feedback data, sending the power state feedback data, and uploading the power state feedback data to the master controller. Specifically, the received power state configuration data is disassembled from the controller into power state configuration information of each core particle, and is transmitted to the corresponding core particle. Or the slave controller splices the received power state feedback information into power state feedback information and uploads the power state feedback information to the master controller.
Alternatively, the slave controller may be disposed in one of the cores of its corresponding die set group, with the cores of the slave controller and the other of the die set group disposed The core grains are all in communication connection through a second communication bus so as to realize communication connection between the slave controller and each core grain in the module group. As shown in fig. 2, there are k×m core grains in the module group, and the slave controller is disposed in the core grain 0, and the core grain 0 and the other k×m-1 core grains are respectively connected in communication through the second communication bus. As shown in fig. 1, in the system on a chip of the present invention, the module groups are distributed on the wafer, and the master controller is communicatively connected to the die having the slave controller built in each module group through a first communication bus including one clock line SCL and one data line SDA. The first communication bus further includes a plurality of address lines ADDR. The N address lines ADDR may be at most 2 N The individual core grains provide different addresses.
The power state configuration information is used for representing the power state required by the core particle with different contents, and the content of the power state configuration information can be specifically set according to the actual condition of the power state required by the core particle in actual use. For example, a power state configuration information of "0" indicates that the core is required to be configured to be inactive or in a low power mode; a power state configuration information of "1" indicates that the core is required to be configured to a normal operation mode. Similarly, the power state feedback information is used for representing the power state of the core particle during feedback, and represents the power state fed back by the core particle in different contents, and in actual use, the content of the power state feedback information can be specifically set according to the actual condition of the power state of the core particle during feedback. In this embodiment, the core particle states to be configured, i.e., the inactive mode and the low power consumption mode, are set to correspond to the same power state configuration information content, and because the core particle is in the inactive or low power consumption mode, which is determined by the power supply design of the core particle, the same power supply signal is sent, and the core particle may be in the inactive mode or the low power consumption mode.
The core particle is used for receiving the power state configuration information sent by the slave controller and setting the power state according to the power state configuration information or uploading power state feedback information to the slave controller according to the instruction of the slave controller. Specifically, the core particle can adjust its own power state according to the power state configuration information after receiving the power state configuration information, or can upload its own power state after receiving an instruction from the controller, that is, a power state request signal from the controller. The core particle can be selected as follows: each core particle is provided with a core particle power-on control circuit, and after the core particle power-on control circuit receives the power state configuration information, the core particle power-on control circuit sends a corresponding power enabling signal to a power enabling port of the core particle so that the power state of the core particle is consistent with the required power state displayed by the power state configuration information. For example, if the power enable signal for disabling or reducing the power consumption of the core is "0", the power enable signal for disabling or reducing the power consumption of the core is "1", and the power state configuration information is "0" indicating that the core needs to be configured to be in the disabled or reducing the power consumption mode, the power state configuration information is "1" indicating that the core needs to be configured to be in the normal operation mode, that is, the content of the power state configuration information is consistent with the power enable signal of the core; the power-on control circuit of the core particle sends the power state configuration information to the power enabling port of the core particle, and then the setting of the power state of the core particle can be completed. If the power enable signal for enabling the core particle to be in the non-working or low power consumption mode is '1', the power enable signal for enabling the core particle to be in the normal working mode is '0', the power state configuration information is '0' to indicate that the core particle needs to be configured into the non-working or low power consumption mode, and the power state configuration information is '1' to indicate that the core particle needs to be configured into the normal working mode, namely the content of the power state configuration information is opposite to the power enable signal of the core particle; the core particle power-on control circuit sends an inverted signal of the power state configuration information to the power enabling port of the core particle, and then the setting of the power state of the core particle can be completed. It should be noted that, according to actual requirements, the above-mentioned core particle power-on control circuit may be disposed in the core particle, or may be integrated in the slave controller; those skilled in the art can also implement the above functions using conventional technical means.
The arrangement can accurately control the electrification state of each core particle in the on-chip system, can avoid the problem that all or part of core particles cannot work normally due to the fact that a surge damage circuit structure is generated when all electrification is started at one time, can adaptively set the electrification states of different core particles in the system according to different application scenes, adjusts the power consumption of the whole on-chip system, and reduces unnecessary energy consumption. Meanwhile, the power state of all core particles of the system on the crystal can be fed back for the external use object to make analysis and decision.
Preferably, the power state configuration information of each core particle in the corresponding module group is compared with the power state feedback information of each core particle one by one from the controller, or the power state configuration information of each core particle in the corresponding module group is compared with the power state configuration information acquired in the previous time one by one, so as to obtain the core particle with the power state needing to be adjusted, and the corresponding power state configuration information is sent to the core particle with the power state needing to be adjusted. So configured, the slave controller can derive the core that needs to adjust the power state in two ways. In one mode, the slave controller obtains the core particle needing to adjust the power state by comparing the acquired power state configuration information with the power state feedback information uploaded by the core particle. In another mode, the slave controller obtains the core particle needing to adjust the power state by comparing the power state configuration information acquired at this time or the power state configuration information of the core particle acquired at the previous time. Therefore, the slave controller does not need to send power state configuration information to all the core grains in the module group, and only needs to send configuration information to part of the core grains needing to adjust the current power state to change the power states of the core grains, so that the accurate configuration from the controller to the core grains is realized, the hardware resource overhead is saved, the system power consumption is reduced, and the efficiency of the power state configuration is improved.
Preferably, the master controller compares the power state configuration data of each module group with the power state configuration data acquired in the previous time one by one, or compares the power state configuration data of each module group with the power state feedback data of each module group one by one, so as to obtain a module group needing to adjust the power state, and sends corresponding power state configuration data to the slave controller corresponding to the module group needing to adjust the power state. So configured, the master controller derives the group of modules and the corresponding slave controller that need to adjust the power state in two ways. In one way, the main controller compares the currently acquired power state configuration data with the previously acquired power state configuration data. Alternatively, the master controller compares the currently acquired power state configuration data with the power state feedback data uploaded from the controller. Therefore, the master controller does not need to send power state configuration data to all the slave controllers, and only needs to send configuration data to the slave controllers corresponding to the module groups of which the current power state needs to be adjusted, so that the accurate data transmission from the master controller to the slave controllers is realized, the hardware resource overhead is saved, the system power consumption is reduced, and the efficiency of power state configuration is improved.
Preferably, as shown in fig. 3, the first communication bus protocol includes a start bit, a destination address, a read-write flag, a reply bit, a data field, a check field, and a stop bit, and is used for data communication between the master controller and each slave controller. The target address includes a slave controller address, and the data field includes power state configuration data or power state feedback data, each of the slave controllers having a unique slave controller address. The first communication bus protocol includes a reply mechanism and a check mechanism to ensure that data is properly received from the controller. The response bit is used for ensuring the reliability and correctness of communication between the master controller and the slave controller, the slave controller feeds back the correct response bit after receiving a target address or a data field or a check field, and informs the master controller or the slave controller, if the master controller or the slave controller does not receive a response or receives an error response within a specified time, the master controller or the slave controller starts a retransmission mechanism and repeatedly transmits data, if the preset retransmission times cannot obtain correct response, the core particles are judged to be damaged, and retransmission is ended; if the response is correct, the retransmission is ended. The external use object can read the core particle state table on the main controller through the network to know the working state of the core particle and whether the core particle is damaged or not. The number of bits of the reply bit includes, but is not limited to, one bit. The check field is used for checking the correctness and integrity of data field transmission, and the check field is generated by using a check algorithm, and the adopted check algorithm comprises but is not limited to CRC, MD5 or SHA and the like. After the master controller or the slave controller receives the verification data, the register address and the data content are verified, if the verification result is correct, correct response bits are returned, if the verification result is incorrect, incorrect response bits are returned, the master controller or the slave controller starts a retransmission mechanism after receiving the incorrect response bits, if the response is correct, retransmission is ended, and after the continuous retransmission preset times are failed in verification, retransmission is ended. The custom bus communication mode is introduced, data are interacted only between the module group and the main controller in a serial mode, and the module group is interacted in a parallel mode of inter-core communication, so that the problems of high line connection density and high processing difficulty caused by dense wiring due to the fact that the traditional bus is used for connecting and configuring all cores are solved, and meanwhile, the problem of signal crosstalk caused by dense lines can be avoided.
The invention also provides a power state configuration method in the on-chip system, which is used for configuring the power state of the core particle in the on-chip system, as shown in fig. 4, and comprises the following steps:
step 101: the main controller receives a power state configuration message from an external interface;
step 102: the main controller analyzes the power state configuration message to obtain power state configuration data;
step 103: the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data;
step 104: obtaining power state configuration information of core grains in the corresponding module group from the power state configuration data by the controller;
step 105: transmitting power state configuration information from the controller to the corresponding core particle;
step 106: the core particle receives the power state configuration information sent from the controller and sets the power state according to the power state configuration information.
Specifically, the power state configuration message includes power state configuration data of all the module groups of the on-chip system, and after receiving the power state configuration message from the external interface, the master controller can analyze the power state configuration message to obtain the power state configuration data of each module group, and package and send the power state configuration data to the slave controller corresponding to the module group. The power state configuration data of each module group includes power state configuration information of all the cores in the module group, and the power state configuration information of each core can be extracted from the power state configuration data after the power state configuration data is received from the controller. The slave controller sends the power state configuration information to the corresponding core particle, and the core particle can set the power state of the slave controller according to the power state configuration information after receiving the power state configuration information, so that the power state configuration is completed. The arrangement can accurately control the electrification state of each core particle in the on-chip system, can avoid the problem that all or part of core particles cannot work normally due to the fact that a surge damage circuit structure is generated when all electrification is started at one time, can adaptively set the electrification states of different core particles in the system according to different application scenes, adjusts the power consumption of the whole on-chip system, and reduces unnecessary energy consumption.
Specifically, in step 102, the main controller parses the power configuration message to obtain power configuration data; the method comprises the steps that a master controller searches a module group-slave controller address mapping table, and data of a power supply configuration message are split by taking the module group as a unit to obtain power supply state configuration data of each module group; each of the slave controllers has a unique slave controller address. The corresponding relation between the module group and the corresponding slave controller address is stored in the internal memory of the master controller.
Specifically, as shown in fig. 5, in step 103, the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; in particular to the preparation method of the composite material,
step 201: the master controller sends a start bit and sends a target address to the slave controller in a serial manner through a first communication bus;
step 202: receiving a target address from the controller through the first communication bus, comparing the target address with the local address and sending a response bit;
step 203: the main controller receives the correct response bit and then prepares to write data, and the main controller writes the power state configuration data into the first communication bus in bit series;
Step 204: the slave controller receives the power state feedback data and transmits a response bit, if the master controller does not receive a correct response bit, the data is retransmitted, if the master controller receives a correct response bit, the master controller calculates a check value and transmits the check value as a check field, and the slave controller compares the check value with the received check field and transmits the response bit; if the main controller receives the wrong response bit, the data is retransmitted, and if the main controller receives the correct response bit, the main controller sends a stop signal and switches the target address to be sent to the slave controller address corresponding to the next module group;
step 205: the above steps 201-204 are repeated until all slave controllers in the set order receive the power state configuration data.
As described above, if the master controller does not receive a response or receives an error response within a specified time, the master controller starts a retransmission mechanism and repeatedly transmits data, and if the preset number of retransmissions cannot obtain a correct response, the slave controller or the core particle where the slave controller is located is damaged, and the retransmission is ended; if the response is correct, the retransmission is ended. The external use object can read the core particle state table on the main controller through the network to know the working state of the core particle and whether the core particle is damaged or not. If the verification result is correct, then returning the correct response bit, if the verification result is incorrect, then returning the incorrect response bit, starting a retransmission mechanism after the main controller receives the incorrect response bit, if the main controller responds correctly, ending retransmission, and if the continuous retransmission preset times are all failed in verification, ending retransmission. The order of the setting may be in the order of addresses of the slave controllers, or may be other order specified by the external use object.
Specifically, in step 104, the power state configuration information of the core particles in the corresponding module group is obtained from the power state configuration data by the controller; specifically, the binary valid portion of the power state configuration data corresponds to the power state configuration information of each core particle in the module group bit by bit, and the power state configuration data is analyzed from the controller bit by bit to extract the power state configuration information. The power state configuration data are converted into binary forms, the number of bits of the effective parts in the binary form power state configuration data is the same as the number of core grains in the module group, and each bit of the effective binary form power state configuration data corresponds to the power state configuration information of one core grain respectively. For example, if one module group has No. 0 core, no. 1 core, no. 2 core, no. 3 core, and four cores in total, the power state configuration data is "0101b", the binary valid portion of the power state configuration data is "0101", the power state configuration information of No. 0 core is "1", the power state configuration information of No. 1 core is "0", the power state configuration information of No. 2 core is "1", and the power state configuration information of No. 3 core is "0".
Specifically, step 105 described above, the slave controller transmitting the power state configuration information to the corresponding core particle includes the slave controller transmitting the power state configuration information to the corresponding core particle through the second communication bus.
Specifically, in step 106, the core particle receives the power state configuration information sent from the controller and sets the power state according to the power state configuration information, which includes, as described above, after the core particle power-on control circuit receives the power state configuration information, sending a corresponding power enable signal to the core particle, so that the power state of the core particle is consistent with the required power state displayed by the power state configuration information.
The invention also provides a power state feedback method in the on-chip system, which is used for feeding back the power state of the core particle in the on-chip system, as shown in fig. 6, and comprises the following steps:
step 301: uploading power supply state feedback information to the slave controller by the core particle according to the instruction of the slave controller;
step 302: receiving power state feedback information uploaded by the core particles from the controller;
step 303: the slave controller generates power state feedback data according to the power state feedback information and stores the power state feedback data into a register;
step 304: the slave controller uploads the power state feedback data to the master controller, and the master controller receives the power state feedback data uploaded by the slave controllers of the module groups;
Step 305: and the main controller packages the power state feedback data to generate a power state feedback message, and sends the power state feedback message through an external interface according to an external instruction.
By the arrangement, the power states of all core particles of the system on the crystal can be fed back for the external use object to make analysis and decision.
Specifically, the core particle uploads the power state feedback information to the slave controller according to the instruction of the slave controller, and the method comprises the steps that the slave controller sends feedback request instructions to all core particles of the module group, and each core particle sends the power state feedback information corresponding to the power state during feedback to the slave controller after receiving the feedback instructions. The correspondence of the power state feedback information and the power state is as described above.
Specifically, in the steps 302 and 303, the slave controller receives the power state feedback information uploaded by the core, and generates power state feedback data according to the power state feedback information and stores the power state feedback data in the register; the slave controller combines the power state feedback information of the core grains in the current module group into power state feedback data according to a bit-by-bit corresponding mode of each core grain and a binary effective part of the power state feedback data, and writes the power state feedback data into a register of the slave controller. As described above, for example, there are No. 0, no. 1, no. 2, no. 3, four cores in one module group, the power state feedback information of No. 0 is "1", the power state feedback information of No. 1 is "0", the power state feedback information of No. 2 is "1", the power state feedback information of No. 3 is "0", the binary effective part of the power state feedback data generated by the combination is "0101", and the power state feedback data of the whole module group is "0101b".
Specifically, in step 304, the slave controller uploads the power state feedback data to the master controller, and the master controller receives the power state feedback data uploaded by the slave controller of each module group; as shown in fig. 7, includes:
step 401: the master controller sends a start bit and sends a target address to the slave controller in a serial manner through a first communication bus;
step 402: receiving a target address from the controller through the first communication bus, comparing the target address with the local address and sending a response bit;
step 403: the method comprises the steps that after a correct response bit is received by a main controller, data are ready to be read, a slave controller reads power state feedback data in a register, the power state feedback data are written into a first communication bus in series, the main controller receives the power state feedback data and sends the response bit, if the correct response bit is not received by the slave controller, the data are retransmitted, if the correct response bit is received by the slave controller, a check value is calculated by the slave controller and is taken as a check field to be sent, and the check value is calculated by the main controller and is compared with the received check field to send the response bit;
step 404: the master controller sends a stop signal and switches to the address of the slave controller in the next module group;
Step 405: repeating the steps 401-404 until all the slave controllers corresponding to the module groups send the power state feedback data according to the set sequence.
As described above, if the slave controller does not receive a response or receives an error response within a specified time, starting a retransmission mechanism, repeatedly transmitting data, and if the preset number of retransmissions cannot obtain a correct response, ending retransmission; if the response is correct, the retransmission is ended. If the verification result is correct, then returning the correct response bit, if the verification result is incorrect, then returning the incorrect response bit, starting a retransmission mechanism after receiving the incorrect response bit from the controller, if the response is correct, ending retransmission, and if the continuous retransmission preset times are all failed in verification, ending retransmission. The order of the setting may be in the order of addresses of the slave controllers, or may be other order specified by the external use object.
Specifically, in step 305, the main controller packages the power state feedback data to generate a power state feedback message, and sends the power state feedback message through an external interface according to an external instruction; the method comprises the steps that the main controller combines and packages all power state feedback data sent by the corresponding slave controllers according to a set sequence to generate a power state feedback message.
The invention also provides a power state control method in the on-chip system, which is used for controlling the power state of the core grain in the on-chip system, and comprises the power state configuration method and the feedback method in the on-chip system, as shown in fig. 8, and further comprises the following steps:
step 501: the main controller receives the power state configuration message, analyzes the power state configuration message to obtain power state configuration data of each module group, and then compares the power state configuration data with the power state configuration data of each module group obtained in the previous time to obtain the power state configuration data of the module group needing to change the power state in the module group;
step 502: the master controller sends the power state configuration data of the module group needing to change the power state to the corresponding slave controller, and the slave controller receives the power state configuration data;
step 503: obtaining power state configuration information of core grains in the corresponding module group from the power state configuration data by the controller; transmitting power state configuration information from the controller to the corresponding core particle;
step 504: the core particle receives the power state configuration information sent from the controller and sets a power state according to the power state configuration information.
The main controller receives the power state configuration message, analyzes the power state configuration message to obtain power state configuration data of each module group, and then compares the power state configuration data with the power state configuration data of each module group obtained in the previous time to obtain the power state configuration data of the module group needing to change the power state in the module group; the master controller transmits power state configuration data of a module group requiring a change in power state to a corresponding slave controller, and the slave controller receives the power state configuration data. The method specifically comprises the steps that after a master controller analyzes a power state configuration message to obtain power state data of each module group, the power state configuration data is bound with a unique address of a slave controller corresponding to the module group to generate a slave controller routing list. After receiving the power state feedback data, the master controller can bind the power state feedback data with the unique address of the slave controller corresponding to the module group to generate a slave controller route list. The slave controller routing list format is shown in fig. 9, and the contents include slave controller address, power state data of a modular group, valid-invalid bits. And when the method is initialized, the power state of each core particle in each module group in the slave controller routing list generated by the master controller is set to be 0. After all steps of the configuration method are executed, all steps of the feedback method are executed. The master controller compares the slave controller route list generated by analysis with the slave controller route list generated last time, and if the power state data of the module group are the same, the master controller invalidates the route item by setting the valid-invalid bit of the route item in the slave controller route list generated this time. And after comparing the route items one by one and adjusting the valid-invalid bits, generating a slave controller route list of this time. And setting the target address to be sent by the master controller as the slave controller address of the effective routing item of the slave controller routing list generated at this time, and setting the data field to be sent as the power state configuration data of the module group in the effective routing item of the slave controller routing list generated at this time. The master controller sequentially sends the power state configuration data of the effective routing items of the slave controller routing list generated at this time according to the set sequence until all the slave controllers corresponding to the effective routing items receive the power state configuration data. As described above, the master controller does not need to send the power state configuration data to all the slave controllers, and only needs to send the configuration data to the slave controllers corresponding to the module groups of which the current power state needs to be adjusted, so that the accurate data transmission from the master controller to the slave controllers is realized, the hardware resource overhead is saved, the system power consumption is reduced, and the efficiency of the power state configuration is improved.
Preferably, the power state configuration data is received from the controller, after the power state configuration data is analyzed to obtain the power state configuration information of each core particle, the power state configuration information is compared with the power state configuration information of each core particle acquired in the previous time, and the power state configuration information of the core particle needing to change the power state in the module group is obtained. Specifically, after receiving the power state configuration data from the controller, the power state configuration data is parsed bit by bit and bound with the corresponding core address to form a core routing list. After receiving the power state feedback information from the controller, the power state feedback information and the unique address of the corresponding core particle can be bound to generate a core particle route list. The core routing list format is shown in fig. 10, and the contents include a core address, power state information of the core, and valid-invalid bits. And when the power supply state information of the core particles in the core particle routing list generated by the controller is initialized, the power supply state information of the core particles is set to be 0. And comparing the core particle route list generated by analysis with the core particle route list generated last time by the slave controller, and if the power state information of the core particles is the same, setting the valid-invalid bit of the route item in the core particle route list generated this time, so as to invalidate the route item. And after comparing the route items one by one and adjusting the valid-invalid bits, generating a slave controller route list of this time. And setting a target address to be sent from the controller as a core address of an effective routing item of the generated core routing list, and setting power state configuration information as power state configuration information of the core in the effective routing item of the generated core routing list. And sequentially sending the power state configuration information of the effective routing items of the generated core particle routing list from the controller according to the set sequence until all core particles corresponding to the effective routing items receive the power state configuration information. As described above, the slave controller does not need to send power state configuration information to all the core particles in the module group, and only needs to send configuration information to part of the core particles needing to adjust the current power state to change their power states, so that accurate configuration from the controller to the core particles is realized, hardware resource overhead is saved, system power consumption is reduced, and efficiency of power state configuration is improved.
The above is the core idea of the invention, and based on the embodiments of the invention, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of protection of the present application. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
Specific examples: a system on a wafer, as shown in fig. 11, includes a wafer integrated with a plurality of core particles and a main controller, wherein a circular area in the figure represents the wafer, and 16 die groups are provided on the wafer, and 4 core particles having the same function are provided in each die group. A power supply network (VDD) and a Ground Network (GND) are provided on the wafer, and each core is connected to the power supply network (VDD) and the Ground Network (GND). In the figure, a slave controller is arranged in the core particle 0 of each module group, and the master controller is respectively in communication connection with the core particle 0 with the slave controller in each module group through a first communication bus, namely, 1 clock line (SCL), 1 data line (SDA) and 4 address lines (ADDR) are connected between the master controller and the core particle 0 of each module group.
As shown in fig. 12, in the present embodiment, the protocol of the first communication bus includes a bus message format including a start bit (S), an 8-bit destination address, a one-bit read/write flag (R- : r represents a read signal, ">Representing a write signal), an 8-bit data field, a 4-bit check field, a stop bit (P), and a number of reply bits. The response bit comprises a response signal (A) and a non-response signal (+)>）。
The start bit (S) is a bus communication start flag by which the slave is notified to start communication. When SCL is high, the falling edge of SDA is indicated as a start bit;
8-bit target address: the mode group corresponds to the slave controller one by one, so that the 8-bit target address is set as the slave controller address, that is, the 8-bit target address is set as the register address of the core grain where the slave controller is located. In this embodiment, the slave controller addresses of the 16 slave controllers corresponding to the 16 module groups on the wafer are respectively: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0f.
And (3) reading and writing a mark: and marking the read-write type of the message, if the read-write type is marked as a write signal, writing the corresponding data field into a register address of the core particle where the corresponding slave controller is located, and if the read-write type is marked as a read signal, returning the data in the corresponding register address from the slave controller to the master controller.
8-bit data field: one byte of power state configuration data or power state feedback data may be read and written.
4-bit check field: checking the correctness and integrity of the data field, using a checking algorithm (CRC, SHA or MD5, etc.), respectively calculating the checking result of the data by the master controller or the slave controller, comparing the calculated checking result with the data in the received checking field, if the checking result is correct, then feeding back the correct response bit, otherwise feeding back the wrong response bit.
Stop bit: the slave is notified of the end of communication by this stop bit as a bus communication end flag. When SCL is high, the rising edge of SDA is indicated as a stop bit.
A number of reply bits: "A" or "A-The field indicates a response bit, and after receiving data of one field, the slave controller feeds back a response signal (A) to inform the master controller, if the master controller does not receive a response or receives a non-response signal within a specified time (the slave controller receives the non-response signal within a specified time period)>) And the main controller starts a retransmission mechanism to repeatedly send data, if the data is correctly responded, the retransmission is ended, and if the data cannot be correctly responded for three times (namely, the preset times above), the main controller ends the retransmission and judges that the core particles are damaged.
The main controller is arranged in main control equipment on a power supply PCB (printed circuit board) outside the wafer, and internally comprises a message retransmission logic circuit, a verification algorithm circuit and the like, and the logic function of the main controller mainly comprises a main controller state machine, as shown in figures 13-14.
The master controller state machine includes the following states: IDLE State, ready State, slave_addr State, read_data State, write_data State, check State, calc State, acq_state State, p_state State, 9 states in total.
IDLE state, IDLE state: i.e. the initial state, is responsible for detecting whether a power state configuration message is received or not and analyzing the power state configuration message. In the IDLE state processing logic of the master controller, waiting for a power state configuration message sent to an external interface, after receiving the power state configuration message, starting to analyze the power state configuration message, extracting power state configuration data from the message, binding the power state configuration data with a unique address of a slave controller corresponding to a module group to generate a slave controller route list, comparing the power state configuration data with the power state data of each module group in the slave controller route list generated last time item by item, and if the power state data are the same, invalidating the route item, namely setting the valid-invalid bit of the route item to be 0. In this embodiment, an active-inactive bit of 1 indicates that the routing entry is active, and an active-inactive bit of 0 indicates that the routing entry is inactive. The power state of the core in each module group is represented by 0 and 1, and the destination address to be transmitted is set as the first routing table valid entry, that is, the power state configuration information of the core in each module group is represented by 0 and 1. Setting the target address to be sent as the slave controller address of the first effective routing item, setting the power state data as the resolved first effective routing item, and in the embodiment, configuring the data for the power state corresponding to the first module group, and entering a Ready state, namely a Ready state after completion.
Ready state, ready state: and the data transmission from the master controller to the slave controller corresponding to the target address is started when the write configuration data is started. In the Ready state processing logic of the master controller, a start signal is sent, i.e. SCL, SDA is set high simultaneously, during which SDA is set low. After completion, the state of the transmission destination address, that is, the slave_addr state is entered.
The send target address state is the slave_addr state: is responsible for sending the target address and the read-write flag to the target slave controller. In the slave_addr state processing logic of the master controller, when the SCL is controlled to be pulled down, changing the SDA to be the highest bit 0b of a target address value to be transmitted, pulling the SCL high after the SDA is changed to be unchanged, pulling the SCL low to complete the transmission of the highest bit address, and sequentially completing the transmission of the target address 0x00 in a serial mode according to the method. Case one: when the former state is the Ready state, a one-bit write signal, i.e., (0), is sent as a read-write flag after the destination address is sent. When the main controller receives the response signal (A), the state is switched to a Write DATA state, namely a write_DATA state; if the main controller does not receive the response signal in the slave_addr state, the target address is retransmitted until the response signal is received, or after the retransmission times reach the set times and the response signal is not received, a stop signal (P) is transmitted, at this time, if the current target address is not the address of the last valid route item in the Slave controller route list, the target address to be transmitted is set as the Slave controller address of the valid route item in the next Slave controller route list, the power state configuration data is set as the power state data of the mode group of the valid route item of the next Slave controller route list after analysis, and the Ready state is entered after completion, namely the Ready state. If the current target address is the address of the last valid route item in the slave controller route list, the master controller enters a feedback acquisition State, namely an Acq_State State. And a second case: when the former State is the acq_state State, a one-bit read signal (1) is sent as a read/write flag after the completion of the target address transmission. When the main controller receives the response signal (A), the state is switched to a Read DATA state, namely a read_DATA state, DATA are ready to be Read, and SCL is controlled to switch between high and low levels; if the main controller does not receive the response signal in the slave_addr state, the target address is retransmitted until the response signal is received, or after the retransmission times reach the set times and the response signal is not received, a stop signal (P) is transmitted, at this time, if the current target address is not the address of the last valid route item in the Slave controller route list, the target address to be transmitted is set as the Slave controller address of the valid route item in the next Slave controller route list, the power state configuration data is set as the power state data of the mode group of the valid route item of the next Slave controller route list after analysis, and the Ready state is entered after completion, namely the Ready state. If the current target address is the address of the last valid route item in the slave controller route list, the master controller enters a feedback acquisition State, namely an Acq_State State.
Read DATA state, i.e., read_data state: is responsible for receiving data from the slave controller. In the read_data state processing logic of the main controller, after receiving the DATA field, namely the power state feedback DATA, the main controller sends a response signal (A) and switches the state to a Check state, namely a Check state.
Write DATA state, write_data state: is responsible for transmitting the power state configuration data to the target slave controller. In the write_data state processing logic of the master controller, the SDA is changed to the power state configuration DATA to be sent when SCL is pulled low. And pulling SCL high after SDA change is completed to keep SDA unchanged, and pulling SCL low to complete transmission of the highest address. If the main controller receives the response signal (A), switching to a calculation verification state, namely a Calc state; if the main controller does not receive the response signal (A) in the write_DATA state, the power state configuration DATA are rearranged until the response signal (A) is received, or a stop signal (P) is sent after the number of retransmission reaches the set number and the response signal is not received, at this time, if the current target address is not the address of the last valid route item in the slave controller route list, the target address to be sent is set as the slave controller address of the valid route item in the next slave controller route list, the power state configuration DATA are set as the power state DATA of the mode group of the valid route item of the next slave controller route list after analysis, and the Ready state is entered after completion. If the current target address is the address of the last valid route item in the slave controller route list, the master controller enters a feedback acquisition State, namely an Acq_State State.
Check state is Check state: and the checking module is responsible for checking whether the received check field value is matched with the check value calculated by the check algorithm. In the Check state processing logic of the main controller, the main controller receives the Check field, calculates the received power supply state feedback data according to the same Check algorithm, and calculates the calculated power supply state feedback dataThe check value is compared with the received check field value. If the data is completely matched, the data transmission is correct, and the main controller sends a response signal (A); if the data transmission is not matched, the data transmission generates error codes, and the main controller sends an unacknowledged signal). The master controller receives a stop signal (P), if the current target address is not the address of the last effective routing item in the slave controller routing list, the target address to be sent is set as the slave controller address of the effective routing item in the next slave controller routing list, the power State configuration data is set as the power State configuration data of the module group of the effective routing item of the next slave controller routing list after analysis, and the State is in a continuous configuration State, namely an Acq_State State after completion. If the current target address is the address of the last valid route item in the slave controller route list, the master controller enters a feedback sending State, namely a P_State State.
The calculation state is Calc state: is responsible for calculating the value of the check field from the value of the data field. In the Calc state processing logic of the main controller, a CRC-4/ITU check algorithm is adopted to calculate a check value for the power state configuration data of the data field, namely a check field value, and the check field value is transmitted bit by bit through a serial bus. If the main controller receives the response signal (A), a stop signal (P) is sent, and if the current target address is not the address of the last effective routing item in the routing list of the slave controller, the target address to be sent is set as the slave controller address of the effective routing item in the routing list of the next slave controller, the power state configuration data is set as the power state data of the module group of the effective routing item of the routing list of the next slave controller after analysis, and the Ready state is entered after completion. If the current target address is the address of the last valid route item in the slave controller route list, the master controller enters a feedback acquisition State, namely an Acq_State State. If the main controller receives the unanswered signal @) Return to writing dataThe state is that the write_data state resends the power state configuration DATA, or sends a stop signal (P) after the resending times reach the set times and no response signal is received yet, at this time, if the current target address is not the address of the last valid route item in the slave controller route list, the target address to be sent is set as the slave controller address of the valid route item in the next slave controller route list, the power state configuration DATA is set as the power state DATA of the module group of the valid route item of the next slave controller route list after analysis, and the Ready state is the Ready state after completion. If the current target address is the address of the last valid route item in the slave controller route list, the master controller enters a feedback acquisition State, namely an Acq_State State.
The feedback acquisition State is acq_state: and the data transmission from the master controller to the slave controller corresponding to the target address is started when the feedback data is read. In the acq_state State processing logic of the master controller, the target address to be sent is set as the Slave controller address of the routing item of the Slave controller routing list, then a start signal is sent, namely SCL and SDA are pulled high simultaneously, SDA is pulled down in the period, and the State of the target address is sent to the slave_ADDR State after completion.
Feedback send status, p_state: and packaging the power state feedback data of all the module groups into a message format used for interaction with the outside and sending out the current power state fed back by all the core particles.
The slave controller, located inside the core, has its logic function consisting essentially of a slave controller state machine, as shown in fig. 14-15.
The slave controller state machine includes the following states: IDLE state, read_data state, write_data state, check state, calc state, CTRL state, get_pstate state, 7 states total.
IDLE state: the initial state is responsible for detecting whether the target address, the power state configuration data, the matching target address, the response and the verification are received. The IDLE state processing logic of the slave controller waits for receiving the target address and the Read-Write flag, receives the target address, compares the target address with the local address, and sends a response signal (A signal, namely SDA is pulled down) if the address is matched, and the slave controller is simultaneously switched to a Read DATA state, namely read_DATA state (when the Read-Write flag is 0) or to a Write DATA state, namely write_DATA state (when the Read-Write flag is 1); if the addresses do not match, the IDLE state is maintained. For example, when the target slave of the master is the slave of the module 0, the slave receives the target address through the bus and compares it with the local address, and if the slave in the module 0 is completely matched, the slave in the module 0 transmits the response signal (a) and switches to the read_data state (when the Read/Write flag is 0) or the Write DATA state (when the Read/Write flag is 1) at the same time, and if the other slaves are not matched with the comparison address, the IDLE state is maintained.
Read DATA state, i.e., read_data state: is responsible for receiving the data fields from the host controller. In the read_data state processing logic of the slave controller, after receiving the DATA field, namely the power state configuration DATA, the slave controller stores the DATA field, namely the power state configuration DATA, in a register, simultaneously sends a response signal (A), and switches the state to a Check state, namely a Check state.
Write DATA state, write_data state: is responsible for sending power state configuration data to the host controller. From the controller's write_data state processing logic, the control SCL changes SDA to the power state feedback DATA to be sent when it pulls low. And pulling SCL high after SDA change is completed to keep SDA unchanged, and pulling SCL low to complete transmission of the most significant data. If the response signal (A) is received from the controller, the state is switched to a calculation check state, namely a Calc state; if the slave controller does not receive the reply signal (a) in the write_data state, the power state feedback DATA is retransmitted until the reply signal (a) is received.
Check state is Check state: and the checking module is responsible for checking whether the received check field value is matched with the check value calculated by the check algorithm. In the Check state processing logic of the slave controller, the slave controller receives the Check field and then performs the same Check algorithm After the received power state configuration data is calculated, the calculated check value is compared with the received check field value. If the data is completely matched, the data transmission is proved to be correct, and a response signal (A) is sent from the controller; if the data transmission is not matched, the data transmission generates error codes, and an unacknowledged signal is sent from the controller). The control state, i.e. the CTRL state, is entered after detection of a stop signal (P) from the controller.
The calculation state is Calc state: and is responsible for calculating the value of the check field based on the value of the data field, i.e., the transmitted power state feedback data. And calculating a check value, namely a check field value, from the power state feedback data of the data field by adopting a specific check algorithm (such as CRC, MD5, SHA and other algorithms) in the Calc state processing logic of the controller, and transmitting the check value bit by bit through a serial bus. When the response signal (A) is received from the controller, a stop signal (P) is transmitted, and the controller is switched to an IDLE state, that is, an IDLE state. If no response signal is received from the controller) The power state feedback DATA is retransmitted back to the Write DATA state, i.e., the Write _ DATA state.
Control state, CTRL state: is responsible for setting the power state of each core in the modular group according to the power state configuration data. And in CTRL state processing logic of the controller, each bit of the received power state configuration data corresponds to one core particle in the current module group, the power state configuration data is analyzed into power state configuration information bit by bit, the power state configuration information serving as the power state information of the core particle is bound with a corresponding core particle address to form a core particle route list format of the current module group, the power state of each core particle in the core particle route list generated last time is compared with the power state of each core particle in the core particle route list, if the power state of each core particle is the same, the route item is invalidated, and namely the valid-invalid bit of the route item is set to 0. In this embodiment, an active-inactive bit of 1 indicates that the routing entry is active, and an active-inactive bit of 0 indicates that the routing entry is inactive. And then sending a power state configuration signal to the core particle of the corresponding address through the second communication bus item by item (effective item) according to the routing table to enable the core particle to change the current power state (0: non-working or low-power consumption mode; 1: normal working mode), and switching from the controller state to the get_pstate state after the completion. In this embodiment, the current core routing list format of the slave controller of the module 0 is shown in fig. 16, and each bit of the power status configuration data 1111b corresponds to one core in the current module group.
Acquiring a feedback sending state, namely a get_pstate state: and the power state feedback information of each core particle feedback is acquired, and power state feedback data is formed and written into a register. In the get_pstate state processing logic of the slave controller, the slave controller sends a power state request signal to obtain the current power state of each core particle through a second communication bus according to the effective route item in the current core particle route list, combines the power state feedback information of the core particle in the current module group into power state feedback data according to the bit-by-bit corresponding mode of each core particle and the binary effective part of the power state feedback data, writes the power state feedback data into a register, and returns to the IDLE state from the controller after the completion of the power state feedback data.
In this embodiment, the core particle can adjust its own power state according to the power state configuration information after receiving the power state configuration information, and can upload its own power state after receiving an instruction of the slave controller, that is, a power state request signal of the slave controller.
Assuming that the configuration information of the power supply state of each core of the 16 module groups is {1111b, 1110b, 1100b, 1000b, 1011b, 0011b, 0111b, 0001b, 1111b, 1111b, 1111b, 1111b, 0001b, 0010b, 0100b, 1000b }, the corresponding slave controller routing list is shown in fig. 17. The working manner of this embodiment is as follows.
(1) Initializing, wherein the power state data of each module group in a routing list of a slave controller in a master controller are 0000b and valid invalid bit is 1; the power state information of each core in the core routing list in each slave controller is 0 and the valid invalid bit is 1.
(2) The main controller enters an IDLE state to wait for a power state configuration message sent to an external interface, after receiving the power state configuration message, the main controller starts to analyze the power state configuration message, binds the power state configuration data with a unique address of a slave controller corresponding to a module group to generate a slave controller route list, and compares the power state configuration data with the power state data of each module group in the slave controller route list generated last time item by item, if the power state data are the same, the route item is invalidated, namely the valid-invalid bit of the route item is set to 0. The target address to be sent is set as the slave controller address 0x00 of the first valid routing item, the data field is set as the power state data of the module group of the first valid routing item after parsing, that is, the power state configuration data 1111b corresponding to the first module group in this embodiment, and the Ready state, that is, the Ready state, is entered after completion.
(3) After the master controller enters the Ready state, a start signal is sent, that is, SCL and SDA are set to high level simultaneously, and during this period, SDA is set to low level. After completion, the state of the transmission destination address, that is, the slave_addr state is entered. The slave controller maintains the IDLE state at this time.
(4) After entering the slave_addr state, the master controller controls the SDA to be changed into the highest bit 0b of the target address value to be transmitted when the SCL is pulled down, pulls up the SCL to keep the SDA unchanged after the SDA is changed, and then pulls down the SCL to complete the transmission of the highest bit address, and sequentially transmits the target address 0x00 in a serial mode according to the method. And after the destination address is sent, a one-bit write signal is sent (0). At this time, each slave controller receives the target address through the bus, compares with the local address, and only the slave controller in the module group 0 is completely matched, the slave controller in the module group 0 sends a response signal (A) and is simultaneously switched to a Read DATA state, namely a read_DATA state, and the rest slave controllers ignore to keep the IDLE state when the compared addresses of the slave controllers are not matched.
(5) When the host controller receives the response signal (a), the state is switched to the Write DATA state, i.e., the write_data state, and the power state configuration DATA 1111b of the corresponding mode group is also transmitted in a bit-by-bit serial transmission manner. If the main controller does not receive the response signal (A) in the slave_ADDR state, the target address is retransmitted. When the main controller receives the response signal (A), the state is switched to a calculation check state, namely a Calc state. After receiving the power state configuration DATA 1111b in the read_data state, the slave controller saves it in a register, simultaneously transmits a response signal (a), and switches the state to a Check state, i.e., a Check state.
(6) The host controller calculates the power state configuration data 1111b to have a check field value of 0110b using a CRC-4/ITU check algorithm in the Calc state and transmits it bit by bit over the serial bus. At this time, the slave controller receives the Check field in the Check state, calculates the received power state configuration data according to the same Check algorithm, and compares the calculated Check value with the received Check field value. If the data is completely matched, the data transmission is proved to be correct, and a response signal (A) is sent from the controller; if the data transmission is not matched, the data transmission generates error codes, and an unacknowledged signal is sent from the controller). At this time, the slave controller calculates the check code 0110b from the received power status configuration data 1111b according to the same algorithm, and if the check code 0110b is completely matched, it indicates that the data transmission is correct and the response signal (a) is sent at the same time. If the main controller receives the unacknowledged signal (+)>) The power state data is retransmitted. And after receiving the response signal (A), the main controller sends a stop signal (P). At this time, the master controller sets the target address to be transmitted as the slave controller address of the valid routing item in the next slave controller routing list, i.e. 01, and the power state data is set as the power state data of the module group of the valid routing item in the next slave controller routing list, i.e. 1110b, and enters the Ready state after completion.
(7) After detecting a stop signal (P), the slave controller of the module 0 enters a control state, namely a CTRL state, and the power state configuration data is analyzed into power state configuration information bit by bit, the power state configuration information is used as the power state information of the core particles, the power state configuration information and the corresponding core particle address are bound and shaped into a core particle route list format of the current module group, the core particle route list format is compared with the power state of each core particle in the core particle route list generated last time, if the power states of the core particles are the same, the route item is invalidated, namely the valid-invalid bit of the route item is set to be 0. And then sending a power state configuration signal to the core particle of the corresponding address through the second communication bus item by item (effective item) according to the routing table to enable the core particle to change the current power state, enabling the core particles 1-4 to be set into a normal working mode, and switching from the controller state to the get_pstate state after completion.
(8) In the get_pstate state, the slave controller sends a power state request signal to obtain the current power state of each core particle through the second communication bus according to the effective route item in the current core particle route list, and combines the power state feedback information of the core particle in the current module group into power state feedback data 1111b according to the bit-by-bit corresponding mode (namely, the lowest bit data corresponds to core particle 0 and the highest bit data corresponds to core particle 3) of the binary effective part of the power state feedback data of each core particle, and the power state feedback data is written into a register, and returns to the IDLE state from the controller after the completion.
(9) The main controller repeats steps 3 to 8 until the data transmission of all the module groups is completed, and enters the acq_state State.
(10) In a feedback sending State, namely an Acq_State State, the master controller sets a target address to be sent as an address 0x00 of a Slave controller of a first module group of a first Slave controller routing list, then sends a starting signal, namely SCL and SDA are pulled up simultaneously, SDA is pulled down in the period, and the master controller enters a sending target address State, namely a slave_ADDR State after completion of the SDA; the slave controller maintains the IDLE state at this time.
(11) In the slave_addr state, the master controller controls the SDA to be changed into the highest bit of a target address value to be transmitted when the SCL is pulled down, pulls up the SCL to keep the SDA unchanged after the SDA is changed, then pulls down the SCL to complete the transmission of the highest bit address, sequentially completes the transmission of the target address 0x00 in a serial mode according to the method, and transmits a one-bit read signal (1) after the transmission of the target address is completed; at this time, each slave controller receives the target address through the bus, compares with the local address, and only the slave controllers in the module group 0 are completely matched, the slave controllers in the module group 0 send a response signal (A) and switch to the read DATA state, namely the write_DATA state, at the same time, and the rest slave controllers ignore to keep the IDLE state when the compared addresses of the slave controllers are not matched.
(12) When the main controller receives the response signal (A), the state is switched to the Read DATA state, namely the read_DATA state, so as to prepare for reading DATA, and meanwhile, the SCL is controlled to switch between the high band level and the low band level. The slave controller at address 0x00, after entering the write_data state, reads the value 1111b of the power state feedback DATA held in the register, and modifies the SDA bitwise serial Write bus when SCL is low. When the main controller receives the data, it sends a response signal (A) and switches to Check state. Detecting whether a response signal (A) is received or not by the slave controller, and retransmitting data if the response signal (A) is not received; if the slave controller receives the response signal (A), the slave controller switches to the Calc state.
(13) The slave controller calculates the power configuration data 1111b with a CRC-4/ITU check algorithm in the Calc state to have a check field value of 0110b and transmits it bit by bit via the serial bus. At this time, the slave controller receives the Check field in the Check state, calculates the received power state configuration data according to the same Check algorithm, and compares the calculated Check value with the received Check field value. If the data is completely matched, the data transmission is proved to be correct, and a response signal (A) is sent from the controller; if the data transmission is not matched, the data transmission generates error codes, and an unacknowledged signal is sent from the controller ). If the main controller receives the unacknowledged signal (+)>) The power state data is retransmitted. When the master controller receives the response signal (a), it transmits a stop signal (P), switches the State to the acq_state State, and sets the target address to be transmitted as the address 0x01 of the slave controller of the next module group. The slave controller detects a stop signal and switches the state to the IDLE state.
(14) And repeating the steps 10 to 13 until the power states of all the module groups are updated, switching the states into P_State by the main controller, packaging all the feedback data of the power states of the module groups into a message format for interaction with the outside, and sending out the current power states fed back by all the core particles. After completion, the main controller switches the state to the IDLE state.
After the above 14 steps are completed, the control of the states of all the core particle power supplies in the on-chip system is completed as shown in fig. 18, and the current states of all the core particle power supplies after the configuration according to the preset can be obtained.
In summary, by adopting the system on a chip and the power state configuration, feedback and control method thereof, the starting process of each core particle in the system on the chip can be accurately and efficiently controlled, the problem that large-scale core particles are simultaneously electrified to cause large current to damage a circuit structure is avoided, and the corresponding core particle starting work is accurately controlled according to the starting configuration, so that better performance is provided with smaller power consumption. Meanwhile, the serial bus protocol of the improved version is adopted in addition to the management in a mode of a module group, serial bus communication is only adopted between the main controller and the module group, and high-speed parallel bus communication among core particles is adopted in the module group.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same. While the invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements thereof without departing from the scope of the invention, which is to be encompassed by the appended claims.

Claims (12)

1. A system on a chip, comprising a plurality of module groups and a power control assembly, wherein,
a die set group including a plurality of core particles having the same function;
the power supply control assembly comprises a main controller and a plurality of slave controllers which are arranged in one-to-one correspondence with the module groups, wherein the main controller is in communication connection with the plurality of slave controllers through a first communication bus, and each slave controller is in communication connection with each core particle in the corresponding module group; wherein,
the master controller is used for acquiring the power state configuration data of each module group through an external interface in communication connection with the master controller and sending the power state configuration data to the corresponding slave controller, or is used for receiving the power state feedback data uploaded by the slave controller of each module group and sending the power state feedback data through the external interface;
The slave controller is used for receiving the power state configuration data, acquiring power state configuration information of each core particle in the corresponding module group from the power state configuration data, sending the power state configuration information to the corresponding core particle, or receiving power state feedback information uploaded by the core particle and generating power state feedback data for sending, and uploading the power state feedback data to the master controller;
and the core particle is used for receiving the power state configuration information and setting a power state according to the power state configuration information or uploading power state feedback information to the slave controller according to an instruction of the slave controller.
2. The system on a chip of claim 1, wherein the power state configuration information of each core in the corresponding module group is compared with the power state feedback information of each core one by one from a controller, or the power state configuration information of each core in the corresponding module group is compared with the power state configuration information acquired in the previous time one by one, so as to obtain a core with a power state needing to be adjusted, and the corresponding power state configuration information is sent to the core with the power state needing to be adjusted.
3. The system on a chip of claim 1, wherein the main controller compares the power state configuration data of each module group with the power state configuration data obtained in the previous time one by one, or compares the power state configuration data of each module group with the power state feedback data of each module group one by one, so as to obtain a module group needing to adjust the power state; and the master controller sends corresponding power state configuration data to the slave controllers corresponding to the module groups needing to be adjusted in power state.
4. The system on a chip of claim 1, wherein the first communication bus protocol includes a start bit, a destination address, a read-write flag, a reply bit, a data field, a check field, and a stop bit for taking charge of data communication between the master controller and each slave controller; the target address comprises a slave controller address, and the data field comprises power state configuration data or power state feedback data; each of the slave controllers has a unique slave controller address.
5. A power state configuration method in a system on chip for configuring a power state of a core in the system on chip according to claims 1 to 4, comprising the steps of:
the main controller receives a power state configuration message from an external interface;
the main controller analyzes the power state configuration message to obtain power state configuration data;
the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data;
obtaining power state configuration information of core grains in the corresponding module group from the power state configuration data by the controller;
transmitting power state configuration information from the controller to the corresponding core particle;
The core particle receives the power state configuration information sent from the controller and sets a power state according to the power state configuration information.
6. The power state configuration method of claim 5, wherein the master controller transmits power state configuration data to a corresponding slave controller, and the slave controller receives power state configuration data; the method specifically comprises the following steps:
the master controller sends a start bit and sends a target address to the slave controller in a serial manner through a first communication bus;
receiving a target address from the controller through the first communication bus, comparing the target address with the local address and sending a response bit;
the main controller receives the correct response bit and then prepares to write data, and the main controller writes the power state configuration data into the first communication bus in bit series;
the slave controller receives the power state feedback data and transmits a response bit, if the master controller does not receive the correct response bit, the data is retransmitted, if the master controller receives the correct response bit, the master controller calculates a check value and transmits the check value as a check field, and the slave controller calculates the check value, compares the check value with the received check field and transmits the response bit; if the main controller receives the wrong response bit, the data is retransmitted, and if the main controller receives the correct response bit, the main controller sends a stop signal and switches the target address to be sent to the slave controller address corresponding to the next module group;
Repeating the steps until all the slave controllers in the set sequence receive the power state configuration data.
7. The power state configuration method according to claim 5, wherein the slave controller obtains the power state configuration information of the core grains in the corresponding module group from the power state configuration data, specifically comprising: the binary valid portion of the power state configuration data corresponds bit by bit to the power state configuration information of each core in the modular group, and the power state configuration data is parsed bit by bit from the controller to extract the power state configuration information.
8. A power state feedback method in a system on chip for feeding back the power state of a core particle in the system on chip according to claims 1-4, comprising the steps of:
uploading power supply state feedback information to the slave controller by the core particle according to the instruction of the slave controller;
receiving power state feedback information uploaded by the core particles from the controller;
the slave controller generates power state feedback data according to the power state feedback information and stores the power state feedback data into a register;
the slave controller uploads the power state feedback data to the master controller, and the master controller receives the power state feedback data uploaded by the slave controllers of the module groups;
And the main controller packages the power state feedback data to generate a power state feedback message, and sends the power state feedback message through an external interface according to an external instruction.
9. The power state feedback method of claim 8, wherein the slave controller receives power state feedback information uploaded by the core; the slave controller generates power state feedback data according to the power state feedback information and stores the power state feedback data into a register; the slave controller combines the power state feedback information of the core grains in the current module group into power state feedback data according to a bit-by-bit corresponding mode of each core grain and a binary effective part of the power state feedback data, and writes the power state feedback data into a register of the slave controller.
10. The power state feedback method according to claim 8, wherein the slave controller uploads the power state feedback data to the master controller, and the master controller receives the power state feedback data uploaded by the slave controllers of each module group, and specifically comprises:
the master controller sends a start bit and sends a target address to the slave controller in a serial manner through a first communication bus;
receiving a target address from the controller through the first communication bus, comparing the target address with the local address and sending a response bit;
The method comprises the steps that after a correct response bit is received by a main controller, data are ready to be read, a slave controller reads power state feedback data in a register, the power state feedback data are written into a first communication bus in series, the main controller receives the power state feedback data and sends the response bit, if the correct response bit is not received by the slave controller, the data are retransmitted, if the correct response bit is received by the slave controller, a check value is calculated by the slave controller and is taken as a check field to be sent, and the check value is calculated by the main controller and is compared with the received check field to send the response bit;
the master controller sends a stop signal and switches to the address of the slave controller in the next module group;
repeating the steps until all the slave controllers corresponding to the module groups send the power state feedback data according to the set sequence.
11. A power state control method in a system on a chip, for controlling a power state of a core in the system on a chip according to claims 1 to 4, comprising the above power state configuration method and feedback method in the system on a chip, characterized by further comprising the steps of:
the main controller receives the power state configuration message, analyzes the power state configuration message to obtain power state configuration data of each module group, and then compares the power state configuration data with the power state configuration data of each module group obtained in the previous time to obtain the power state configuration data of the module group needing to change the power state in the module group;
The master controller sends the power state configuration data of the module group needing to change the power state to the corresponding slave controller, and the slave controller receives the power state configuration data;
obtaining power state configuration information of core grains in the corresponding module group from the power state configuration data by the controller; transmitting power state configuration information from the controller to the corresponding core particle;
the core particle receives the power state configuration information sent from the controller and sets a power state according to the power state configuration information.
12. The method according to claim 11, wherein the power state configuration information of each core is obtained by comparing the power state configuration information with the power state configuration information of each core obtained in the previous time after the power state configuration data is received from the controller and analyzed, and the power state configuration information of the core requiring a change in power state in the module group is obtained.
CN202311134904.9A 2023-09-05 2023-09-05 Crystal system and power state configuration, feedback and control method thereof Pending CN117331422A (en)

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