CN116864598A - Light-emitting chip, preparation method and display device - Google Patents
Light-emitting chip, preparation method and display device Download PDFInfo
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- CN116864598A CN116864598A CN202310902003.3A CN202310902003A CN116864598A CN 116864598 A CN116864598 A CN 116864598A CN 202310902003 A CN202310902003 A CN 202310902003A CN 116864598 A CN116864598 A CN 116864598A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The application discloses a light-emitting chip, a preparation method and a display device, and relates to the technical field of light emission. The light-emitting chip comprises a light-emitting array, wherein the light-emitting array realizes the electrical connection among a plurality of light-emitting units through a conductive layer; each light-emitting unit comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer, wherein the first semiconductor layer, the light-emitting layer and the second semiconductor layer are sequentially stacked; the second semiconductor layer has a non-overlapping portion with the light emitting layer; the non-overlapping portion of each of the plurality of light emitting units is respectively in contact with the conductive layer, so that electrical connection among the plurality of light emitting units is realized. The light-emitting chip provided by the application has good reliability and high light-emitting efficiency.
Description
Technical Field
The present application relates to the field of light emitting technologies, and in particular, to a light emitting chip, a manufacturing method thereof, and a display device.
Background
Micro-Led (Micro light emitting diode ) technology, that is, led miniaturization and matrixing technology, refers to a high-density Micro-sized Led array integrated on a chip, for example, an Led display screen, in which each pixel is addressable and individually driven to light, which can be regarded as a miniature version of the Led display screen, and the pixel distance is reduced from millimeter level to micrometer level. In the related art, the yield of the light emitting chip is not high.
Disclosure of Invention
The application provides a light-emitting chip, a preparation method and a display device.
The application provides:
a light emitting chip, comprising:
the light emitting array realizes the electrical connection among a plurality of light emitting units through the conductive layer;
each light-emitting unit comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer, wherein the first semiconductor layer, the light-emitting layer and the second semiconductor layer are sequentially stacked; the second semiconductor layer has a non-overlapping portion with the light emitting layer; the non-overlapping portion of each of the plurality of light emitting units is respectively in contact with the conductive layer, so that electrical connection among the plurality of light emitting units is realized.
In addition, the light emitting chip according to the present application may further have the following additional technical features:
in some embodiments of the application, the conductive layer includes a first electrode layer having one side in contact with a non-overlapping portion of each of the plurality of light emitting cells and a second electrode layer having the other side in contact with the second electrode layer.
In some embodiments of the present application, the surface of the conductive layer is further provided with a light blocking layer, the light blocking layer is disposed on a side of the conductive layer, which is close to the first semiconductor layer, and the light blocking layer is surrounded on a circumferential edge of the light emitting layer, so as to absorb and/or reflect light emitted by the light emitting layer.
In some embodiments of the application, the light blocking layer is a diamond-like film.
In some embodiments of the application, the light blocking layer has a height that is greater than or equal to the height of the light emitting layer.
In some embodiments of the present application, the light emitting unit further includes a first electrode connection layer disposed at a side of the light blocking layer remote from the second semiconductor layer.
The application also provides a preparation method of the light-emitting chip, which comprises the following steps:
providing a light emitting array on a substrate, wherein the light emitting array is provided with a conductive layer and a plurality of light emitting units, and the light emitting units comprise a first semiconductor layer, a light emitting layer and a second semiconductor layer;
the first semiconductor layer, the light-emitting layer and the second semiconductor layer are sequentially stacked, and a non-stacked part of the second semiconductor layer and the light-emitting layer exists; the non-overlapping portion of each of the plurality of light emitting units is respectively in contact with the conductive layer, so that electrical connection among the plurality of light emitting units is realized.
In addition, the preparation method of the light-emitting chip can also have the following additional technical characteristics:
in some embodiments of the present application, the second semiconductor layer, the light emitting layer, and the first semiconductor layer are sequentially grown on the substrate;
etching the first semiconductor layer and the light-emitting layer so as to expose the second semiconductor layer;
and providing a conductive layer on the exposed surface of the second semiconductor layer facing the light-emitting layer.
In some embodiments of the present application, the conductive layer is provided on a side of the second semiconductor layer facing the light emitting layer;
the conductive layer and the second semiconductor layer are etched until the substrate is exposed.
In some embodiments of the application, etching the exposed second semiconductor layer to expose the substrate;
the conductive layer is provided on a side of the second semiconductor layer remaining after etching, which faces the light emitting layer.
In some embodiments of the application, a light blocking layer is disposed on a side of the conductive layer remote from the second semiconductor layer.
In some embodiments of the application, a first electrode connection layer is disposed on a side of the light blocking layer remote from the conductive layer.
The application also provides a display device comprising the light-emitting chip of any embodiment, or the light-emitting chip obtained by the preparation method of the light-emitting chip of any embodiment.
Compared with the related art, the application has the following beneficial effects: according to the light-emitting chip provided by the application, the conductive layer is arranged in the light-emitting units and is connected with the surface of one side, close to the light-emitting layer, of the second semiconductor layer of each light-emitting unit, so that the second semiconductor layers of the light-emitting units are electrically connected, partial or complete failure of the light-emitting chip is prevented, the yield of the light-emitting chip is improved, and the cost of the light-emitting chip is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view showing a structure of a light emitting chip over etched in the related art;
fig. 2 is a schematic diagram showing a structure of a related art light emitting chip after flip-chip over-etching;
FIG. 3 is a schematic diagram showing an initial frame structure of a light emitting chip according to some embodiments of the application;
fig. 4 is a schematic view showing a structure of a light emitting chip in which a first semiconductor layer is formed in some embodiments of the present application;
fig. 5 is a schematic view showing the structure of a light emitting chip in which a second semiconductor layer is formed in some embodiments of the present application;
FIG. 6 is a schematic diagram showing the structure of a light emitting chip provided with a first electrode layer according to some embodiments of the present application;
FIG. 7 is a schematic diagram showing the structure of a light emitting chip provided with a second electrode layer and a light blocking layer according to some embodiments of the present application;
FIG. 8 is a schematic diagram showing the structure of a light emitting chip provided with a passivation layer according to some embodiments of the present application;
FIG. 9 is a schematic diagram showing the structure of a light emitting chip provided with a first electrode connection layer and a third electrode connection layer according to some embodiments of the present application;
FIG. 10 is a schematic diagram showing the structure of a light emitting chip provided with a bonding layer according to some embodiments of the present application;
FIG. 11 is a schematic diagram showing the structure of a light emitting chip after peeling off a substrate and flip-chip mounting in some embodiments of the application;
FIG. 12 is a flowchart showing a process for fabricating a light emitting chip according to some embodiments of the present application;
FIG. 13 is a second flowchart of a method for manufacturing a light emitting chip according to some embodiments of the application.
Description of main reference numerals: 1000-a light emitting chip; 100-a light emitting unit; 110-a first semiconductor layer; 120-a light emitting layer; 130-a second semiconductor layer; 131-non-overlapping portions; 132—a connection face; 140-a conductive layer; 141-a first electrode layer; 142-a light blocking layer; 143-a second electrode layer; 150-a third electrode layer; 160-a first electrode connection layer; 170-a third electrode connection layer; 180-passivation layer; 181-a first contact hole; 182-second contact holes; 190-a bonding layer; 200-substrate; 210-intrinsic semiconductor layer.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
As shown in fig. 1 and 2, in the related art, since the epitaxial layer is composed of a material that is not used, the etching speed is not uniform, which easily causes an over etching condition. As shown in fig. 1, the MESA has been etched to the substrate 200 or the intrinsic semiconductor layer 210 when an over-etch condition occurs. Referring to fig. 2 again, after the flip-chip, the first electrode layer 141 and the second semiconductor layer 130 are separated and insulated by the passivation layer 180, so as to form an open circuit, which results in partial or even complete failure of the light emitting chip 1000.
In view of the above problems, the present application provides a light emitting chip 1000 including a plurality of light emitting units 100 distributed in an array. The light emitting chip 1000 is that a plurality of light emitting units 100 are disposed on the same plane at intervals, the plurality of light emitting units 100 may be distributed in an array or other arrangement, and the plurality of light emitting units 100 may be connected to each other or disposed independently of each other.
As shown in fig. 10, the light emitting unit 100 includes a first semiconductor layer 110, a light emitting layer 120, and a second semiconductor layer 130.
Alternatively, the light emitting unit 100 may be a Micro-led or a Mini-led; the second semiconductor layer 130 may be an N-type semiconductor layer, such as an N-GaN, N-AlGaInP layer; the light emitting layer 120 may be a multiple quantum well light emitting layer; the first semiconductor layer 110 may be a P-type semiconductor layer, such as a P-GaN, P-AlGaInP layer.
As shown in fig. 5, the first semiconductor layer 110, the light emitting layer 120, and the second semiconductor layer 130 are sequentially stacked, wherein the second semiconductor layer 130 has a non-stacked portion 131 with the light emitting layer 120.
In this embodiment mode, the second semiconductor layer 130 is provided in a stepped structure on a side close to the light emitting layer 120, so that the second semiconductor layer 130 of the non-stacked portion 131 portion is left.
In this embodiment, the first electrode layer 141 and the second semiconductor layer 130 may be connected in two ways:
one of them is: the light emitting layer 120 is disposed on the top surface of the second semiconductor layer 130, and the conductive layer 140 is connected to the step surface, i.e., the conductive layer 140 is connected to the non-stacked portion 131.
The other is: the light emitting layer 120 is disposed on the top surface of the second semiconductor layer 130, the second semiconductor layer 130 further has a connection surface 132 connected to the non-stacked portion 131, the connection surface 132 is formed by bending and extending the outer periphery of the non-stacked portion 131 in a direction away from the light emitting layer 120, and the conductive layer 140 is connected to the non-stacked portion 131 and the connection surface 132.
The formation of these two connection modes may be related to the different sequencing of the etching process and the e-beam evaporation process.
The non-overlapping portion 131 of each light emitting unit 100 of the plurality of light emitting units 100 is respectively contacted with the conductive layer 140, so that the electrical connection between the plurality of light emitting units 100 is realized, thus, the structure that the conductive layer 140 connects the two non-overlapping portions 131 of the two adjacent second semiconductor layers 130 is used as an electrical connection basis, the first electrode connection layer 160 is connected on the conductive layer 140, and after the flip-chip is mounted with the driving chip, the light emitting units 100 are connected to form a passage, thereby avoiding the problem that the light emitting chip 1000 is partially or even completely invalid, and improving the reliability of the product.
In some embodiments, conductive layer 140 may comprise a metallic material, in which case conductive layer 140 may be considered a metallic layer. In other embodiments, the conductive layer 140 may also include other conductive materials, such as semiconductor materials, etc.
The non-overlapping portion 131 is an annular surface, and the shape of its outer periphery may be a square, a circle, a polygon, an ellipse, or the like.
As shown in fig. 6, further, the conductive layer 140 includes a first electrode layer 141 and a second electrode layer 143, and the first electrode layer 141 is connected to the non-stacked portion 131. Specifically, one side of the first electrode layer 141 is in contact with the non-stacked portion 131 of each of the plurality of light emitting cells 100, and the other side of the first electrode layer 141 is in contact with the second electrode layer 143.
The first electrode layer 141 is a metal electrode made of Ti/Al/Ti/Au/Ni/Fe/Pt/Pd/Au/Ge, and the first electrode layer 141 forms ohmic contact with the surface of the non-stacked portion 131 to form electrical connection.
Ohmic contact between metal and semiconductor means that there is a pure resistance at the contact and the smaller the resistance the better so that most of the voltage drop is in the active region and not at the contact surface when the assembly is in operation. No potential barrier exists between the metal and the semiconductor, and carriers can smoothly flow into the semiconductor from the metal or flow into the metal from the semiconductor, and the corresponding current-voltage curve is a straight line, so that ohm law is satisfied.
In this way, when the conductive layers 140 between the adjacent two light emitting units 100 are connected, electrical connection can be formed between the second semiconductor layers 130 of the adjacent two light emitting units 100, and thus the second semiconductor layers 130 of the entire light emitting chip 1000 are all connected to form electrical connection.
The metal electrode is generally formed by electron beam vapor deposition, and the first electrode layer 141 is formed by plating a film on the non-stacked portion 131, which makes the thickness of the first electrode layer 141 limited, and there is a risk that adjacent first electrode layers 141 cannot abut against each other to form an electrical connection.
Therefore, in the present application, as shown in fig. 7, a light blocking layer 142 is further disposed on the surface of the conductive layer 140, and the light blocking layer 142 is disposed on the side of the first electrode layer 141 near the first semiconductor layer 110.
As shown in fig. 7, the second electrode layer 143 has conductive properties, and the second electrode layer 143 is a metal film or a diamond-like film, for example. In the present embodiment, the second electrode layer 143 is a diamond-like film, and the light blocking layer 142 is also a diamond-like film, so that the second electrode layer 143 and the light blocking layer 142 can be manufactured simultaneously and integrally, and the number of processing steps can be reduced, and the production efficiency can be improved.
It can be understood that when the second electrode layer 143 is a metal film, the second electrode layer 143 and the first electrode layer 141 are synchronously manufactured and integrally arranged, and the thickness of the conductive layer 140 is increased, so that the electrical connection structure between the plurality of light emitting units 100 is more stable.
Optionally, the conductive layer 140 disposed on the second semiconductor layer 130 is disposed around the circumferential edge of the light emitting unit 100, the non-stacked portion 131 of each light emitting unit 100 in the plurality of light emitting units 100 is respectively in contact with the conductive layer 140, so as to realize electrical connection between the plurality of light emitting units 100, so that the plurality of light emitting units 100 share one conductive layer 140, the second semiconductor layers 130 of the plurality of light emitting units 100 are connected by the conductive layer 140 to form a whole with uniform conductivity, and when the light emitting units 100 are in use, only the potential of the third electrode layer 150 connected with the first semiconductor layer 110 on each light emitting unit 100 needs to be controlled, so that the corresponding light emitting unit 100 can be controlled to be turned on, thereby improving the density of the pixels of the light emitting chip 1000 and the area of the light emitting region.
Meanwhile, the light blocking layer 142 is disposed on a side of the first electrode layer 141 near the first semiconductor layer 110, and the light blocking layer 142 is electrically connected to the first electrode layers 141 on the two adjacent light emitting units 100. In this way, the risk that the adjacent first electrode layers 141 cannot abut can be avoided, and stable electrical connection can be formed between the two first electrode connection layers 160 of the adjacent two light emitting units 100.
The third electrode layer 150 is a metal electrode made of Ti/Al/Ti/Au/Ni/Fe/Pt/Pd/Au/Ge.
The inventor also found that the proportion of the lateral light emitted by the Micro-LED chip becomes larger as the chip size is reduced, especially in the case that the Micro-LED chip size is reduced to 10um×10um or less, the lateral light emitted by adjacent Micro-LED chips on the display panel will interfere with each other, thereby forming a light crosstalk phenomenon, and the problem that the screen image becomes blurred.
In view of the above, in the embodiment of the present application, as shown in fig. 7, a light blocking layer 142 is disposed around the circumferential edge of the light emitting layer 120 to absorb and/or reflect the light emitted from the light emitting layer 120. The light blocking layer 142 has a height greater than or equal to the height of the light emitting layer 120.
In other words, in the direction in which the second semiconductor layer 130 is directed toward the first semiconductor layer 110, the side surface of the light blocking layer 142 close to the first semiconductor layer 110 is flush with the side surface of the first semiconductor layer 110 close to the light emitting layer 120; or a side surface of the light blocking layer 142 adjacent to the first semiconductor layer 110 exceeds a side surface of the first semiconductor layer 110 adjacent to the light emitting layer 120. In this way, the light emitted from the light emitting layer 120 of the light emitting unit 100 can be emitted from the direction perpendicular to the light emitting layer 120, and the remaining light is absorbed and/or reflected by the conductive layer 140, thereby avoiding the light crosstalk phenomenon and improving the definition and resolution of the light emitting chip 1000.
More specifically, the light blocking layer 142 is disposed around the circumferential edge of the light emitting layer 120 and spaced from the light blocking layer 142, so as to avoid the contact between the conductive layer 140 and at least two layers of the light emitting unit 100, thereby avoiding a short circuit.
Meanwhile, one end of the light blocking layer 142 is connected to the first electrode layer 141, and the other end of the light blocking layer 142 is flush with a surface of the first semiconductor layer 110, which is close to the light emitting layer 120; or the other end of the light blocking layer 142 exceeds a side surface of the first semiconductor layer 110 near the light emitting layer 120. Thus, the light-emitting layer 120 absorbs/reflects light from the side surface by the light-blocking layer 142, thereby achieving the purpose of preventing light crosstalk.
In this embodiment, the light blocking layer 142 is diamond-like or a metal material with a certain reflectivity. The diamond-like carbon film (DLC, diamond like carbon) has the advantages of high hardness, low friction coefficient, excellent film compactness, good chemical stability, good optical properties, and the like. The diamond-like film can be deposited by a chemical vapor deposition method, and parameters such as power, air pressure, chemical gas, flow, size and the like during the growth of the diamond-like film can be changed, so that the absorptivity of the diamond-like film to light is changed, and the phenomenon of light crosstalk is further regulated. In addition, the light blocking layer 142 may be a metal material with a certain reflectivity, such as gold, silver, copper, aluminum, molybdenum, and other metal materials with high reflectivity.
The diamond-like carbon may absorb light emitted from the light emitting layer 120, thereby reducing the problem of optical crosstalk between adjacent two light emitting cells 100.
Meanwhile, the diamond-like carbon has conductivity, and on the basis of this, the combined light emitting unit 100 further includes a first electrode connection layer 160, and the first electrode connection layer 160 is disposed on a side of the light blocking layer 142 away from the second semiconductor layer 130. Thus, the first electrode connection layer 160 is electrically connected to the diamond-like carbon.
More preferably, the surface of the light blocking layer 142 near the first semiconductor layer 110 exceeds the surface of the first semiconductor layer 110 near the light emitting layer 120 to be flush with the surface of the first semiconductor layer 110 far from the light emitting layer 120, so that the position of the first electrode connection layer 160 is raised, and after the flip-chip, the first electrode connection layer 160 is close to the third electrode layer 150 connected to the first semiconductor layer 110, thereby improving the contact performance between the first electrode connection layer 160 and the bonding layer 190 and increasing the product yield.
Specifically, the conductive layer 140 is disposed around the circumferential edge of the light emitting layer 120 and is in contact with the second semiconductor layer 130, so that the conductive layer 140 and the light emitting unit 100 do not need to be fixed by the substrate 200, and the substrate 200 can be peeled off, so that light is prevented from propagating between adjacent light emitting units 100 through the substrate 200, and further, the phenomenon of optical crosstalk is improved.
As shown in fig. 8 to 11, the light emitting unit 100 further has a third electrode layer 150, a passivation layer 180, a first electrode connection layer 160, a third electrode connection layer 170, and a bonding layer 190.
The third electrode layer 150 is disposed on a side of the first semiconductor layer 110 away from the light emitting layer 120, and the third electrode connection layer 170 is disposed on a side of the third electrode layer 150 away from the first semiconductor layer 110. The first electrode connection layer 160 and the third electrode connection layer 170 are each made of metal, such as titanium, aluminum, gold, or the like.
The passivation layer 180 covers the light emitting chip 1000, a first contact hole 181 communicated with the first electrode connection layer 160 and a second contact hole 182 communicated with the third electrode connection layer 170 are respectively formed in the passivation layer 180, the first contact hole 181 and the second contact hole 182 are respectively provided with the first electrode connection layer 160 and the third electrode connection layer 170, and the bonding layers 190 are respectively arranged on the passivation layer 180 and are respectively connected with the first electrode connection layer 160 and the third electrode connection layer 170 in a one-to-one correspondence manner.
In some embodiments, the passivation layer 180 may be covered by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method on the light emitting chip 1000, thereby protecting the internal structure of the light emitting chip 1000 from oxygen, moisture, dust, etc. affecting the performance of the light emitting chip 1000 by the passivation layer 180.
In other embodiments, the passivation layer 180 may be coated on the light emitting chip 1000, so that the passivation layer 180 protects the internal structure of the light emitting chip 1000 from oxygen, moisture, dust, etc. affecting the performance of the light emitting chip 1000. The passivation layer 180 may be an insulating photoresist, such as PFA photoresist, or the like.
The passivation layer 180 may be filled in the gaps between the light blocking layer 142 and the light emitting layer 120, the first semiconductor layer 110, and the second semiconductor layer 130, thereby further improving the insulation and the stability of the light emitting unit 100.
In some embodiments, the bonding layer 190 is filled in the first contact hole 181 and the second contact hole 182 by thermal evaporation or electron beam evaporation, respectively, so that when the light emitting chip 1000 is bonded with the driving chip, the third electrode connection layer 170 and the first electrode connection layer 160 can be respectively conducted with the pad of the driving chip through the bonding layer 190. The bonding layer 190 may be made of a metal with a lower melting point, such as indium, and the indium metal is heated by reflow soldering, so that the indium metal is melted to be spherical, and is convenient to be soldered and bonded with the bonding pad of the driving chip.
Since the light blocking layer 142 is elevated above the first electrode connection layer 160, the horizontal heights of the positions of the first electrode connection layer 160 and the third electrode connection layer 170 are substantially flush, thereby improving the generation efficiency of the bonding layer 190.
As shown in fig. 12, the present application further provides a method for manufacturing a light emitting chip 1000, including:
step S100: a plurality of light emitting units 100 are disposed on the substrate 200, the plurality of light emitting units 100 are distributed in an array, and the light emitting units 100 include a first semiconductor layer 110, a light emitting layer 120, a second semiconductor layer 130, and a conductive layer 140, wherein the first semiconductor layer 110, the light emitting layer 120, and the second semiconductor layer 130 are sequentially stacked.
Specifically, as shown in fig. 3 and 4, a plurality of light emitting units 100 are formed in such a manner that a second semiconductor layer 130, a light emitting layer 120, and a first semiconductor layer 110 are sequentially disposed on a substrate 200 in a self-preparable manner, thereby obtaining a light emitting chip 1000. The light emitting chip 1000 may also be obtained by purchasing an epitaxial wafer including the substrate 200 and the light emitting unit 100, which has been prepared in advance. The intrinsic semiconductor layer 210 may be disposed on the substrate 200, and then the first semiconductor layer 110 may be disposed on the intrinsic semiconductor layer 210, and the intrinsic semiconductor layer 210 is a pure semiconductor completely free of impurities and lattice defects, so that the manufacturing quality of the light emitting chip 1000 may be ensured.
The conductive layer 140 is connected to the second semiconductor layer 130, and the conductive layer 140 connects each light emitting unit 100, thereby connecting the second semiconductor layers 130 of the plurality of light emitting units 100 as one electrically connected whole.
Step S200: the first semiconductor layer 110, the light emitting layer 120 are etched so that the second semiconductor layer 130 is exposed.
Specifically, on the substrate 200, the first semiconductor layer 110 and the second semiconductor layer 130 of the light emitting unit 100 are fabricated by etching gallium nitride or AlInGAP to prepare the third electrode layer 150 and the first electrode layer 141 for the subsequent electron beam evaporation.
In some embodiments, the first semiconductor layer 110 may include a P-type semiconductor material, and the second semiconductor layer 130 may include an N-type semiconductor material, where the light emitting chip 1000 is of a common N-pole structure.
In some embodiments, the first semiconductor layer 110 may include an N-type semiconductor material, and the second semiconductor layer 130 may include a P-type semiconductor material, where the light emitting chip is of a common P-pole structure. In practice, a Mesa etch may be used.
In this embodiment, the first semiconductor layer 110 and the light-emitting layer 120 are etched by the Mesa-ICP method, so that the light-emitting layer 120 and the first semiconductor layer 110 of the plurality of light-emitting cells 100 are disposed at intervals. The hard mask is photoresist or silicon dioxide, and the etching gas is Cl 2 ，BCl 3 ,N 2 And Ar, etching to the second semiconductor layer 130.
As shown in fig. 4, the second semiconductor layer 130 between two adjacent light emitting cells 100 is connected together, and the second semiconductor layer 130 needs to be further etched to separate the two adjacent light emitting cells 100.
The epitaxial wafer may be etched by dry etching, wet etching, or a mixture of dry and wet etching, thereby forming a plurality of light emitting cells 100 disposed to be spaced apart from each other. Wherein, the dry etching can adopt ICP method and Cl method 2 ，BCl 3 And Ar or the like; wet etching can use hydrofluoric acid (HF), buffer oxygenChemical etching solution (BOE, buffered Oxide Etch) is formed by mixing hydrofluoric acid (49%) with water or ammonium fluoride with water. In this embodiment mode, dry etching is used.
Step S300: the exposed second semiconductor layer 130 is etched, and a conductive layer 140 is disposed on a side of the exposed second semiconductor layer 130 facing the light emitting layer 120.
As described above, in the present embodiment, the first electrode layer 141 is a metal electrode made of Ti/Al/Ti/Au/Ni/Fe/Pt/Pd/Au/Ge, and the metal electrode is typically formed by plating a film on the non-stacked portion 131 by electron beam deposition.
Meanwhile, as shown in fig. 7, the second electrode layer 143 is a diamond-like film, the light blocking layer 142 is also a diamond-like film, and the second electrode layer 143 and the light blocking layer 142 are fabricated simultaneously and integrally.
As shown in fig. 4, 5 and 6, as described above, the first electrode layer 141 and the second semiconductor layer 130 have two connection modes, and the formation of the two connection modes is related to different sequences of the etching process and the e-beam evaporation process, specifically:
as shown in fig. 13, step S310: a first electrode layer 141 is provided on a side of the second semiconductor layer 130 facing the light emitting layer 120; the first electrode layer 141 and the second semiconductor layer 130 are etched until the substrate 200 is exposed.
Specifically, the first electrode layer 141 is formed on the non-stacked portion 131 by electron beam evaporation, and after deposition, the first electrode layer 141 and the non-stacked portion 131 of the second semiconductor layer 130 form ohmic contact by RTA rapid thermal annealing.
Etching by ICP method, wherein the hard mask is photoresist or silicon dioxide, and the etching gas is Cl 2 ，BCl 3 ,N 2 And Ar, etching the first electrode layer 141 and the second semiconductor layer 130 between the two light emitting cells 100 until the substrate 200 is exposed. The second semiconductor layer 130 is formed with a mesa on a side close to the light emitting layer 120, and the mesa may have a square shape, a circular shape, a polygonal shape, an elliptical shape, or the like.
In the related art, the over etching does not form the mesa, but etches the first semiconductor layer 110, the light emitting layer 120 so as to expose the substrate 200. Absent the mesa, after the light emitting units 100 are flipped, there is a possibility that there is no conduction between the adjacent light emitting units 100. The application avoids the situation of no conduction by reserving the table top.
Before the first electrode layer 141 is disposed, the exposed surface of the second semiconductor layer 130 facing the light emitting layer 120 is the non-stacked portion 131. In this step, since the electron beam deposition process is performed and then the etching process is performed, the first electrode layer 141 is connected only to the non-stacked portion 131.
As shown in fig. 13, step S320: etching the exposed second semiconductor layer 130 to expose the substrate 200; the first electrode layer 141 is disposed on a side of the second semiconductor layer 130 remaining after etching toward the light emitting layer 120.
Specifically, an ICP method is adopted for etching, a hard mask is photoresist or silicon dioxide, and the etching gas is Cl 2 ，BCl 3 ,N 2 And Ar, etching the second semiconductor layer 130 between the two light emitting cells 100 until the substrate 200 is exposed. The second semiconductor layer 130 is formed with a mesa on a side close to the light emitting layer 120, and the mesa may have a square shape, a circular shape, a polygonal shape, an elliptical shape, or the like.
And then, the first electrode layer 141 is arranged on one surface of the second semiconductor layer 130 which is left after etching and faces the light-emitting layer 120 by using electron beam evaporation, and after deposition, the first electrode layer 141 and the second semiconductor layer 130 form ohmic contact by using an RTA rapid thermal annealing method.
Before the first electrode layer 141 is disposed, the exposed surface of the second semiconductor layer 130 facing the light emitting layer 120 is the non-stacked portion 131. In this step, since the etching process is first performed, a surface of the second semiconductor layer 130 remaining after etching facing the light emitting layer 120 includes both the non-stacked portion 131 and the connection surface 132; then, the electron beam evaporation process is performed, the first electrode layer 141 is deposited on the non-stacked portion 131 and the connection surface 132, and even the first electrode layer 141 is deposited on the substrate 200 between the adjacent two light emitting units 100, and the first electrode layer 141 forms a connection with the non-stacked portion 131 and the connection surface 132.
Step S400: the third electrode layer 150 is disposed at a side of the first semiconductor layer 110 remote from the light emitting layer 120.
As shown in fig. 7, specifically, the third electrode layer 150 is evaporated by electron beam on the side of the first semiconductor layer 110 away from the light emitting layer 120, and after the third electrode layer 150 is deposited, ohmic contact is formed between the third electrode layer 150 and the surface of the first semiconductor layer 110 by RTA rapid thermal annealing.
Step S500: a light blocking layer 142 is disposed on a side of the first electrode layer 141 remote from the second semiconductor layer 130.
As shown in fig. 7, specifically, diamond-like carbon is deposited by chemical vapor deposition, and the deposited structure of the diamond-like carbon is a light blocking layer 142, and the diamond-like carbon surrounds each light emitting unit 100.
In step S310, step S320, and this step, the light blocking layer 142 deposited on the first electrode layer 141 and the first electrode layer 141 deposited on the second semiconductor layer 130 are not simultaneously contacted with the light emitting layer 120 and the first semiconductor layer 110, so that short circuits are avoided.
By depositing the light blocking layer 142, stable electrical connection is formed between the two second semiconductor layers 130 of the two light emitting units 100 of the adjacent two light emitting units 100, and the plurality of second semiconductor layers 130 of the plurality of light emitting units 100 on the light emitting chip 1000 are connected to form a common N-pole structure.
Further, the deposition height of the light blocking layer 142 should be not lower than the height of the side of the first semiconductor layer 110 near the light emitting layer 120, so that the diamond-like carbon can absorb the light emitted from the light emitting layer 120, thereby reducing the problem of light crosstalk between two adjacent light emitting units 100.
When the deposition height of the light blocking layer 142 is consistent with the height of the side of the first semiconductor layer 110 away from the light emitting layer 120, the position of the first electrode connection layer 160 is raised, and after the flip-chip, the positions of the first electrode connection layer 160 and the third electrode connection layer 170 connected to the first semiconductor layer 110 are close to each other, so that the subsequent bonding process is facilitated, and the product production efficiency is improved.
Step S600: a passivation layer 180 is disposed on the surface of the light emitting unit 100.
As shown in fig. 8, specifically, a passivation layer 180 of SiO2/SiN4 is deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to protect the light emitting unit 100.
Step S700: the first electrode connection layer 160 and the third electrode connection layer 170 are disposed on the passivation layer 180.
As shown in fig. 9 and 10, specifically, a first contact hole 181 and a second contact hole 182 are formed in the passivation layer 180 by ICP, RIE or wet etching, and the main etching gas is SF 6 ，CF 4 Or CHF 3 The opening area may be circular or square, so long as the first electrode layer 141 and the light blocking layer 142 are exposed to contact with the subsequent indium metal. The wet etch may employ a hydrofluoric acid (HF) BOE.
The first contact hole 181 and the second contact hole 182 are filled with electron beam evaporation, and the first electrode connection layer 160 and the third electrode connection layer 170 are formed, respectively.
The first contact hole 181 is correspondingly disposed on the light blocking layer 142, the second contact hole 182 is correspondingly disposed on the third electrode layer 150, the first electrode connection layer 160 is connected to the light blocking layer 142, and the third electrode connection layer 170 is connected to the third electrode layer 150.
Step S800: the substrate 200 is peeled off.
As shown in fig. 10 and 11, in particular, since the conductive layer 140 is disposed on the second semiconductor layer 130, the substrate 200 may be peeled off, thereby preventing light from being transmitted between the plurality of light emitting units 100 through the substrate 200 and improving the phenomenon of optical crosstalk.
Further, when the intrinsic semiconductor layer 210 is disposed between the substrate 200 and the first semiconductor layer 110, the intrinsic semiconductor layer 210 may be removed after the substrate 200 is peeled off, thereby preventing light from being transmitted between the plurality of light emitting units 100 through the intrinsic semiconductor layer 210 and further improving the phenomenon of optical crosstalk.
Specifically, the substrate 200 is wet/dry etched.
In some embodiments, another embodiment of the present application provides a display device, including the light emitting chip 1000 provided in any one of the embodiments described above, or the light emitting chip 1000 manufactured by the method for manufacturing the light emitting chip 1000 provided in any one of the embodiments described above.
The display device provided by the embodiment of the application is provided with the light emitting chip 1000 provided by any embodiment or the light emitting chip 1000 manufactured by the manufacturing method of the light emitting chip 1000 provided by any embodiment. Therefore, the light emitting chip 1000 provided in any of the above embodiments and the light emitting chip 1000 manufactured by the manufacturing method of the light emitting chip 1000 have all the advantages, which are not described herein.
The display device provided by the application can be a display device or an electronic device with a display module, and the display device comprises, but is not limited to, a mobile phone, a tablet, a notebook computer, a television, an AR/VR device, a vehicle instrument and central control, an outdoor display, a head-up display (HUD), a household appliance with a display screen and the like. The display device may also be an electronic device with a light emitting module, including but not limited to a projector, a desk lamp, etc. The display device includes the light emitting chip 1000 or the light emitting chip 1000 manufactured by the manufacturing method, and further includes a driving chip for bonding with the light emitting unit 100, a control module for controlling the display screen of the light emitting unit 100, a power supply module, and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (13)
1. A light emitting chip, comprising:
the light emitting array realizes the electrical connection among a plurality of light emitting units through the conductive layer;
each light-emitting unit comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer, wherein the first semiconductor layer, the light-emitting layer and the second semiconductor layer are sequentially stacked; the second semiconductor layer has a non-overlapping portion with the light emitting layer; the non-overlapping portion of each of the plurality of light emitting units is respectively in contact with the conductive layer, so that electrical connection among the plurality of light emitting units is realized.
2. The light-emitting chip according to claim 1, wherein the conductive layer includes a first electrode layer and a second electrode layer, one side of the first electrode layer is in contact with a non-stacked portion of each of the plurality of light-emitting units, and the other side of the first electrode layer is in contact with the second electrode layer.
3. The light-emitting chip according to claim 1 or 2, wherein a light-blocking layer is further disposed on the surface of the conductive layer, the light-blocking layer is disposed on a side of the conductive layer close to the first semiconductor layer, and the light-blocking layer is disposed around a circumferential edge of the light-emitting layer, so as to absorb and/or reflect light emitted by the light-emitting layer.
4. A light emitting chip as recited in claim 3, wherein the light blocking layer is a diamond-like film.
5. A light emitting chip according to claim 3, wherein the height of the light blocking layer is greater than or equal to the height of the light emitting layer.
6. The light-emitting chip according to claim 5, wherein the light-emitting unit further comprises a first electrode connection layer provided on a side of the light-blocking layer away from the second semiconductor layer.
7. A method of manufacturing a light emitting chip, comprising:
providing a light emitting array on a substrate, wherein the light emitting array is provided with a conductive layer and a plurality of light emitting units, and the light emitting units comprise a first semiconductor layer, a light emitting layer and a second semiconductor layer;
the first semiconductor layer, the light-emitting layer and the second semiconductor layer are sequentially stacked, and a non-stacked part of the second semiconductor layer and the light-emitting layer exists; the non-overlapping portion of each of the plurality of light emitting units is respectively in contact with the conductive layer, so that electrical connection among the plurality of light emitting units is realized.
8. The method for manufacturing a light-emitting chip according to claim 7, wherein,
sequentially growing the second semiconductor layer, the light emitting layer and the first semiconductor layer on the substrate;
etching the first semiconductor layer and the light-emitting layer so as to expose the second semiconductor layer;
and providing a conductive layer on the exposed surface of the second semiconductor layer facing the light-emitting layer.
9. The method for manufacturing a light-emitting chip according to claim 8, wherein,
providing the conductive layer on a side of the second semiconductor layer facing the light emitting layer;
the conductive layer and the second semiconductor layer are etched until the substrate is exposed.
10. The method for manufacturing a light-emitting chip according to claim 8, wherein,
etching the exposed second semiconductor layer to expose the substrate;
the conductive layer is provided on a side of the second semiconductor layer remaining after etching, which faces the light emitting layer.
11. The method of manufacturing a light emitting chip as claimed in claim 10, wherein,
and a light blocking layer is arranged on one side of the conductive layer far away from the second semiconductor layer.
12. The method for manufacturing a light-emitting chip according to claim 11, wherein,
and a first electrode connecting layer is arranged on one side of the light blocking layer away from the conductive layer.
13. A display device comprising the light-emitting chip according to any one of claims 1 to 6, or comprising the light-emitting chip obtained by the method for producing a light-emitting chip according to any one of claims 7 to 12.
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