CN114744095A - Preparation method of micro LED chip, micro LED chip and display device - Google Patents
Preparation method of micro LED chip, micro LED chip and display device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 230000002265 prevention Effects 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 46
- 238000002161 passivation Methods 0.000 claims description 18
- 230000000903 blocking effect Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 229910052738 indium Inorganic materials 0.000 claims description 11
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 7
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000000605 extraction Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002207 thermal evaporation Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000000313 electron-beam-induced deposition Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
- H01L33/465—Reflective coating, e.g. dielectric Bragg reflector with a resonant cavity structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
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Abstract
The invention relates to a preparation method of a micro LED chip, the micro LED chip and display equipment. The preparation method of the micro LED chip comprises the following steps: providing a light-emitting chip structure, wherein the light-emitting chip structure comprises a growth substrate and a light-emitting layer part grown on the growth substrate; preparing a crosstalk prevention layer part on one side of the light emitting layer part, which is far away from the growth substrate, wherein a partial structure of the crosstalk prevention layer part is electrically connected to the light emitting layer part, and the other part of the crosstalk prevention layer part and the side wall of the light emitting layer part are arranged at intervals; bonding the light-emitting chip structure with the driving chip through at least part of the crosstalk prevention layer part; and stripping the light-emitting layer part from the growth substrate. When the preparation method of the micro LED chip in the embodiment is used, the anti-crosstalk layer part is prepared and formed on the light-emitting layer part, so that the light crosstalk phenomenon between the light-emitting layer parts can be reduced, light rays emitted by the light-emitting layer part can be only reflected by the anti-crosstalk layer part, the purposes of limiting the light emission angle and enhancing the backlight light-emitting efficiency are achieved, and the use effect is good.
Description
Technical Field
The invention relates to the technical field of semiconductor photoelectricity, in particular to a preparation method of a micro LED chip, the micro LED chip and display equipment.
Background
The Micro light-Emitting Diode (Micro-LED) has self-luminous display characteristics, is an all-solid-state LED, has the excellent characteristics of long service life, high brightness, low power consumption, small volume, ultrahigh resolution and the like, and can be applied to extreme environments such as high temperature or radiation and the like. Compared with the traditional LED display technology, the Micro-LED has the advantages of high efficiency, long service life, relative stability due to the fact that the material is not easily influenced by the environment, and the phenomenon of ghost shadow can be avoided.
The Micro-LED display technology is a display technology which is characterized in that a traditional LED structure is subjected to Micro-reduction and array, a CMOS integrated circuit technology is adopted to manufacture a driving chip, addressing control and independent driving of each pixel point are achieved, and various indexes such as brightness, contrast, service life, response time, visual angle and resolution of the Micro-LED are better than those of an LCD and an OLED display technology.
As the Micro-LED is getting smaller in size, the pixel density (PPI) thereof is increasing, and the optical crosstalk phenomenon between pixels is inevitable. Therefore, as the distance between the Micro-LEDs is continuously reduced, the degree of optical crosstalk between pixels is continuously increased, so that the light-emitting pixels are blurred, and the quality of the displayed image is affected.
Therefore, it is necessary to improve upon the above-described problems to change the present situation.
Disclosure of Invention
The invention provides a preparation method of a Micro LED chip, the Micro LED chip and display equipment, which are used for solving the problems of pixel blurring and image display quality degradation of a Micro-LED due to size reduction.
The invention provides a preparation method of a micro LED chip, which comprises the following steps:
providing a light-emitting chip structure, wherein the light-emitting chip structure comprises a growth substrate and a light-emitting layer part grown on the growth substrate;
preparing a crosstalk prevention layer part on one side, far away from the growth substrate, of the light emitting layer part, wherein a partial structure of the crosstalk prevention layer part is electrically connected to the light emitting layer part, and the other part of the crosstalk prevention layer part and the side wall of the light emitting layer part are arranged at intervals;
bonding the light-emitting chip structure with a driving chip through at least part of the crosstalk prevention layer part;
and stripping the light-emitting layer part from the growth substrate.
According to an embodiment of the present invention, the light emitting layer portion includes a conductive layer, a p-base layer, a light emitting layer, an n-base layer, and a u-base layer sequentially disposed along the crosstalk prevention layer in a direction toward the growth substrate.
According to an embodiment of the present invention, the light emitting layer portion further includes a carrier confining layer provided between the p-base layer and the light emitting layer.
According to an embodiment of the present invention, the crosstalk prevention layer portion includes a first electrode portion electrically connected to the n-base layer and the driving chip, respectively, a second electrode portion electrically connected to the conductive layer and the driving chip, respectively, and a light-blocking electrode portion electrically connected to the first electrode portion or the second electrode portion; the light blocking electrode part is arranged at an interval with the outer wall of the light emitting layer part, and the orthographic projection of the light emitting layer on the side wall of the light blocking electrode part is positioned in the light blocking electrode part.
According to one embodiment of the present invention, when the light-blocking electrode portion is electrically connected to the first electrode portion, at least a part of the light-blocking electrode portion is provided between two adjacent light-emitting layer portions.
According to an embodiment of the invention, when the light blocking electrode portion is connected to the second electrode portion and encloses with the second electrode portion to form a reflection space, an inner wall of the reflection space is used for reflecting light, and the light emitting layer is accommodated in the reflection space.
According to an embodiment of the present invention, the preparation method further comprises the steps of:
before the anti-crosstalk layer part is prepared, a passivation layer part is prepared on one side, far away from the growth substrate, of the light-emitting layer part, a contact hole is formed in the passivation layer part, and the anti-crosstalk layer part is bonded with the light-emitting layer part through the contact hole.
According to an embodiment of the present invention, the crosstalk prevention layer portion is connected to the driving chip through a lead portion, and the lead portion is accommodated in the contact hole.
According to an embodiment of the present invention, the material of the lead portion includes indium.
According to one embodiment of the invention, the conductive layer comprises an ITO material; and/or the light emitting layer portion comprises a group III-V semiconductor material.
According to an embodiment of the invention, the light emitting layer portion comprises AlGaLnP material.
The invention also provides a micro LED chip which is prepared by the preparation method of any one of the micro LED chips.
The invention also provides a display device comprising the micro LED chip.
The embodiment of the invention has the following beneficial effects:
when the method for manufacturing the micro LED chip in the embodiment is used, the anti-crosstalk layer part is formed on the light-emitting layer part, the anti-crosstalk layer part can separate light rays emitted by the adjacent light-emitting layer parts, so that the light crosstalk phenomenon between the light-emitting layer parts is reduced, the light rays emitted by the light-emitting layer parts can be only reflected by the anti-crosstalk layer part, the purposes of limiting the light emission angle and enhancing the backlight light-emitting efficiency are achieved, and the using effect is good.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
FIG. 1 is a schematic flow chart of a method for manufacturing a micro LED chip according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a micro LED chip according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram illustrating a method for manufacturing a micro LED chip according to a first embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a micro LED chip according to a second embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating a method for fabricating a micro LED chip according to a second embodiment of the present invention;
reference numerals:
10. a micro LED chip;
100. a light emitting layer portion; 110. a conductive layer; 120. a p-base layer; 130. a light emitting layer; 140. n base layer; 150. u base layer;
200. a crosstalk prevention layer portion; 210. a first electrode section; 220. a second electrode section; 230. a light-blocking electrode section; 240. a lead section;
300. a driver chip;
400. a passivation layer portion; 410. a contact hole;
20. and growing the substrate.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 5, an embodiment of the present invention provides a Micro LED chip 10 and a method for manufacturing the Micro LED chip 10, where the Micro LED chip 10(Micro-LED) is manufactured by the above manufacturing method; specifically, referring to fig. 1, the method for manufacturing the micro LED chip 10 includes the following steps:
step S100, providing a light-emitting chip structure, wherein the light-emitting chip structure comprises a growth substrate 20 and a light-emitting layer part 100 grown on the growth substrate 20;
step S200, preparing a crosstalk prevention layer 200 on a side of the light emitting layer 100 away from the growth substrate 20, wherein a part of the structure of the crosstalk prevention layer 200 is electrically connected to the light emitting layer 100, and another part of the crosstalk prevention layer 200 is spaced apart from a sidewall of the light emitting layer 100;
step S300, bonding the light-emitting chip structure with the driving chip 300 through at least part of the crosstalk prevention layer part 200;
step S400 is to peel off the light-emitting layer portion 100 from the growth substrate 20.
When the method for manufacturing the micro LED chip 10 in the above embodiment is used, the anti-crosstalk layer portion 200 is formed on the light emitting layer portion 100, the anti-crosstalk layer portion 200 can separate light rays emitted from adjacent light emitting layer portions 100, so as to reduce the optical crosstalk phenomenon between the light emitting layer portions 100, and the light rays emitted from the light emitting layer portions 100 can be only reflected by the anti-crosstalk layer portion 200, so as to achieve the purposes of limiting the light emission angle and enhancing the backlight light extraction efficiency, and the using effect is good.
It should be noted that, in the light emitting chip structure of the present embodiment, the growth substrate 20 is sapphire, and a GaN epitaxial layer is generated on the growth substrate 20, and the GaN epitaxial layer structure includes a p-GaN layer, an MQWs multi-quantum well light emitting layer, an n-GaN layer, and an intrinsic GaN layer.
In this embodiment, the etching definition of the p region and the n region is generally performed by an ICP method, the mask may be a thick photoresist or silicon dioxide, and the used gases are Cl2, BCl3 and Ar, and are etched until the n-GaN layer, so as to form a light-emitting Mesa of Mesa; the shape of the Mesa of Mesa includes, but is not limited to, rectangular, circular, polygonal, elliptical.
After the light-emitting chip structure is in flip-chip bonding to the driving chip 300, the GaN buffer layer at the GaN/sapphire interface can be decomposed by using laser energy, so that the Micro-LED and the sapphire substrate can be separated, and the Micro-LED chip transfer is completed.
Specifically, the light emitting layer portion 100 includes a conductive layer 110, a p-base layer 120, a light emitting layer 130, an n-base layer 140, and a u-base layer 150 sequentially disposed in a direction toward the growth substrate 20 along the crosstalk prevention layer.
In the present embodiment, the light emitting layer portion 100 includes a III-V semiconductor material. In one embodiment, light emitting layer portion 100 includes AlGaLnP material. In this embodiment, the light emitting layer 130 may be GaN-based, or may be a III-V semiconductor material such as AlGaInP.
In the present embodiment, the conductive layer 110 includes an ITO (indium tin oxide) material, and the conductive layer 110 made of ITO is a transparent conductive layer. In the light-emitting layer part 100 of the present embodiment, ITO can be deposited by magnetron sputtering, and current diffusion can be made more uniform. After deposition is finished, the photoresist is removed by a Lift-off process, and ITO is left. And then forming ohmic contact between the ITO and the GaN surface by using an RTA rapid thermal annealing method.
In other embodiments, the conductive layer 110 may also be made of Ni or Au, which is not limited herein. The p-based layer 120 is p-GaN, the n-based layer 140 is n-GaN, the u-based layer 150 is u-GaN, and the light emitting layer 130 is an MQWs quantum well.
In one embodiment, the light emitting layer portion 100 further includes a carrier confining layer disposed between the p-base layer 120 and the light emitting layer 130.
Further, referring to fig. 3 and 5, the above preparation method further includes the steps of:
before the crosstalk preventing layer portion 200 is prepared, a passivation layer portion 400 is prepared on a side of the light emitting layer portion 100 away from the growth substrate 20, and a contact hole 410 is formed on the passivation layer portion 400, and the crosstalk preventing layer portion 200 is bonded to the light emitting layer portion 100 through the contact hole 410.
In the present embodiment, the passivation layer 400 includes but is not limited to SiO2/Ta2O5、SiO2、Si3N4，Al2O3,Ta2O5Or an insulating material, and is not limited herein. It can be understood that the passivation layer 400 can protect the device and improve the performance of the device. Specifically, the passivation layer portion 400 can be prepared by a thin film deposition technique such as PECVD, ALD, and the like. In a preferred implementation, the blue LED is preferably ALD alternating deposition of SiO2/Ta2O5Finally, a layer of Al is covered2O3。
Further, referring to fig. 2 and 4, the crosstalk prevention layer portion 200 includes a first electrode portion 210, a second electrode portion 220 and a light blocking electrode portion 230, the first electrode portion 210 is electrically connected to the n-base layer 140 and the driving chip 300, the second electrode portion 220 is electrically connected to the conductive layer 110 and the driving chip 300, and the light blocking electrode portion 230 is electrically connected to the first electrode portion 210 or the second electrode portion 220; the light-blocking electrode portion 230 is disposed at an interval from the outer wall of the light-emitting layer portion 100, and an orthogonal projection of the light-emitting layer 130 on the side wall of the light-blocking electrode portion 230 is located inside the light-blocking electrode portion 230.
With this arrangement, when the light emitting layer part 100 is connected to the driving chip 300, the first electrode part 210 may be electrically connected to the n-base layer 140, and the second electrode part 220 may be electrically connected to the p-base layer 120, thereby forming a PN loop.
In the arrangement state shown in fig. 2 and 4, the height dimension of the light-blocking electrode part 230 is not less than the height dimension of the light-emitting layer 130 in the vertical direction, and the orthographic projection of the light-emitting layer 130 is located within the light-blocking electrode part 230 in the horizontal direction; with this arrangement, the light blocking electrode 230 can block light from the side surface of the light emitting layer 130, and at the same time, the emission angle of light emitted from the light emitting layer 130 is limited, so as to achieve the function of preventing optical crosstalk.
The first embodiment is as follows:
specifically, referring to fig. 2 and 3, in the present embodiment, the light-blocking electrode portion 230 is electrically connected to the first electrode portion 210, and at least a portion of the light-blocking electrode portion 230 is disposed between two adjacent light-emitting layer portions 100.
Referring to fig. 2 and 3, in the first embodiment, the first electrode portion 210 is disposed at an interval from the light-blocking electrode portion 230, and the light-blocking electrode portion 230 is located between two adjacent light-emitting layers 130; after the light-emitting layer portion 100 is connected to the driving chip 300 through the crosstalk prevention layer portion 200, the light-blocking electrode portion 230 and/or the first electrode portion 210 may reflect the light emitted by the light-emitting layer portion 100 toward a direction away from the driving chip 300, and the light-blocking electrode portion 230 may reflect the light emitted by the light-emitting layer portion 100 toward a side surface, so that the light is conducted toward the adjacent light-emitting layer portion 100 along the light path in fig. 2, thereby achieving an effect of eliminating the optical crosstalk phenomenon of the micro LED chip 10.
Referring to fig. 4 and 5, in the second embodiment, the first electrode portion 210 may be a p electrode, the second electrode portion 220 may be an n electrode, and the first electrode portion 210 and the second electrode portion 220 may be prepared by the method for preparing the p electrode and the n electrode in the first embodiment, which is not described herein again.
As shown in fig. 1 and fig. 3, in this embodiment, the step S200 specifically includes the following steps:
step S201, etching to form a p area and an n area:
the side of the light emitting layer portion 100 away from the growth substrate 20 is etched to the n-base layer 140. A Mesa that emits light is formed on the light emitting layer portion 100 by etching, and the Mesa at this time includes the p-base layer 120 and the light emitting layer 130. Specifically, the etching process may be performed by using an ICP process, where a mask in the ICP process includes but is not limited to photoresist and silicon dioxide, and a gas in the ICP process includes but is not limited to Cl2、BCl3And Ar. In the present embodiment, the cross section of the Mesa of Mesa may be circular, polygonal, elliptical, etc. in the direction perpendicular to the axial direction thereof, which is not limited herein.
Step S202, depositing the conductive layer 110:
a conductive layer 110 is deposited on the Mesa side of Mesa away from n-base layer 140. In this step, the current spreading uniformity can be improved by depositing the conductive layer 110 on the Mesa of Mesa. Specifically, in this step, a process such as magnetron sputtering may be used to deposit the conductive layer 110, after the deposition is completed, a Lift-off process is used to remove the photoresist on the light emitting layer portion 100 and leave the conductive layer 110, and finally, an RTA rapid thermal annealing method may be used to form an ohmic contact between the conductive layer 110 and the surface of the p-base layer 120.
Step S203, preparing the crosstalk prevention layer part 200:
an electrode region is defined on the light emitting layer portion 100, and a light blocking electrode portion 230 and a second electrode portion 220 are vapor-deposited on the n-base layer 140, and a first electrode portion 210 is vapor-deposited on the conductive layer 110. In this step, the electrode region of the light-emitting layer part 100 may be defined by using a photoresist, and specifically, a metal electrode may be deposited by using a process such as electron beam deposition, magnetron sputtering, thermal evaporation, or the like. The photoresist may be removed by a Lift-off process, and the first electrode portion 210, the second electrode portion 220, and the light blocking electrode portion 230 are left, the conductive electrode material includes but is not limited to Ti/Al/Ti/Au, Ni, Fe, Pt, Pd, and other conductive materials, and the cross-sectional shapes of the first electrode portion 210 and the second electrode portion 220 include but are not limited to a square, a circle, and a rounded square, which is not limited herein.
In this embodiment, the light-blocking electrode 230 may form a grid structure on the n-based layer 140, and at least one Mesa is disposed in each grid space and connected to the first electrode 210 to realize circuit conduction, so that the light-blocking electrode 230 not only can make the current conduction of the first electrode 210 more uniform, but also the grid light-blocking electrode 230 can reflect the light of the light-emitting layer 130, thereby realizing the anti-crosstalk function.
In the present embodiment, the current of the driving chip 300 is conducted to the n-base layer 140 through the second electrode portion 220, and then conducted through the light blocking electrode portion 230; in yet another embodiment, opposite ends of the light-blocking electrode part 230 may be connected to the n-base layer 140 and the connection point of the second electrode part 220 on the driving chip 300, respectively, along the vertical direction, and the current conducted by the driving chip 300 via the second electrode part 220 may be conducted via the light-blocking electrode part 230 at the same time.
In addition, in some embodiments, one end of the light-blocking electrode portion 230, which is far away from the driving chip 300, may be disposed at an interval with the n-base layer 140, and at this time, the light-blocking electrode portion 230 is not electrically connected with the n-base layer 140, and the function of preventing optical crosstalk may also be achieved by implementing electrical connection between the second electrode portion 220 and the n-base layer 140.
Step S204, preparing a passivation layer portion 400:
a passivation layer 400 is deposited on the surface of the light emitting layer 100 away from the growth substrate 20, and contact holes 410 corresponding to the first electrode portion 210 and the second electrode portion 220 are formed in the passivation layer 400.
Specifically, in this step, the contact hole 410 opening region of the passivation layer 400 is first defined by photoresist, and then the connection is opened by ICP, RIE or BOE wet etchingA contact hole 410; when SiO is usedAt 2 timeThe etching gas used for etching includes but is not limited to SF6、CF4、CHF3The opening shape of the contact hole 410 includes, but is not limited to, rectangular, circular, polygonal, and oval. In another embodiment, the BOE wet etch may use a 49% aqueous HF solution: 40% NH4F aqueous solution 1: 6 (volume ratio), and is not limited herein.
Step S205, preparing lead portion 240:
the lead part 240 is prepared at the contact hole 410 and the crosstalk prevention layer part 200 is electrically connected to the driving chip 300 through the light blocking electrode part 230.
Referring to fig. 2 and 4, in the present embodiment, the crosstalk prevention layer 200 is connected to the driving chip 300 through the lead portion 240, and the lead portion 240 is accommodated in the contact hole 410. Specifically, the material of lead portion 240 includes indium.
In this step, thermal evaporation or electron beam evaporation may be used to deposit indium metal, the shape of the indium metal includes, but is not limited to, round corner, square, and round, after the deposition is completed, the photoresist is removed by a Lift-off process, the indium metal is retained, and then a reflow process may be used to make the indium metal spherical for bonding with the driver chip 300.
Example two:
specifically, referring to fig. 4 and fig. 5, the difference between the present embodiment and the first embodiment is that the light-blocking electrode 230 is connected to the second electrode 220 and forms a reflective space with the second electrode 220, an inner wall of the reflective space is used for reflecting light, the light-emitting layer 130 is accommodated in the reflective space, and an opening of the reflective space faces a side away from the driving chip 300.
Referring to fig. 4, in the second embodiment, at least a portion of the light-emitting layer portion 100 is accommodated in the reflection space formed by the second electrode portion 220 and the light-blocking electrode portion 230, the light emitted by the light-emitting layer portion 100 can be reflected by the inner wall of the reflection space, and the reflected light is guided out from the opening of the reflection space along the light path in fig. 4, so as to achieve the effect of eliminating the optical crosstalk phenomenon of the micro LED chip 10. Specifically, in the present embodiment, one end of the light-blocking electrode 230 facing the driving chip 300 is spaced from the driving chip 300 or isolated from the driving chip 300 by an insulating material.
As shown in fig. 1 and fig. 5, in this embodiment, the step S200 specifically includes the following steps:
step S201, depositing the conductive layer 110:
a conductive layer 110 is deposited on the Mesa side of Mesa away from n-base layer 140. In this step, the current diffusion uniformity can be improved by depositing the conductive layer 110 on the Mesa of Mesa. Specifically, in this step, a process such as magnetron sputtering may be used to deposit the conductive layer 110, after the deposition is completed, a Lift-off process is used to remove the photoresist on the light emitting layer portion 100 and leave the conductive layer 110, and finally, an RTA rapid thermal annealing method may be used to form an ohmic contact between the conductive layer 110 and the surface of the p-base layer 120.
Step S202, etching to form a p area and an n area:
the side of the light emitting layer portion 100 away from the growth substrate 20 is etched to the n-base layer 140. A Mesa that emits light is formed on the light emitting layer portion 100 by etching, and the Mesa at this time includes the p-base layer 120 and the light emitting layer 130. Particularly, the etching process can be performed by using an ICP process or an RIE process, wherein a mask in the ICP process includes but is not limited to photoresist and silicon dioxide, and a gas in the ICP process includes but is not limited to CH4、H2And Ar. In the present embodiment, the cross section of the Mesa of Mesa may be circular, polygonal, elliptical, etc. in the direction perpendicular to the axial direction thereof, which is not limited herein.
Step S203, preparing the passivation layer part 400:
a passivation layer 400 is deposited on the surface of the light emitting layer 100 away from the growth substrate 20, and contact holes 410 corresponding to the first electrode portion 210 and the second electrode portion 220 are formed in the passivation layer 400.
Specifically, in this step, a photoresist is used to define an opening region of the contact hole 410 of the passivation layer portion 400, and then the contact hole 410 is opened by using an ICP, RIE or BOE wet etching method; when SiO is used2In this case, the etching gas used for etching includes, but is not limited to, SF6、CF4、CHF3Opening of contact hole 410Shapes include, but are not limited to, rectangular, circular, polygonal, elliptical. In another embodiment, the BOE wet etch may use a 49% aqueous HF solution: 40% NH4F aqueous solution 1: 6 (volume ratio), and is not limited to the only example.
Step S204, preparing the crosstalk prevention layer part 200:
an electrode region is defined on the light emitting layer part 100, a first electrode part 210 is evaporated on the n-base layer 140, and a second electrode part 220 and a light blocking electrode part 230 are evaporated on the conductive layer 110. In this step, the electrode region of the light-emitting layer part 100 may be defined by using a photoresist, and specifically, a metal electrode may be deposited by using a process such as electron beam deposition, magnetron sputtering, thermal evaporation, or the like. The photoresist may be removed by a Lift-off process, and the first electrode portion 210, the second electrode portion 220, and the light blocking electrode portion 230 are left, the conductive electrode material includes but is not limited to Ti/Al/Ti/Au, Ni, Fe, Pt, Pd, and other conductive materials, and the cross-sectional shapes of the first electrode portion 210 and the second electrode portion 220 include but are not limited to a square, a circle, and a rounded square, which is not limited herein.
In the embodiment, the light-blocking electrode part 230 and the second electrode part 220 are connected to form a cover-shaped structure having a light-reflecting space, and the cover-shaped structure not only can realize the circuit conduction between the conductive layer 110 and the driving chip 300, but also can reflect the light emitted from the light-emitting layer 130 in the light-reflecting space, thereby realizing the anti-crosstalk function.
In this step, thermal evaporation or electron beam evaporation may be used to deposit indium metal, the shape of the indium metal includes, but is not limited to, round corner, square, and round, after the deposition is completed, the photoresist is removed by a Lift-off process, the indium metal is retained, and then a reflow process may be used to make the indium metal spherical for bonding with the driver chip 300.
With this arrangement, the micro LED chip 10 formed by the manufacturing method in any one of the above embodiments is manufactured, and the crosstalk prevention layer portion 200 is provided to separate the adjacent light emitting layer portions 100 (i.e., light emitting pixels), thereby reducing the crosstalk of light between the adjacent light emitting layer portions 100; in addition, the crosstalk prevention layer 200 can enhance the back light extraction efficiency of the micro LED chip 10, limit the light emission angle, prevent crosstalk between pixels, and improve the light extraction efficiency.
The present invention also provides a display device including the micro LED chip 10 formed as prepared in any one of the above embodiments.
It can be understood that, in the display device of the present embodiment, by using the micro LED chip 10 of the above embodiment, the display device can achieve the effect of reducing the optical crosstalk between adjacent pixels, and the back light extraction efficiency is high, the light extraction efficiency is high, and the using effect is good.
In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. Specific meanings of the above terms in the embodiments of the present invention may be understood as specific cases by those of ordinary skill in the art.
In embodiments of the invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (13)
1. A preparation method of a micro LED chip is characterized by comprising the following steps:
providing a light-emitting chip structure, wherein the light-emitting chip structure comprises a growth substrate and a light-emitting layer part grown on the growth substrate;
preparing a crosstalk prevention layer part on one side, far away from the growth substrate, of the light emitting layer part, wherein a partial structure of the crosstalk prevention layer part is electrically connected to the light emitting layer part, and the other part of the crosstalk prevention layer part and the side wall of the light emitting layer part are arranged at intervals;
bonding the light-emitting chip structure with a driving chip through at least part of the crosstalk prevention layer part;
and stripping the light-emitting layer part from the growth substrate.
2. The method of claim 1, wherein the light emitting layer comprises a conductive layer, a p-based layer, a light emitting layer, an n-based layer, and a u-based layer sequentially disposed along the anti-crosstalk layer in a direction toward the growth substrate.
3. The method of claim 2, wherein the light-emitting layer further comprises a carrier confining layer disposed between the p-base layer and the light-emitting layer.
4. The method according to claim 2, wherein the crosstalk prevention layer portion includes a first electrode portion electrically connected to the n-base layer and the driving chip, a second electrode portion electrically connected to the conductive layer and the driving chip, and a light blocking electrode portion electrically connected to the first electrode portion or the second electrode portion; the light blocking electrode part is arranged at an interval with the outer wall of the light emitting layer part, and the orthographic projection of the light emitting layer on the side wall of the light blocking electrode part is positioned in the light blocking electrode part.
5. The method according to claim 4, wherein when the light-blocking electrode portion is electrically connected to the first electrode portion, at least a portion of the light-blocking electrode portion is disposed between two adjacent light-emitting layer portions.
6. The method according to claim 4, wherein when the light-blocking electrode is connected to the second electrode and forms a reflective space with the second electrode, an inner wall of the reflective space is used for reflecting light, and the light-emitting layer is accommodated in the reflective space.
7. The method for preparing a micro LED chip according to claim 4 or 5, further comprising the steps of:
before the anti-crosstalk layer part is prepared, a passivation layer part is prepared on one side, far away from the growth substrate, of the light-emitting layer part, a contact hole is formed in the passivation layer part, and the anti-crosstalk layer part is bonded with the light-emitting layer part through the contact hole.
8. The method for manufacturing a micro LED chip according to claim 7, wherein the anti-crosstalk layer is connected to the driving chip through a lead portion, and the lead portion is received in the contact hole.
9. The method of claim 8, wherein the lead portion comprises indium.
10. The method of claim 9, wherein the conductive layer comprises an ITO material; and/or the light emitting layer portion comprises a group III-V semiconductor material.
11. The method of claim 10, wherein the light emitting layer portion comprises AlGaLnP material.
12. A micro LED chip prepared by the method of any one of claims 1 to 11.
13. A display device comprising the micro LED chip according to claim 12.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117219715A (en) * | 2023-11-08 | 2023-12-12 | 华引芯（武汉）科技有限公司 | Preparation method of micro LED matrix light source and micro LED matrix light source |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117219715A (en) * | 2023-11-08 | 2023-12-12 | 华引芯（武汉）科技有限公司 | Preparation method of micro LED matrix light source and micro LED matrix light source |
| CN117219715B (en) * | 2023-11-08 | 2024-03-01 | 华引芯（武汉）科技有限公司 | Preparation method of micro LED matrix light source and micro LED matrix light source |
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