CN116864541A

CN116864541A - Schottky diode and power circuit

Info

Publication number: CN116864541A
Application number: CN202210313499.6A
Authority: CN
Inventors: 王嘉乐; 樊宗荐; 张强; 侯朝昭; 董耀旗; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2023-10-10
Also published as: WO2023185195A1

Abstract

The application relates to the technical field of semiconductors, in particular to a Schottky diode and a power circuit. The schottky diode includes: a first layer; a second layer in contact with the first layer, the first layer being one of a semiconductor layer and a metal layer, the second layer being the other of the semiconductor layer and the metal layer, a schottky barrier being present between the first layer and the second layer; a carrier providing layer coupled to the first layer for increasing a ratio of a number of first carriers in the first layer to a total number of carriers in the first layer; wherein the energy of the first carrier is lower than the height of the schottky barrier when the diode is in an off state; when the schottky diode enters an on state from an off state, the height of the schottky barrier is reduced so that the first carriers cross the schottky barrier and enter the second layer; alternatively, the width of the schottky barrier is reduced such that the first carriers tunnel through the schottky barrier into the second layer. The schottky diode can realize the rapid switching from the off state to the on state.

Description

Schottky diode and power circuit

Technical Field

The application relates to the technical field of semiconductors, in particular to a Schottky diode and a power circuit.

Background

Schottky barrier diode (schottky barrier diode, SBD), also known as schottky diode, is a microelectronic device composed of metal and semiconductor. The rectification characteristic of the Schottky barrier formed by the contact of the metal and the semiconductor endows the Schottky diode with unidirectional conduction capability, so that the Schottky diode can be used as a microelectronic switching element and applied to the aspects of generating, controlling, receiving, converting, amplifying signals, converting energy and the like. For example, schottky diodes may be used in conjunction with insulated gate bipolar transistors (insulated gate bipolar transistor, IGBTs) as switching elements in inverter circuits to convert direct current to alternating current and thereby drive the motor (motorr) to operate.

The lower on-voltage of the schottky diode allows for high speed switching between the off-state and the on-state. Because of the limitation of electron state density distribution of the materials constituting the Schottky diode, the ideal factor of the Schottky diode is larger than 1, namely the subthreshold swing is larger than 60mV/dec, and the characteristic that the Schottky diode allows high-speed switching between an off state and an on state is difficult to be exerted.

Disclosure of Invention

The embodiment of the application provides a Schottky diode and a power circuit, which can realize the rapid switching from an off state to an on state.

In a first aspect, there is provided a schottky diode comprising: a first layer; a second layer in contact with the first layer, wherein the first layer is one of a semiconductor layer and a metal layer, the second layer is the other of the semiconductor layer and the metal layer, and a Schottky barrier exists between the first layer and the second layer; a carrier providing layer coupled to the first layer for increasing a ratio of a number of first carriers in the first layer to a total number of carriers in the first layer; wherein the energy of the first carrier is lower than the height of the schottky barrier when the diode is in an off state; when the Schottky diode enters an on state from an off state, the height of the Schottky barrier is reduced, so that a first carrier passes over the Schottky barrier and enters a second layer; alternatively, the width of the schottky barrier is reduced such that the first carriers tunnel through the schottky barrier into the second layer.

Wherein the carriers mentioned herein are carriers of the same type. It is understood that carriers are divided into electrons and holes. The ratio of the number of the first carriers in the first layer to the total number of carriers in the first layer specifically means: the ratio of the number of first electrons in the first layer to the total number of electrons in the first layer, or the ratio of the number of first holes in the first layer to the total number of holes in the first layer.

Under the influence of the carrier providing layer, the duty cycle of the first carriers in the first layer in the schottky diode is raised, and the energy of the first carriers is lower than the height of the schottky barrier when the schottky diode is in the off-state, so that when the schottky diode is in the off-state, very few or even zero of the first carriers in the first layer can cross or tunnel through the schottky barrier, and a great majority or even all of the first carriers remain in the first layer. When a voltage is applied to the schottky diode to cause the schottky diode to enter an on state from an off state, the height of the schottky barrier is reduced so that the first carrier can cross the schottky barrier, or the width of the schottky barrier is reduced so that the first carrier can tunnel through the schottky barrier, thereby a larger current can be quickly generated, the schottky diode can quickly enter the on state, a subthreshold swing of less than 60mV/dec is shown, and the quick switching of the schottky diode from the off state to the on state is realized.

In one possible embodiment, the semiconductor layer is obtained by doping impurities in an intrinsic semiconductor layer, and the intrinsic semiconductor layer is made of at least one of germanium, germanium silicon, gallium nitride, indium gallium arsenic and carbon nanotubes; or the semiconductor layer is replaced by a carbon nano tube layer, wherein the carbon nano tube layer is made of carbon nano tubes.

In the embodiment, the intrinsic semiconductor can be flexibly selected for doping, so that a semiconductor layer for forming a Schottky barrier is obtained, and the scheme flexibility and the compatibility with the existing technology are improved. In this implementation, a carbon nanotube layer may also be used instead of the semiconductor layer.

The carbon nanotubes have ultrahigh mobility and saturation speed, so that the schottky diode has larger on current after entering an on state. And moreover, the carbon nano tube material has good ductility, is easy to be compatible with various device shapes, and is beneficial to three-dimensional (3D) integration of devices.

In one possible embodiment, the first layer is a semiconductor layer, the second layer is a metal layer, and the carrier providing layer includes a first semiconductor layer and a first conductor layer, wherein the first conductor layer is located between the first semiconductor layer and the first layer, and the first semiconductor layer and the first layer are doped with impurities of different properties.

Doping impurities of different nature means doping impurities of different types. It is understood that for a semiconductor, impurities can be classified into N-type impurities for providing electrons and P-type impurities for providing holes. When the two are doped with impurities with different properties, if one of the two is doped with N-type impurities, the other is doped with P-type impurities; if one of the two is doped with P-type impurity, the other is doped with N-type impurity.

This embodiment provides a specific structure of the schottky diode, which is simple and easy to manufacture. Also, in this embodiment mode, since the first semiconductor layer, the first conductor layer, and the first layer are different in material and fermi surface, energy band dislocation between the multiple layers of materials can be introduced, so that the first semiconductor layer can supply the first carriers to the first layer, and thus the ratio of the number of the first carriers in the first layer to the total number of carriers in the first layer can be increased.

In one possible embodiment, the carrier providing layer further includes a second semiconductor layer, the second semiconductor layer being located between the first conductor layer and the first layer, the second semiconductor layer and the first layer being doped with impurities of the same nature, and the doping concentration of the second semiconductor layer being greater than the doping concentration of the first layer.

In this embodiment mode, the second semiconductor layer and the first layer are doped with impurities of the same property, and the doping concentration of the second semiconductor layer is large, so that ohmic contact can be formed between the first conductor layer and the first layer, and resistance of the first carriers flowing from the first conductor layer to the first layer is reduced.

In one possible embodiment, the doping concentration of the second semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the first layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

When the doping concentration of the second semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the first layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 The first carrier encounters less resistance to flow from the first conductor to the first layer.

In one possible embodiment, the doping concentration of the first semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the first layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

When the doping concentration of the first semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the first layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 When the first semiconductor layer may provide the first layer with more first carriers, the ratio of the total number of first carriers in the first layer to the total number of carriers in the first layer may be increased more greatly.

In one possible embodiment, the material of the first conductor layer is metal or silicide; alternatively, the metal layer is replaced by a silicide layer or a transition metal disulfide layer.

In this embodiment, the material selection range of the first conductor layer is large, so that different materials can be selected according to specific needs (for example, compatibility of processes, availability of materials, and the like). There are many alternatives to the metal layer used to form the schottky barrier so that the material used to form the schottky barrier can be selected according to specific needs (e.g., process compatibility, availability of materials, etc.).

In one possible embodiment, the first layer is a metal layer, the second layer is a semiconductor layer, and the carrier providing layer includes a third semiconductor layer, the third semiconductor layer and the second layer being doped with impurities of different properties.

This embodiment provides a specific structure of the schottky diode, which is simple and easy to manufacture. Also, in this embodiment mode, since the materials of the first layer, the second layer, and the third semiconductor layer are different and fermi surfaces are different, energy band dislocation between the materials of the plurality of layers can be introduced, so that the third semiconductor layer can supply the first carriers to the first layer, and thus the ratio of the number of the first carriers in the first layer to the total number of carriers in the first layer can be increased.

In one possible embodiment, the doping concentration of the third semiconductor layer is greater than the doping concentration of the second layer.

When the doping concentration of the third semiconductor layer is greater than that of the second layer, the third semiconductor layer can provide more first carriers for the first layer, so that the ratio of the total number of the first carriers in the first layer to the total number of the carriers in the first layer can be greatly increased.

In one possible embodiment, the doping concentration of the third semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the second layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

When the doping concentration of the third semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the second layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 When the third semiconductor layer provides more first carriers for the first layer, the ratio of the number of the first carriers in the first layer to the total number of the carriers in the first layer can be greatly increased.

In one possible embodiment, the schottky diode further includes: an ohmic contact layer in contact with the second layer.

The ohmic contact layer may reduce the resistance between the second layer and a device (e.g., a power supply or a driving circuit) to which the second layer is connected, thereby improving the electrical performance of the schottky diode.

In one possible embodiment, the metal layer is replaced by any one of a semi-metal layer, a cold metal layer, a silicide layer, a transition metal disulfide layer.

In this embodiment, there may be a variety of alternatives to the metal layer used to form the schottky barrier, so that the material used to form the schottky barrier may be selected according to specific needs (e.g., process compatibility, availability of materials, etc.).

In one possible embodiment, the first layer is a semiconductor layer, the second layer is a metal layer, and the carrier providing layer includes a third layer, and the third layer is made of a cold metal layer or a semi-metal layer.

This embodiment provides a specific structure of the schottky diode, which is simple and easy to manufacture.

In cold metallic or semi-metallic materials, the first charge carrier is present in a high ratio. The cold metal or semi-metal is adopted as the carrier providing layer, more first carriers can be provided for the first layer, and the ratio of the number of the first carriers in the first layer to the total number of the carriers in the first layer is increased.

In this embodiment mode, the carrier providing layer further includes a fourth semiconductor layer between the third layer and the first layer, the fourth semiconductor layer and the first layer are doped with impurities of the same nature, and a doping concentration of the fourth semiconductor layer is greater than that of the first layer.

In this embodiment mode, the fourth semiconductor layer and the first layer are doped with impurities having the same property, and the doping concentration of the fourth semiconductor layer is large, so that ohmic contact can be formed between the third layer and the first layer, and resistance of the first carriers flowing from the third layer to the first layer can be reduced.

In one possible embodiment, the first layer is made of N-type halfThe third layer is made of NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ At least one of P-doped semi-metals; or the first layer is made of P-type semiconductor, and the third layer is made of NbS ₂ ,TaS ₂ At least one of an N-doped semi-metal.

In this embodiment, the third layer with different materials may be selected according to the impurities doped in the first layer, so that the third layer is more adapted to the first layer, thereby providing more first carriers for the first layer, and increasing the ratio of the first carriers in the first layer in the total number of carriers in the first layer.

In one possible embodiment, the metal layer is replaced by a silicide layer or a transition metal disulfide layer.

There are many alternatives to the metal layer used to form the schottky barrier so that the material used to form the schottky barrier can be selected according to specific needs (e.g., process compatibility, availability of materials, etc.).

In one possible embodiment, the first layer and the carrier providing layer are the same layer, and the second layer is a semiconductor layer, wherein the material of the first layer is a cold metal layer or a semi-metal layer.

In cold metallic or semi-metallic materials, the first charge carrier is present in a high ratio. The use of a cold metal or semi-metal as both the carrier-providing layer and the first layer makes it possible to raise the ratio of the number of first carriers in the first layer to the total number of carriers in the first layer to a maximum limit.

In a second aspect, a power circuit is provided, comprising the schottky diode and the field effect transistor provided in the first aspect.

The schottky diode provided by the first aspect exhibits a subthreshold swing below 60mV/dec and has a faster switching speed, thereby reducing the operating delay of the power circuit.

When the Schottky diode provided by the embodiment of the application enters the on state from the off state, the current can be quickly increased, the current can be quickly entered into the on state, subthreshold swing lower than 60mV/dec is shown, the quick switching of the Schottky diode from the off state to the on state is realized, and the method and the device can be used for reducing the operation time delay of an electronic device.

Drawings

Fig. 1 is a schematic structural diagram of a schottky diode according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a schottky diode according to an embodiment of the present application;

Fig. 3A is a schematic diagram showing the band distribution of the schottky diode shown in fig. 2 when in an off state;

fig. 3B is a schematic diagram of the band distribution of the schottky diode shown in fig. 2 when the schottky diode is in an on state;

fig. 4 is a schematic structural diagram of a schottky diode according to an embodiment of the present application;

fig. 5A is a schematic diagram showing the band distribution of the schottky diode shown in fig. 4 when in an off state;

fig. 5B is a schematic diagram showing the band distribution of the schottky diode shown in fig. 4 when the schottky diode is in an on state;

fig. 6 is a schematic structural diagram of a schottky diode according to an embodiment of the present application;

FIG. 7 is a schematic diagram of carrier density of cold source metal at different energies;

fig. 8 is a schematic structural diagram of a schottky diode according to an embodiment of the present application;

fig. 9A is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

fig. 9B is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

fig. 10A is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

fig. 10B is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

fig. 11 is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

Fig. 12 is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

fig. 13 is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present application;

fig. 14A is a graph showing a volt-ampere characteristic of a schottky diode according to an embodiment of the present application;

fig. 14B is a graph showing a volt-ampere characteristic of a schottky diode according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of a power circuit according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

It is understood that in the description of embodiments of the application, words such as "exemplary," "such as" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a alone, B alone, and both A and B. In addition, unless otherwise indicated, the term "plurality" means two or more.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

In addition, "contacting" in embodiments of the present application may be understood as "top-on" and generally refers to the two objects being brought together in a block or sheet shape, or one of the two objects being located on the surface of the other object. In addition, in embodiments of the present application, "connected" may refer to the direct contact of two objects. "connected" may also mean that two objects are connected by a third object, i.e., one side or end of the third object contacts one of the two objects and the other side or end of the third object contacts the other of the two objects.

The schottky diode can be used as a microelectronic switching element in an electronic device, and the speed of entering an on state from an off state affects the operation time delay of the electronic device. Wherein, the off state refers to the off state, and the on state refers to the on state.

The speed at which the off state enters the on state depends on the on speed of the forward current, which is limited by the reduced efficiency of the schottky barrier and the increased efficiency of the electron density at the source (S). The efficiency of the increase in electron density at the source is limited by the boltzmann distribution, so that the subthreshold swing of the conventional schottky diode turn-on cannot be lower than 60mV/dec. The subthreshold swing is a performance index for measuring the mutual conversion rate between the off state and the on state of the diode, and the smaller the subthreshold swing is, the faster the mutual conversion rate between the off state and the on state of the diode is.

In the embodiment of the present application, the source terminal refers to a terminal that provides carriers in the on state of the schottky diode. I.e. when the schottky diode is turned on, the end of the schottky diode that provides the carriers is called the source end. The other end of the schottky diode terminal may be referred to as a drain (D). The source and drain terminals have schottky barriers. When the schottky diode enters an on state from an off state, the schottky barrier in the schottky diode is lowered, and more carriers can flow from the source terminal of the schottky diode to the drain terminal of the schottky diode, thereby generating a current capable of realizing the on of the schottky diode.

The carriers refer to particles of a substance having a charge that can move freely. In the semiconductor field, carriers generally refer to electrons and holes. That is, electrons and holes may be collectively referred to as carriers, with electrons being one carrier and holes being the other carrier. The hole is called an electron hole, and refers to a void left on a covalent bond after one electron is lost from the covalent bond.

The embodiment of the application provides a scheme which can increase the ratio of the number of cold carriers in the source end to the total number of carriers in the source end. Wherein the carriers mentioned here are carriers of the same type, i.e. either electrons or holes. The ratio of the number of the up Leng Zailiu carriers to the total number of carriers means the ratio of the number of the up cold electrons to the total number of electrons or the ratio of the number of the up cold holes to the total number of holes.

In addition, it is understood that the schottky barrier is formed by the contact of the semiconductor layer and the metal layer. If the semiconductor layer forming the schottky barrier is an N-type semiconductor, the Leng Zailiu electrons are electrons and may be referred to as cold electrons. If the semiconductor layer forming the schottky barrier is a P-type semiconductor, the Leng Zailiu electrons are holes and may be referred to as cold holes.

The energy of the Leng Zailiu component is lower than the height of the Schottky barrier when the Schottky diode is in the off state, so that when the Schottky diode is in the off state, few or even zero cold carriers at the source end can cross the Schottky barrier, and most or even all cold carriers are reserved at the source end. When a voltage is applied to the schottky diode that causes the schottky diode to enter an on state from an off state, the height of the schottky barrier is reduced so that a large number of cold carriers can cross the schottky barrier, or the width of the schottky barrier is reduced so that a large number of cold carriers can tunnel through the schottky barrier, thereby a large current can be quickly generated so that the schottky diode quickly enters an on state, a subthreshold swing of less than 60mV/dec is exhibited, and quick switching of the schottky diode from the off state to the on state is realized.

In the embodiment of the present application, the reduction in the height of the schottky barrier can also be understood as a relative reduction in the height of the schottky barrier. Specifically, when the energy of the carrier increases, even if the absolute height of the schottky barrier is unchanged or the height increase amplitude is smaller than the carrier energy increase amplitude, it may be called the height decrease of the schottky barrier. Of course, when the energy of the carrier is unchanged or decreases, the absolute height of the schottky barrier decreases, or the height of the schottky barrier decreases by a larger magnitude than the energy of the carrier, which may also be referred to as the height of the schottky barrier decreases.

Next, an exemplary embodiment of the present application will be described with reference to the accompanying drawings.

Referring to fig. 1, an embodiment of the present application provides a schottky diode 10 including a layer 100 and a layer 200. Wherein layer 100 may be a semiconductor layer and layer 200 may be a metal layer; alternatively, layer 100 may be a metal layer and layer 200 may be a semiconductor layer. That is, layer 100 may be one of a semiconductor layer and a metal layer, and layer 200 may be the other of a semiconductor layer and a metal layer. Wherein layer 100 and layer 200 are in contact, their contact forms a schottky junction, i.e., a schottky barrier exists between layer 100 and layer 200.

In some embodiments, the semiconductor layer herein may be obtained by doping impurities in the intrinsic semiconductor layer. The impurity doped may be an N (positive) type impurity for providing electrons or a P (positive) type impurity for providing holes. The specific doping of the impurities will be described below, and will not be described again here. The intrinsic semiconductor layer is made of any one of germanium, germanium-silicon, gallium nitride, indium-gallium-arsenic and carbon nano tube, or can be a combination of two or more of germanium, germanium-silicon, gallium nitride, indium-gallium-arsenic and carbon nano tube.

In some embodiments, the semiconductor layer herein may be replaced by a carbon nanotube layer. The carbon nanotubes are made of carbon nanotubes.

In some embodiments, the metal layer may be made of metal, such as one or a combination of at least two of gold, silver, aluminum, platinum, nickel, titanium, and the like.

In some embodiments, the metal layer may be replaced with a transition metal disulfide layer. The transition metal disulfide layer is made of transition metal disulfide (transition metal disulfide, TMD).

In some embodiments, the metal layer may be replaced with a silicide layer. The silicide layer may be made of metal silicide. The metal silicide refers to a compound formed by metal (such as nickel, titanium, cobalt, lithium, calcium, magnesium, iron, chromium, etc.) and silicon, and has excellent electrical conductivity and thermal conductivity. In one example, the silicide layer is made of NiSi ₂ 、TiSi ₂ 、CoSi ₂ One or a combination of at least two of the foregoing.

In some embodiments, the metal layer may be replaced by a semi-metal layer. The semi-metal layer is made of semi-metal. The close-spaced material between the conduction and valence bands of the semi-metal has a higher density of electron states near the fermi level than the insulator, while being much smaller than the metal. Graphene, three-dimensional Bi, na ₃ Bi、Cd ₃ As ₂ Carbon nanotubes, etc. are more typical semi-metals.

In some embodiments, the metal layer may be replaced with a cold metal layer. The material of the cold metal layer is cold metal (clod metal). Cold metals refer to a class of materials with a rapid decrease in electron state density near the fermi surface, e.g. NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ 、NbS ₂ 、TaS ₂ . Wherein NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ May be referred to as cold electron metals, and may provide electrons. Can be called cold hole metal, nbS ₂ 、TaS ₂ Holes may be provided.

In some embodiments, the metal layer has a thickness of 3nm to 5nm.

Layer 100 may serve as the source terminal of schottky diode 10 and, correspondingly, layer 200 may serve as the drain terminal of the schottky diode.

When the layer 100 is a semiconductor layer and the layer 200 is a metal layer, the structure of the schottky diode 10 is a forward biased structure, and the schottky diode 10 may be referred to as a forward biased diode, i.e., the schottky diode 10 is turned on by a forward bias voltage. When the layer 100 is an N-type semiconductor, the forward bias voltage is: layer 100 is at a low potential and layer 200 is at a high potential. When the layer 100 is a P-type semiconductor, the forward bias voltage is: layer 100 is at a high potential and layer 200 is at a low potential.

When the layer 100 is a metal layer and the layer 200 is a semiconductor layer, the structure of the schottky diode 10 is a reverse bias structure, and the schottky diode 10 can be turned on under the action of a reverse bias voltage. When the layer 200 is an N-type semiconductor, the reverse bias voltage is: layer 100 is at a low potential and layer 200 is at a high potential. When the layer 200 is a P-type semiconductor, the reverse bias voltage is: layer 100 is at a high potential and layer 200 is at a low potential.

With continued reference to fig. 1, schottky diode 10 also includes a carrier-providing layer 300. The carrier-providing layer 300 may also be referred to as a cold source. The carrier provides a coupling of layer 300 to layer 100 that increases the ratio of the number of cold carriers in layer 100 to the number of carriers in layer 100.

Next, in various embodiments, the structure, material, and implementation of the material of the carrier-providing layer 300, and the layers 100 and 200, will be described.

In embodiment 1, the schottky diode 10 of the forward bias structure A1 is used.

Referring to fig. 2, embodiment 1 provides a schottky diode 10 employing a forward bias structure A1. In the forward bias structure A1, the layer 100 is a semiconductor layer, the layer 200 may be a metal layer, and the carrier supply layer 300 may include a semiconductor layer 311 and a conductor layer 312. Wherein conductor layer 312 is located between semiconductor layer 311 and layer 100.

In one illustrative example of embodiment 1, layer 100 may be an N-type semiconductor, i.e., a semiconductor doped with N-type impurities.

In one illustrative example of embodiment 1, layer 100 may be a P-type semiconductor, i.e., a semiconductor doped with P-type impurities.

The semiconductor layer 311 and the layer 100 are doped with impurities of different properties. Doping impurities of different nature means doping impurities of different types. It is understood that for a semiconductor, impurities can be classified into N-type impurities for providing electrons and P-type impurities for providing holes. When the two are doped with impurities with different properties, if one of the two is doped with N-type impurities, the other is doped with P-type impurities, and if one of the two is doped with P-type impurities, the other is doped with N-type impurities.

Wherein when semiconductor layer 311 is a P-type semiconductor, i.e., when layer 100 is an N-type semiconductor, carrier-providing layer 300 serves to raise the ratio of the number of electrons in layer 100 to the total number of electrons in layer 100. Wherein cold electrons refer to electrons having energies below the height of the schottky barrier when the schottky diode is in the off state.

Wherein when the semiconductor layer 311 is an N-type semiconductor, i.e., when the layer 100 is a P-type semiconductor, the carrier providing layer 300 serves to raise the ratio of the number of cooling holes in the layer 100 to the total number of holes in the layer 100. Wherein, cold holes refer to holes with energy lower than the height of the schottky barrier when the schottky diode is in the off state.

In one illustrative example of embodiment 1, the semiconductor layer 311 is a heavily doped semiconductor. Heavily doped semiconductor is also referred to as a heavily doped semiconductor, meaning that the semiconductor is doped with a relatively large amount of impurities. Corresponding to the heavily doped semiconductor is a lightly doped semiconductor. Lightly doped semiconductor, also referred to as lightly doped semiconductor, means that less impurities are doped into the semiconductor. That is, it can be classified into light doping and heavy doping according to the amount of the doped impurities.

ExampleThe doping concentration of the semiconductor layer 311 is 10 ¹⁹ -10 ²¹ cm ^-3 . In one example, the doping concentration of the semiconductor layer 311 is 10 ²⁰ cm ^-3 . In one example, the doping concentration of the semiconductor layer 311 is 10 ^19.5 cm ^-3 . In one example, the doping concentration of the semiconductor layer 311 is 10 ^20.5 cm ^-3 。

In one illustrative example of embodiment 1, the material of the conductor layer 312 may be metal. Such as gold, silver, aluminum, platinum, etc.

In one illustrative example of embodiment 1, the material of the conductor layer 312 may be silicide. The silicide may be a metal silicide. For example, niSi ₂ 、TiSi ₂ 、CoSi ₂ One or a combination of at least two of the foregoing.

In one illustrative example of embodiment 1, the material of the metal layer may be a metal, such as one or a combination of at least two of gold, silver, aluminum, platinum, and the like.

In one illustrative example of embodiment 1, the metal layer may be replaced with a silicide layer. The silicide layer may be made of metal silicide. The metal silicide refers to a compound formed by metal (such as nickel, titanium, cobalt, lithium, calcium, magnesium, iron, chromium, etc.) and silicon, and has excellent electrical conductivity and thermal conductivity. In one example, the silicide layer is made of NiSi ₂ 、TiSi ₂ 、CoSi ₂ One or a combination of at least two of the foregoing.

In one illustrative example of embodiment 1, the metal layer may be replaced with a transition metal disulfide layer.

In one illustrative example of embodiment 1, as shown in fig. 2, the carrier providing layer 300 may further include a semiconductor layer 313. Semiconductor layer 313 is located between conductor layer 312 and layer 100. Wherein semiconductor layer 312 and layer 100 are doped with impurities of the same nature. Both are doped with impurities of the same nature, meaning that the type of impurities doped with both are the same. Specifically, both are doped with N impurities at the same time, or doped with P-type impurities at the same time. The doping concentration of semiconductor layer 312 may be greater than the doping concentration of layer 100 so that an ohmic contact may be formed between conductor 312 and layer 100, reducing the resistance to flow of carriers from conductor 312 to layer 100.

Illustratively, the semiconductor layer 313 has a doping concentration of 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of layer 100 is 10 ¹⁵ -10 ¹⁸ cm ^-3 . In one example, the doping concentration of the semiconductor layer 313 is 10 ²⁰ cm ^-3 . In one example, the doping concentration of the semiconductor layer 313 is 10 ^19.5 cm ^-3 . In one example, the doping concentration of the semiconductor layer 313 is 10 ^20.5 cm ^-3 . In one example, the doping concentration of layer 100 is 10 ^17.5 cm ^-3 . In one example, the doping concentration of layer 100 is 10 ¹⁷ cm ^-3 . In one example, the doping concentration of layer 100 is 10 ^16.5 cm ^-3 . In one example, the doping concentration of layer 100 is 10 ¹⁶ cm ^-3 . In one example, the doping concentration of layer 100 is 10 ^15.5 cm ^-3 。

Next, taking the semiconductor layer 311 as an example of a P-type semiconductor, that is, taking a carrier as an example of an electron, the physical principle of the carrier providing layer 300 to raise the ratio of the number of cold carriers in the layer 100 to the total number of carriers in the layer 100 is described as an example.

Due to the physical properties of materials, when materials with different fermi surface positions are contacted, the fermi surfaces of the materials change towards a consistent direction, thereby driving the energy bands (including valence band and conduction band) of the materials to change, and thus introducing energy band dislocation between the multi-layer materials. The valence band of semiconductor layer 311, the valence band of conductor layer 312, and the fermi-plane of layer 100 (or semiconductor layer 313) are different, and contact in this order may result in the valence band and conduction band distributions shown in fig. 3A. Electrons in semiconductor layer 311 having energies below the valence band energy Ev of semiconductor layer 311 and above the conduction band energy of layer 100 (or semiconductor layer 313 and layer 100) may enter layer 100 (or semiconductor layer 313 and layer 100) by quantum tunneling. The energy of the electrons in this portion is lower than the energy Ev and the energy of some or all of the electrons in this portion is lower than the height of the schottky barrier in the off state of the schottky diode 10, i.e., the energy of the electrons in the portion of the electrons in which the energy Ev is lower than the height of the schottky barrier in the off state of the schottky diode 10. These electrons having energies below energy Ev and below the height of the schottky barrier when the schottky diode 10 is in the off state are cold electrons. Meanwhile, since the semiconductor layer 311 is a P-type semiconductor, electrons in the conduction band of the semiconductor layer 311 are fewer, and thus the semiconductor layer 311 has less influence on the hot carrier concentration in the layer 100. In this manner, the ratio of the number of electrons in layer 100 to the total number of electrons in layer 100 may be increased.

In addition, electrons having energies higher than Leng Zailiu can be referred to as hot carriers. Wherein the hot carriers have a higher average kinetic energy than the cold carriers at zero electric field. Under zero electric field, when the hot carrier in layer 100 acquires enough kinetic energy, the confinement of the schottky barrier can be broken through and enter layer 200, forming leakage current in the off state of the diode. While Leng Zailiu has low average kinetic energy, can not overcome the constraint of the Schottky barrier, does not enter or rarely enters the layer 200 under the zero electric field, and quickly crosses the Schottky barrier and enters the layer 200 when the Schottky barrier is lowered, thereby realizing ultra-low (lower than 60 mV/dec) subthreshold swing.

In addition, when Leng Zailiu is an electron, the corresponding hot carrier is also an electron. When Leng Zailiu is a hole, the corresponding hot carrier is also a hole.

Specifically, as shown in fig. 3A, when the potential or potential of layer 200 is low, there is not a sufficiently high potential difference between layer 100 and layer 200, the schottky barrier height is high, and there are not enough high-state carriers in layer 100 that can cross the schottky barrier, so that the current between layer 100 and layer 200 is small, or there is only leakage current.

As shown in fig. 3B, when the potential of layer 200 increases, the potential difference between layer 100 and layer 200 increases, the schottky barrier height is low, so that cold carriers can quickly cross the schottky barrier and enter layer 200, thereby generating a large current between layer 100 and layer 200, i.e., the current between layer 100 and layer 200 increases rapidly, so that schottky diode 10 quickly enters an on state from an off state, exhibiting an ultra-low (below 60 mV/dec) subthreshold swing.

In addition, when the carriers are holes, the physical principle of increasing the ratio of the number of Leng Zailiu carriers to the total number of carriers in the layer 100 is similar to that described above, and will not be described here again.

In embodiment 2, the schottky diode 10 of the reverse bias structure B1 is used.

Referring to fig. 4, embodiment 2 provides a schottky diode 10 employing a reverse bias structure B1. In the reverse bias structure B1, the layer 100 is a metal layer, the layer 200 is a semiconductor layer, and the carrier providing layer 300 may be the semiconductor layer 300. Wherein semiconductor layer 300 and layer 200 are doped with impurities of different nature. That is, if the semiconductor layer 300 is a P-type semiconductor, the layer 200 is an N-type semiconductor. That is, if the semiconductor layer 300 is an N-type semiconductor, the layer 200 is a P-type semiconductor.

In one illustrative example of embodiment 2, the doping concentration of semiconductor layer 300 is greater than the doping concentration of layer 200. Alternatively, semiconductor layer 300 is a heavily doped semiconductor and layer 200 is a lightly doped semiconductor. Exemplary, the doping concentration of the semiconductor layer 300 is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of layer 200 is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

In one example, the doping concentration of the semiconductor layer 300 is 10 ²⁰ cm ^-3 . In one example, the doping concentration of the semiconductor layer 300 is 10 ^19.5 cm ^-3 . In one example, the doping concentration of the semiconductor layer 300 is 10 ^20.5 cm ^-3 . In one example, layer 200 has a doping concentration of 10 ^17.5 cm ^-3 . In one example, layer 200 has a doping concentration of 10 ¹⁷ cm ^-3 . In one example, layer 200 has a doping concentration of 10 ^16.5 cm ^-3 . In one example, layer 200 has a doping concentration of 10 ¹⁶ cm ^-3 . In one example, layer 200 has a doping concentration of 10 ^15.5 cm ^-3 。

In one illustrative example of embodiment 2, the material of the metal layer may be a metal, such as one or a combination of at least two of gold, silver, aluminum, platinum, and the like.

In one illustrative example of embodiment 2, the metal layer may be replaced with a silicide layer. The silicide layer may be made of metal silicide. Metal silicide refers to a compound of a metal (such as nickel, titanium, cobalt, lithium, calcium, magnesium, iron, chromium, etc.), and has excellent electrical and thermal conductivity. In one example, the silicide layer is made of NiSi ₂ 、TiSi ₂ 、CoSi ₂ One or a combination of at least two of the foregoing.

In one illustrative example of embodiment 2, the metal layer may be replaced by a semi-metal layer. The semi-metal layer is made of semi-metal. The close-spaced material between the conduction and valence bands of the semi-metal has a higher density of electron states near the fermi level than the insulator, while being much smaller than the metal. Graphene, three-dimensional Bi, na ₃ Bi、Cd ₃ As ₂ Carbon nanotubes, etc. are more typical semi-metals.

In one illustrative example of embodiment 2, the metal layer may be replaced with a cold metal layer. The material of the cold metal layer is cold metal (clod metal). Cold metals refer to a class of materials with a rapid decrease in electron state density near the fermi surface, e.g. NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ 、NbS ₂ 、TaS ₂ . Wherein NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ May be referred to as cold electron metals, and may provide electrons. Can be called cold hole metal, nbS ₂ 、TaS ₂ Holes may be provided.

In one illustrative example of embodiment 2, the metal layer may be replaced with a transition metal disulfide layer.

In one illustrative example of embodiment 2, as shown in fig. 4, schottky diode 10 further includes an ohmic contact layer. The ohmic contact layer serves to reduce resistance between the layer 200 and a device (e.g., a power supply or a driving circuit) to which the layer 200 is connected. Illustratively, the ohmic contact layer includes a semiconductor layer 411 and a conductor layer 412. Wherein the semiconductor layer 411 is located between the conductor layer 412 and the layer 200, and one side of the semiconductor layer 411 is in contact with the layer 200 and the other side is in contact with the conductor layer 412, thereby forming an ohmic contact layer.

Wherein the semiconductor layer 411 and the layer 200 are doped with impurities of the same nature. That is, if the layer 200 is an N-type semiconductor, the semiconductor layer 411 is also an N-type semiconductor. If layer 200 is a P-type semiconductor, semiconductor layer 411 is also a P-type semiconductor. And, the doping concentration of the semiconductor layer 411 is greater than that of the layer 200. Alternatively, the semiconductor layer 411 is a heavily doped semiconductor and the layer 200 is a lightly doped semiconductor. Exemplary, the doping concentration of the semiconductor layer 411 is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of layer 200 is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

Illustratively, the material of the conductor layer 412 may be metal. Such as gold, silver, aluminum, platinum, etc. The material of the conductive layer 412 may be silicide. The silicide may be a metal silicide. For example, niSi ₂ 、TiSi ₂ 、CoSi ₂ One or a combination of at least two of the foregoing.

Next, taking the semiconductor layer 300 as an example of a P-type semiconductor, that is, taking a carrier as an example of an electron, the example describes a physical principle that the carrier supply layer 300 raises the ratio of the number of cold carriers in the layer 100 to the total number of carriers in the layer 100.

Due to the physical properties of the materials, when materials with different Fermi surface positions are contacted, the Fermi surfaces of the materials change towards the consistent positions, thereby driving the energy band change of the materials and introducing energy band dislocation among the multiple layers of materials. The valence band of semiconductor layer 300 and the fermi surface of layer 100 are different, and contact between the two can lead to the valence band and conduction band distributions shown in fig. 5A. Electrons in semiconductor layer 300 having energies below the valence band energy Ev of semiconductor layer 300 and above the conduction band energy of layer 100 may enter layer 100 by quantum tunneling. The energy of the electrons in this portion is lower than the energy Ev and the energy of some or all of the electrons in this portion is lower than the height of the schottky barrier in the off state of the schottky diode 10, i.e., the energy of some or all of the electrons in the electrons having an energy Ev is lower than the height of the schottky barrier in the off state of the schottky diode 10. These electrons having energies below energy Ev and below the height of the schottky barrier when the schottky diode 10 is in the off state are cold electrons. Meanwhile, since the semiconductor layer 300 is a P-type semiconductor, electrons in the conduction band thereof are less, and thus the semiconductor layer 300 has less influence on the hot carrier concentration in the layer 100. In this manner, the ratio of the number of electrons in layer 100 to the total number of electrons in layer 100 may be increased.

In addition, electrons having energies higher than Leng Zailiu can be referred to as hot carriers. Wherein the hot carriers have a higher average kinetic energy than the cold carriers at zero electric field. Under zero electric field, when the hot carrier in layer 100 acquires enough kinetic energy, the confinement of the schottky barrier can be broken through and enter layer 200, forming leakage current in the off state of the diode. While Leng Zailiu has low average kinetic energy, can not overcome the constraint of the Schottky barrier, does not enter or rarely enters the layer 200 under the zero electric field, and can tunnel through the Schottky barrier to enter the layer 200 by quantum tunneling effect when the Schottky barrier width is reduced, thereby realizing ultra-low (lower than 60 mV/dec) subthreshold swing.

Specifically, as shown in fig. 5A, when the potential or potential of layer 200 is low, and there is not a sufficiently high potential difference between layer 100 and layer 200, the schottky barrier is wider and fewer carriers tunnel through the schottky barrier, so that the current between layer 100 and layer 200 is small, or there is only leakage current.

As shown in fig. 5B, when the potential of layer 200 increases, the potential difference between layers 100 and 200 increases, and the width of the schottky barrier decreases, so that cold carriers can tunnel through the schottky barrier by quantum tunneling effect, into layer 200, thereby generating a large current between layer 100 and layer 200, i.e., the current between layer 100 and layer 200 increases rapidly, so that schottky diode 10 rapidly goes from an off state to an on state, exhibiting an ultra-low (below 60 mV/dec) subthreshold swing.

In embodiment 3, the schottky diode 10 of the forward bias structure A2 is used.

Referring to fig. 6, embodiment 3 provides a schottky diode 10 employing a forward bias structure A2. In the forward bias structure A2, the layer 100 is a semiconductor layer, the layer 200 is a metal layer, and the carrier supply layer 300 may include a layer 611. The material of layer 611 may be semi-metallic or cold metal. Semi-metals are a class of materials that are closely spaced between the conduction and valence bands, with states near the fermi level having a density of states greater than that of the insulator and much less than that of the metal. Cold metals are a class of materials with a rapid decrease in electron density near the fermi surface.

For convenience of description, hereinafter, when the half metal and the cold metal are not particularly distinguished, they may be simply referred to as cold source metal.

Fig. 7 shows carrier state densities of a metal and a cold source metal at different energies. The ordinate in fig. 7 is energy, and the constant is carrier state density. The carrier state density represents the carrier density or duty cycle with a corresponding energy. As shown in fig. 7, the proportion of carriers having energy lower than the schottky barrier height in the cold source metal is higher than that in the metal. The schottky barrier height herein refers to a height of the schottky barrier when the schottky diode 10 is in an off state. In other words, the density or duty cycle of charge carriers in cold source metals is greater than that of metals. Thus, layer 611 may provide more cold carriers to layer 100, thereby increasing the ratio of the number of cold carriers in layer 100 to the total number of carriers in layer 100.

The material of layer 611 varies depending on the semiconductor type of layer 100.

When the layer 100 is an N-type semiconductor, the material of the layer 611 may be NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ At least one of the isocool metals can be P-type doped semi-metal or NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ A mixture of an isocooled metal and a P-doped semi-metal. Wherein the semi-metal can be graphene,Three-dimensional Bi, na ₃ Bi、Cd ₃ As ₂ At least one of the following. The P-type doping can alter the position of the fermi surface of the semi-metallic material to yield a P-type doped semi-metal with the proper carrier state density to produce layer 611.

When the layer 100 is an N-type semiconductor, the material of the layer 611 may be NbS ₂ ,TaS ₂ At least one of the isocooled metals can be N-type doped semi-metal or NbS ₂ ,TaS ₂ A mixture of an isocooled metal and an N-doped semi-metal. Wherein the semi-metal can be graphene, three-dimensional Bi, na ₃ Bi、Cd ₃ As ₂ At least one of the following. The N-type doping can alter the position of the fermi surface of the semi-metallic material to yield an N-type doped semi-metal with the proper carrier state density to produce layer 611.

In one illustrative example of embodiment 3, the metal layer may be replaced by a silicide layer. The silicide layer may be specifically described above, and will not be described herein.

In one illustrative example of embodiment 3, the metal layer may be replaced with a transition metal disulfide layer.

In one illustrative example of embodiment 3, as shown in fig. 6, the carrier providing layer 300 may include a semiconductor layer 612. Semiconductor layer 612 is located between layer 611 and layer 100 to reduce the resistance between layer 611 and layer 100. Wherein semiconductor layer 612 and layer 100 are doped with impurities of the same nature, and the doping concentration of semiconductor layer 612 is greater than the doping concentration of layer 100. Alternatively, semiconductor layer 612 is a heavily doped semiconductor and layer 100 is a lightly doped semiconductor. Exemplary, the doping concentration of the semiconductor layer 612 is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of layer 100 is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

In embodiment 3, carrier providing layer 300 may provide more cold carriers to the source terminal (i.e., layer 100) of schottky diode 10, increasing the ratio of the number of cold carriers in the source terminal to the total number of carriers in the source terminal. At lower potentials of the layer 200 of the schottky diode, i.e., when the schottky diode 10 is in the off state, the Leng Zailiu sub-does not cross or tunnel across the schottky barrier, or only very few cold carriers cross or tunnel across the schottky barrier. When the potential of the layer 200 of the schottky diode increases, i.e., the schottky diode 10 goes from an off state to an on state, the Leng Zailiu sub-rapidly crosses or tunnels through the schottky barrier, causing a rapid increase in current, speeding up the switching speed of the schottky diode 10 from the off state to the on state, exhibiting an ultra-low (below 60 mV/dec) subthreshold swing.

In embodiment 4, the schottky diode 10 of the reverse bias structure B2 is used.

Referring to fig. 8, embodiment 4 provides a schottky diode 10 employing a reverse bias structure B2. In the reverse bias structure B2, the layer 100 and the carrier supply layer 300 are the same layer, and the layer 200 is a semiconductor layer. The material of layer 100 or carrier-providing layer 300 may be a cold metal or a semi-metal.

As noted above, the density or duty cycle of charge carriers is greater in cold metals and semi-metals than in metals. I.e., the proportion of carriers in the cold metal and semi-metal that have energies below the schottky barrier height is higher. The schottky barrier height herein refers to a height of the schottky barrier when the schottky diode 10 is in an off state. Thus, layer 100 has more cold carriers, i.e., the material of layer 100 is cold metal or semi-metal, increasing the ratio of the number of cold carriers in layer 100 to the total number of carriers in layer 100.

In one illustrative example of embodiment 4, schottky diode 10 further includes: an ohmic contact layer in contact with layer 200. The ohmic contact layer serves to reduce resistance between the layer 200 and a device (e.g., a power supply or a driving circuit) to which the layer 200 is connected. Illustratively, the ohmic contact layer includes a semiconductor layer 811 and a conductor layer 812. Wherein the semiconductor layer 811 is located between the conductor layer 812 and the layer 200, and one side of the semiconductor layer 811 is in contact with the layer 200 and the other side is in contact with the conductor layer 812, thereby forming an ohmic contact layer.

Wherein semiconductor layer 811 and layer 200 are doped with impurities of the same nature. That is, if the layer 200 is an N-type semiconductor, the semiconductor layer 811 is also an N-type semiconductor. If it isThe layer 200 is a P-type semiconductor, and the semiconductor layer 811 is also a P-type semiconductor. And, the doping concentration of the semiconductor layer 811 is greater than the doping concentration of the layer 200. Alternatively, semiconductor layer 811 is a heavily doped semiconductor and layer 200 is a lightly doped semiconductor. Illustratively, the semiconductor layer 811 has a doping concentration of 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of layer 200 is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

Illustratively, the material of the conductor layer 812 may be metal. Such as gold, silver, aluminum, platinum, etc. The material of the conductive layer 812 may be silicide. The silicide may be a metal silicide. For example, niSi ₂ 、TiSi ₂ 、CoSi ₂ One or a combination of at least two of the foregoing.

In example 4, the charge carrier occupancy in the source terminal (i.e., layer 100) of schottky diode 10 was compared. At lower potentials of the layer 200 of the schottky diode, i.e., when the schottky diode 10 is in the off state, the Leng Zailiu sub-does not cross or tunnel across the schottky barrier, or only very few cold carriers cross or tunnel across the schottky barrier. When the potential of the layer 200 of the schottky diode increases, i.e., the schottky diode 10 goes from an off state to an on state, the Leng Zailiu sub-rapidly crosses or tunnels through the schottky barrier, causing a rapid increase in current, speeding up the switching speed of the schottky diode 10 from the off state to the on state, exhibiting an ultra-low (below 60 mV/dec) subthreshold swing.

The above examples describe the structural form of the schottky diode 10, and it is understood that the above description is a schematic structure of the schottky diode 10, and connection relations, contact relations, and the like of the respective components are schematically described. The above description is not limited to the specific shape of the schottky diode 10 and the specific shape of the components in the schottky diode 10 and the specific manner of connection and contact. In practical production applications, schottky diode 100 may be implemented as a vertical structure, a horizontal structure, a stacked structure, etc.

The respective semiconductor layers in the schottky diode 10 described in the above embodiments may be obtained by doping impurities in the intrinsic semiconductor layer. Wherein the intrinsic semiconductor layer is made of a material capable of realizing the above-mentioned energy band dislocation. The material of the intrinsic semiconductor layer used in the embodiment of the application can be any one of germanium, germanium-silicon, gallium nitride, indium-gallium-arsenic and carbon nano-tube, and can also be the combination of two or more of germanium, germanium-silicon, gallium nitride, indium-gallium-arsenic and carbon nano-tube.

In some embodiments, the semiconductor layer forming the schottky barrier in the schottky diode 10 may be replaced with a carbon nanotube layer and the metal layer may be replaced with a graphene layer. That is, the carbon nanotube layer may replace the semiconductor layer for forming the schottky barrier, and the graphene layer may replace the metal layer for forming the schottky barrier. I.e. the interface between the carbon nanotube layer and the graphene layer forms a schottky barrier of the schottky diode 10. The carbon nano tube has high electrical mobility and atomic layer quasi-one-dimensional structure, and the mobility exceeds 1500cm ² The saturation speed of the catalyst can reach 3 multiplied by 10 ⁷ cm/s, so that the Schottky diode has larger on-current after entering an on-state. The carbon nano tube material has better ductility, is easy to be compatible with various device shapes, and is beneficial to three-dimensional (3D) integration of devices.

In one example of these embodiments, the carbon nanotube layer is made of carbon nanotubes doped with impurities, the graphene layer is made of graphene doped with impurities, and the carbon nanotubes and the graphene are doped with impurities of different properties. Therefore, the fermi surface of the carbon nanotube layer and the fermi surface of the graphene layer can be regulated and controlled by doping impurities into the carbon nanotube and the graphene, so that energy band dislocation between the carbon nanotube layer and the graphene layer is realized, and a Schottky barrier is generated.

In another example of these embodiments, the carbon nanotube layer is made of carbon nanotubes, and the graphene layer is made of graphene. Additional gates (not shown) may be added to the schottky diode 10 through which the fermi surface of the carbon nanotube layer and the fermi surface of the graphene layer are modulated, achieving energy band dislocation between the carbon nanotube layer and the graphene layer, and creating a schottky barrier. In this example, a doping process is not required, and the fermi surface of the carbon nanotube layer and the fermi surface of the graphene layer are regulated by the gate electrode, a higher degree of regulation flexibility can be achieved.

The above examples describe the structure, materials, and principles of functional implementation of the schottky diode 10. Next, the preparation scheme of the schottky diode 10 is described as an example.

Fig. 9A shows a preparation scheme of the schottky diode 10 using the forward bias structure A1, and the flow is specifically as follows.

An intrinsic semiconductor, i.e., a semiconductor which has not been doped with impurities, is obtained as a substrate (substrate). The intrinsic semiconductor layer may be any one of germanium, germanium silicon, gallium nitride, indium gallium arsenic, and carbon nanotubes.

A corresponding impurity is implanted on the intrinsic semiconductor and an annealing activation is performed to prepare the semiconductor layer 311. In this embodiment of the present application, "implantation" may be understood as "doping", i.e. the implanted impurity is a doping impurity.

A conductor layer 312 is grown on the semiconductor layer 311.

A semiconductor layer 313 may be deposited on the conductor layer 312. This step is optional, and may or may not prepare semiconductor layer 313.

Next, the layer 100 may be deposited over the semiconductor layer 313 (in the case of preparing the semiconductor layer 313), or the conductor layer 312 (in the case of not preparing the semiconductor layer 313), and an annealing treatment may be performed so that the layer 100 and the semiconductor layer 313 are crystallized and doped impurities are activated.

Layer 200 is prepared on layer 100. Then, etching is performed. Wherein the upper surface of the semiconductor layer 311 is etched. The upper surface of the semiconductor layer 311 refers to the surface of the semiconductor layer 311 facing away from the intrinsic semiconductor.

Then, a photoresist may be deposited and an overlay may be performed on the prepared portion to expose a partial region of the upper surface of the semiconductor layer 311, and an electrode may be deposited on the exposed region. Wherein the electrode is in contact with the semiconductor layer 311 but not with the conductor layer 312. The electrode may be a metal electrode.

Finally, the photoresist is washed away, and the schottky diode 10 adopting the forward bias structure A1 can be prepared.

The materials of the layers in the preparation process shown in fig. 9A may refer to the description of the embodiment shown in fig. 2, and are not repeated here.

Fig. 9B shows a preparation scheme of the schottky diode 10 using the reverse bias structure B1, and the flow thereof is specifically as follows.

An intrinsic semiconductor, i.e., a semiconductor which has not been doped with impurities, is obtained as a substrate. The intrinsic semiconductor layer may be any one of germanium, germanium silicon, gallium nitride, indium gallium arsenic, and carbon nanotubes.

A corresponding impurity is implanted on the intrinsic semiconductor and annealed to prepare the semiconductor layer 300, i.e., the carrier-providing layer 300.

Layer 100 is grown over semiconductor layer 300.

Layer 200 may be deposited over layer 100.

Next, a semiconductor layer 411 may be deposited over the layer 200. Wherein this step is optional.

An annealing process may be performed to crystallize the layer 200 and the semiconductor layer 411 and activate the doped impurities.

In the case of preparing the semiconductor layer 411, the conductor layer 412 may be prepared on the semiconductor layer 411.

Then, etching is performed. Wherein the upper surface of the semiconductor layer 300 is etched. Wherein, the upper surface of the semiconductor layer 300 refers to the side of the semiconductor layer 300 facing away from the intrinsic semiconductor.

Then, a photoresist may be deposited and an overlay may be performed on the prepared portion to expose a partial region of the upper surface of the semiconductor layer 300, and an electrode may be deposited on the exposed region. Wherein the electrodes are in contact with the semiconductor layer 300 and not with the layer 100. The electrode may be a metal electrode.

Finally, the photoresist is washed away, and the schottky diode 10 using the reverse bias structure B1 can be manufactured.

The materials of the layers in the preparation process shown in fig. 9B may be referred to the above description of the embodiment shown in fig. 4, and will not be repeated here.

Fig. 10A shows another fabrication scheme of the schottky diode 10 using the forward bias structure A1, which can fabricate the schottky diode 10 of a horizontal structure. In the schottky diode 10 having the horizontal structure, the conductor layer 312 may be stacked over the semiconductor layer 311 and the semiconductor layer 313, or may be interposed between the semiconductor layer 311 and the semiconductor layer 313. The scheme flow is specifically as follows.

Silicon (silicon on insulator, SOI) on an insulating substrate is obtained. As shown in fig. 10A, the SOI consists of a top silicon layer, an oxide layer, and a backing substrate, which are connected in sequence.

A corresponding impurity may be implanted at one side of the top silicon layer to prepare the semiconductor layer 311.

Then, in a region of the top silicon located beside the semiconductor layer 311 and in contact with the semiconductor layer 311, a corresponding impurity is implanted to prepare a semiconductor layer 313.

Thereafter, in the region of the top layer silicon where the impurity implantation has not been performed, the corresponding impurity is implanted to prepare layer 100.

Layer 200 may be deposited over layer 100.

The conductor layer 312 may be prepared on the semiconductor layer 311 and the semiconductor layer 313. The semiconductor layer 311 and the semiconductor layer 313 are in contact with the prepared semiconductor layer 312, whereby the semiconductor layer 312 is stacked over the semiconductor layer 311 and the semiconductor layer 313.

Finally, an electrode may be prepared on the semiconductor layer 311. Wherein the prepared electrode is in contact with the semiconductor layer 311 and is not in contact with the conductor layer 312.

Thus, the schottky diode 10 using the forward bias structure A1 can be manufactured.

The materials of the layers in the preparation process shown in fig. 10A may be referred to the above description of the embodiment shown in fig. 2, and will not be repeated here.

Fig. 10B shows another fabrication scheme of the schottky diode 10 using the reverse bias structure B1, which can fabricate the schottky diode 10 of a horizontal structure. In the schottky diode 10 of the horizontal structure, the layer 100 may overlap the semiconductor layer 300 and the layer 200, or may be interposed between the semiconductor layer 300 and the layer 200. The scheme flow is specifically as follows.

The SOI is obtained and a corresponding impurity is implanted at one side of the top silicon of the SOI to prepare the semiconductor layer 300.

Then, in the region of the top silicon located beside the semiconductor layer 300 and in contact with the semiconductor layer 300, the corresponding impurities are implanted to prepare the layer 200.

Thereafter, in a region of the top-layer silicon where impurity implantation has not been performed, a corresponding impurity is implanted to prepare the semiconductor layer 411.

A conductor layer 412 may be deposited on the semiconductor layer 411.

Layer 100 may be fabricated on semiconductor layer 300 and layer 200. Both the semiconductor layer 300 and the layer 200 are in contact with the prepared layer 100, whereby the layer 100 overlies the semiconductor layer 300 and the layer 200.

Finally, an electrode may be prepared on the semiconductor layer 300. Wherein the prepared electrode is in contact with the semiconductor layer 300 and is not in contact with the layer 100.

Thus, the schottky diode 10 using the reverse bias structure B1 can be manufactured.

The materials of the layers in the preparation process shown in fig. 10B may be referred to the above description of the embodiment shown in fig. 4, and will not be repeated here.

Fig. 11 shows yet another fabrication scheme of the schottky diode 10 using the reverse bias structure B1, which is specifically performed as follows.

A corresponding impurity is implanted on the intrinsic semiconductor and annealed to produce layer 200.

Layer 100 is grown on layer 200 and semiconductor layer 300 is deposited on layer 100 and annealed.

Then, the layer 100 and the semiconductor layer 300 on a partial region of the layer 200 are removed by photolithography or etching to expose the partial region. Then, the partial region is further implanted with a corresponding impurity and annealed to prepare the semiconductor layer 411 having a higher doping concentration than the layer 200, wherein the semiconductor layer 411 is not in contact with the layer 100.

Then, a conductor layer 412 is prepared over the semiconductor layer 411. Wherein conductor layer 412 is not in contact with layer 200.

The materials of the layers in the preparation process shown in fig. 11 may be referred to the above description of the embodiment shown in fig. 4, and will not be repeated here.

Fig. 12 shows a preparation scheme of the schottky diode 10 using the forward bias structure A2, which is specifically described as follows.

A corresponding impurity is implanted on the intrinsic semiconductor and annealed to produce layer 100.

A semiconductor layer 612 is deposited over layer 100 and a layer 611 is grown over semiconductor layer 612.

Layer 611 and semiconductor layer 612 are etched to expose a partial region of layer 100. Layer 200 is then locally grown over the exposed areas of layer 100. Wherein layer 200 is in contact with layer 100 and not with semiconductor layer 612.

Electrodes are prepared on layer 611.

Thus, the schottky diode 10 using the forward bias structure A2 is obtained.

The materials of the layers in the preparation process shown in fig. 12 may be referred to the above description of the embodiment shown in fig. 6, and will not be repeated here.

Fig. 13 shows a preparation scheme of the schottky diode 10 using the reverse bias structure B2, which is specifically described as follows.

A corresponding impurity is implanted on the intrinsic semiconductor and annealed to prepare a semiconductor layer 811.

Layer 200 is deposited over semiconductor layer 811 and layer 100 is grown over layer 200.

Layer 100 and layer 200 are etched to expose a portion of the area of semiconductor layer 811. Then, a conductor layer 812 is locally grown on the exposed region of the semiconductor layer 811. Wherein conductor layer 812 is in contact with semiconductor layer 811 but not with layer 200.

Electrodes may be prepared on layer 100.

Thereby, the schottky diode 10 using the reverse bias structure B2 is obtained.

The materials of the layers in the preparation process shown in fig. 13 may be referred to the above description of the embodiment shown in fig. 8, and will not be repeated here.

The preparation method described above has simple process steps, is easy for industrial operation, and can efficiently prepare the schottky diode 10.

The embodiment of the present application performs a simulation test on the switching ratio (i.e., the ratio of the current in the on state to the current in the off state of the diode) of the schottky diode 10 of the forward bias structure A1 to obtain the volt-ampere characteristic (IV) curve as shown in fig. 14A, and it can be seen that the schottky diode 10 of the forward bias structure A1 has a steeper IV curve slope compared with the conventional schottky diode.

The embodiment of the present application performs a simulation test on the switching ratio of the schottky diode 10 of the reverse bias structure B1 to obtain the volt-ampere characteristic (IV) curve as shown in fig. 14B, and it can be seen that the schottky diode 10 of the reverse bias structure B1 has a steeper IV curve slope compared with the conventional schottky diode.

It will be appreciated that the steeper the slope of the IV curve, the smaller the subthreshold swing and the larger the switching ratio. Therefore, the schottky diode 10 provided by the embodiment of the application has smaller subthreshold swing and larger on-off ratio, and can rapidly enter the on state from the off state. When the schottky diode 10 is used as a microelectronic switching element of an electronic device, the operation delay of the electronic device can be reduced.

The schottky diode 10 provided by the embodiment of the application can be applied to various power circuits, such as an inverter circuit, a rectifying circuit, a freewheel circuit and the like.

Fig. 15 shows a power circuit which can convert direct current into alternating current. The power circuit may be a three-phase inverter circuit including three legs for generating U-, V-, W-phases. Two switching elements can be arranged on each bridge arm in series, and direct current can be converted into alternating current by controlling the on and off of the switching elements on different bridge arms, so that the alternating current motor can be driven. The switching element on the bridge arm may be composed of a schottky diode 10 and a field effect transistor. The field effect transistor may be an insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT), for example.

It is to be understood that fig. 15 is for exemplary purposes only and is not intended to be limiting of the schottky diode 10. The schottky diode 10 may have other applications, not specifically illustrated herein.

It should be understood that the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A schottky diode, comprising:

A first layer;

a second layer in contact with the first layer, wherein the first layer is one of a semiconductor layer and a metal layer, the second layer is the other of the semiconductor layer and the metal layer, and a schottky barrier exists between the first layer and the second layer;

a carrier providing layer coupled to the first layer for increasing a duty cycle of a number of first carriers in the first layer to a total number of carriers in the first layer; wherein the energy of the first carrier is lower than the height of the schottky barrier when the schottky diode is in an off state;

wherein when the schottky diode goes from an off-state to an on-state, the height of the schottky barrier decreases such that the first carriers cross the schottky barrier and enter the second layer; alternatively, the width of the schottky barrier is reduced such that the first carriers tunnel through the schottky barrier into the second layer.

2. The schottky diode of claim 1 wherein,

the semiconductor layer is obtained by doping impurities into an intrinsic semiconductor layer, and the intrinsic semiconductor layer is made of at least one of germanium, germanium-silicon, gallium nitride, indium-gallium-arsenic and carbon nano tubes; or alternatively, the process may be performed,

The semiconductor layer is replaced by a carbon nanotube layer.

3. The schottky diode of claim 1 or 2 wherein the first layer is the semiconductor layer and the second layer is the metal layer, the carrier providing layer comprising a first semiconductor layer and a first conductor layer, wherein the first conductor layer is located between the first semiconductor layer and the first layer, the first semiconductor layer and the first layer being doped with impurities of different properties.

4. The schottky diode of claim 3 wherein the carrier-providing layer further comprises a second semiconductor layer located between the first conductor layer and the first layer, the second semiconductor layer and the first layer being doped with impurities of the same nature, and the second semiconductor layer having a doping concentration greater than the doping concentration of the first layer.

5. The schottky diode of claim 4 wherein the doping concentration of the second semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the first layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

6. The schottky diode of any of claims 3-5 wherein the first semiconductor layer has a doping concentration of 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the first layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

7. The schottky diode of any of claims 3-6 wherein the first conductor layer is a metal or a silicide; alternatively, the metal layer is replaced by a silicide layer or a transition metal disulfide layer.

8. The schottky diode of claim 1 wherein the first layer is the metal layer and the second layer is the semiconductor layer, the carrier providing layer comprising a third semiconductor layer, the third semiconductor layer and the second layer being doped with impurities of different properties.

9. The schottky diode of claim 8 wherein the doping concentration of the third semiconductor layer is greater than the doping concentration of the second layer.

10. The schottky diode of claim 9 wherein the doping concentration of the third semiconductor layer is 10 ¹⁹ -10 ²¹ cm ^-3 The doping concentration of the second layer is 10 ¹⁵ -10 ¹⁸ cm ^-3 。

11. The schottky diode of any of claims 8-10, further comprising: and an ohmic contact layer in contact with the second layer.

12. The schottky diode of any of claims 8-11 wherein the metal layer is replaced by any of a semi-metal layer, a cold metal layer, a silicide layer, a transition metal disulfide layer.

13. The schottky diode of claim 1 wherein the first layer is the semiconductor layer, the second layer is the metal layer, the carrier providing layer comprises a third layer, and the third layer is a cold metal layer or a semi-metal layer.

14. The schottky diode of claim 13 wherein the carrier-providing layer further comprises a fourth semiconductor layer, the fourth semiconductor layer being located between the third layer and the first layer, the fourth semiconductor layer and the first layer being doped with impurities of the same nature, and the fourth semiconductor layer having a doping concentration greater than the doping concentration of the first layer.

15. The schottky diode of claim 13 or 14 wherein,

the first layer is made of N-type semiconductor, and the third layer is made of NbSe ₂ 、NbTe ₂ 、TaSe ₂ 、TaTe ₂ At least one of P-doped semi-metals; or alternatively, the process may be performed,

the first layer is made of P-type semiconductor, and the third layer is made of NbS ₂ ,TaS ₂ At least one of an N-doped semi-metal.

16. The schottky diode of any of claims 13-15 wherein the metal layer is replaced by a silicide layer or a transition metal disulfide layer.

17. The schottky diode of claim 1 wherein the first layer and the carrier providing layer are the same layer and the second layer is a semiconductor layer, wherein the material of the first layer is a cold metal layer or a semi-metal layer.

18. The schottky diode of claim 17 further comprising: and an ohmic contact layer in contact with the second layer.

19. A power circuit comprising a schottky diode as defined in any of claims 1-18 and a field effect transistor.