CN116845107A - 碳化硅半导体元件 - Google Patents

碳化硅半导体元件 Download PDF

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CN116845107A
CN116845107A CN202211135375.XA CN202211135375A CN116845107A CN 116845107 A CN116845107 A CN 116845107A CN 202211135375 A CN202211135375 A CN 202211135375A CN 116845107 A CN116845107 A CN 116845107A
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silicon carbide
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颜诚廷
洪湘婷
许甫任
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Jisi Creative Co ltd
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Abstract

一种碳化硅半导体元件，具有一主动区以及一在一平面视角上围绕该主动区的终端区。该碳化硅半导体元件包括一碳化硅基板、一漂移层、一绝缘层、一多晶硅层、一设置于该多晶硅层上的层间介电层以及一金属层。该多晶硅层包括一设置在该主动区上方的第一部分以及一设置于该终端区上方的第二部分。该金属层包括一设置在该主动区上方的第一部分以及一设置于该终端区上方的第二部分。该多晶硅层的该第二部分以及该金属层的该第二部分中的至少一个被配置为电连接至一栅极以及一源极中的至少一个。

Description

碳化硅半导体元件
技术领域
本发明涉及一种碳化硅半导体元件，且特别涉及一种碳化硅功率半导体元件。
背景技术
功率半导体元件基于尺寸的限制，通常采用接面终端结构(junctiontermination structure)来避免功率半导体元件的边缘产生高电场集中，以提高崩溃电压并降低漏电流。碳化硅的宽能隙可以使碳化硅功率元件以较薄的漂移层承受较高的电压，其中，最常用的边缘终端(edge termination)包括浮接防护环(floating guard rings，FGR)以及接面终端延伸(junction termination extension，JTE)。浮接防护环(FGR)通常是多个分离地形成在n型漂移层的上表面的p型掺杂环，且围绕在碳化硅功率元件的主动区的边缘。而接面终端延伸(JTE)通常是一个或多个不同掺杂浓度的p型轻掺杂区，该些p型轻掺杂区是部分地重迭且围绕在碳化硅功率元件的主动区的边缘。边缘终端结构占据碳化硅功率元件相当大的面积，若碳化硅金属氧化物半导体场效晶体管(SiC MOSFET)的导通电阻较高，则边缘终端结构占芯片总面积的比例会因为主动区的面积较小而更大。此外，漂移层的掺杂浓度及厚度也会影响碳化硅功率元件的崩溃电压，举例来说，具有相同主动区以及端接设计的碳化硅金属氧化物半导体场效晶体管，当漂移层的掺杂浓度较高且漂移层厚度较低时，其导通电阻会较低。
然而，在掺杂浓度较高且漂移层厚度较薄时，崩溃电压会降低，而边缘终端结构在提高崩溃电压方面越有效，碳化硅功率元件的性能就越好。
发明内容
根据本发明一实施例的一碳化硅半导体元件包括：一碳化硅基板，具有一第一导电类型；一漂移层，具有该第一导电类型且设置于碳化硅基板上；一主动区，形成于该漂移层，该主动区包括多个晶体管单元；一终端区，形成于该漂移层且围绕该主动区；一绝缘层，设置于该漂移层上；一多晶硅层，设置于该绝缘层上，该多晶硅层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分；一层间介电层，设置于该多晶硅层上；以及一金属层，设置于该层间介电层上，该金属层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分；其中，该多晶硅层的该第二部分以及该金属层的该第二部分中的至少一个被配置为电连接至一栅极以及一源极中的至少一个。
根据本发明另一实施例的一碳化硅半导体元件包括：一碳化硅基板，具有一第一导电类型；一漂移层，具有该第一导电类型且设置于碳化硅基板上；一主动区，形成于该漂移层，该主动区包括多个晶体管单元；一终端区，形成于该漂移层且围绕该主动区；一绝缘层，设置于该漂移层上；一多晶硅层，设置于该绝缘层上，该多晶硅层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分，该多晶硅层的该第二部分被配置为连接至一栅极以及一源极中的至少一个；一层间介电层，设置于该多晶硅层上；以及一金属层，设置于该层间介电层上。
根据本发明又一实施例的一碳化硅半导体元件包括：一碳化硅基板，具有一第一导电类型；一漂移层，具有该第一导电类型且设置于碳化硅基板上；一主动区，形成于该漂移层，该主动区包括多个晶体管单元；一终端区，形成于该漂移层且围绕该主动区；一绝缘层，设置于该漂移层上；一多晶硅层，设置于该绝缘层上；一层间介电层，设置于该多晶硅层上；一金属层，设置于该层间介电层上，该金属层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分，该金属层的该第二部分被配置为连接至一栅极以及一源极中的至少一个。
附图说明
图1为本发明第一实施例的碳化硅半导体元件的示意性平面视图。
图2为本发明第一实施例的碳化硅半导体元件的截面示意图。
图3为本发明第二实施例的碳化硅半导体元件的截面示意图。
图4为本发明第三实施例的碳化硅半导体元件的截面示意图。
图5为本发明第四实施例的碳化硅半导体元件的截面示意图。
图6为本发明第五实施例的碳化硅半导体元件的截面示意图。
具体实施方式
应当理解的是，尽管在本文中使用「第一」、「第二」等用语来描述各种元件，但该些用语并非用于限制该些元件。该些用语仅用于区分一个元件与另一个元件。例如，可将第一元件解释为第二元件，类似地，也可将第二元件解释为第一元件，而不脱离本发明的范围。
如本文所用的用语「及/或」包括任何一个或多个相关列出的项目及其所有组合。
还应理解的是，当元件诸如层、部分、区域或基板被称为「在…之上」、「覆盖」或「在…上方」另一个元件时，它可以直接在该元件之上、直接覆盖该元件或直接在该元件上方；或中间也可能存在其他元件。相反地，当一个元件被称为「直接在…之上」、「直接覆盖」或「直接在…上方」另一个元件上时，不存在中间元件。同样，还将理解，当一个元件被称为「连接」或「耦接」到另一个元件时，它可以直接连接或耦接到另一个元件，或者可以存在中间元件。相反，当一个元件被称为「直接连接」或「直接耦接」到另一个元件时，不存在中间元件。
此处可以使用诸如「高于」、「低于」、「上方」、「下方」、「水平」、「横向」或「垂直」等相对用语来描述附图中的一个元件、层、部分或区域与另一个元件、层、部分或区域的关系。应当理解的是该些用语与上述的那些用语意旨在涵盖除了图中描绘的方向之外的元件的不同方向。
在本文中，对各种实施例的描述中所使用的用语只是为了描述特定示例的目的，而并非旨在进行限制。除非上下文另外明确地表明，或刻意限定元件的数量，否则本文所用的单数形式「一」、「该」也包含复数形式。将进一步理解，用语「包括」及/或「包含」在本文中使用时指出了所叙述的特征、元件及/或组件的存在，但不排除一个或多个其他特征、元件、组件及/或它们的群组的添加或存在。不定冠词和定冠词应包括复数和单数，除非从上下文中清楚地看出相反的情况。
参阅图1，为本发明第一实施例的碳化硅半导体元件100的平面视图。该碳化硅半导体元件100被配置为一场效晶体管(例如MOSFET)，该碳化硅半导体元件100包括一栅极、一漏极以及一源极，其中，在该漏极以及该源极之间流动的电流(Id)可以通过施加在该栅极以及该源极之间的偏压(Vgs)来控制。该碳化硅半导体元件100包括一主动区110，该主动区110被设置于一碳化硅基板的一中心区域，该碳化硅基板为一半导体层，沿着该主动区110的一外周边缘部分形成有一终端区，该终端区为具有圆角的方形环状，该终端区包括一主接面区120以及一相邻该主接面区120的边缘区130。
参阅图2，为本发明第一实施例的碳化硅半导体元件100的截面示意图，是沿图1的A-A剖面线。
该碳化硅半导体元件100包括一碳化硅基板101、一漂移层102、多个晶体管单元103、一绝缘层104、一多晶硅层105、一层间介电层106以及一金属层107。
该碳化硅基板101具有一第一导电类型(例如n型)。该漂移层102设置在该碳化硅基板101上并且可具有该第一导电类型。该晶体管单元103形成在该漂移层102中。每个该晶体管单元103包括一第一阱区103a、一源区103b以及一掺杂区103c。该第一阱区103a形成在该漂移层102中并且可具有一第二导电类型(例如p型)。该源区103b形成在该第一阱区103a中并且可具有该第一导电类型。该掺杂区103c形成于该第一阱区103a中并且被该源区103b包围。该掺杂区103c可具有该第二导电类型。
该晶体管单元103实质上是均匀地设置在该主动区110的一表面。在一优选实施例中，该晶体管单元103被配置为形成一金属氧化物半导体场效晶体管(MOSFET)元件。然而，该碳化硅半导体元件100可以是任何类型的元件，例如双注入场效晶体管(DIMOSFET)、沟槽式金属氧化物半导体场效晶体管、绝缘栅极双极性晶体管(IGBT)等。
该主接面区120以及该边缘区130是位于该主动区110以及该碳化硅半导体元件100的一端部之间的区域，并围绕在该主动区110的一边缘。该主接面区120包括一第二阱区108，该边缘区130包括多个保护环109。该第二阱区108具有该第二导电类型，该第二阱区108以及该保护环109于该漂移层102内延伸并环绕该主动区110。该主接面区120以及该边缘区130是形成在该漂移层102的一边缘终端结构，以降低该碳化硅基板101在一正面的电场并维持一阻隔电压。该阻隔电压是一额定极限电压，在该额定极限电压下不会有操作错误或元件损坏的情形发生。该阻隔电压通常低于发生一雪崩效应(avalanche effect)的元件的实际崩溃电压。例如，对于额定阻隔电压为650V的SiC MOSFET，其崩溃电压可能在660V到800V之间，具体取决于所需的操作裕度(operation margin)。该保护环109形成为与该主接面区120的结构相似的形状，并且与该主接面区120以及该主动区110间隔地放置在该主动区110之外。
本领域的技术人员可理解的是，本发明的碳化硅半导体元件100不限于图2中的说明，其也适用于具有不同形式的边缘终端结构的晶体管单元，包括浮接保护环、一个或多个JTE终端以及保护环和JTE的组合。本案图示中以绘制四个保护环表示多个的该保护环109，然而，该保护环109的数量可以少于或多于四个，在此不加以限制。
该多晶硅层105覆盖该绝缘层104并且包括一第一部分105a以及一第二部分105b。该多晶硅层105的该第一部分105a设置于该主动区110的一部分之上并沿其延伸，而该多晶硅层105的该第二部分105b设置于该主接面区120的一部分与该边缘区130的一部分之上并沿其延伸。
该层间介电层106形成于该绝缘层104以及该多晶硅层105之上。该金属层107覆盖该层间介电层106并且包括一第一部分107a以及一第二部分107b。该金属层107的该第一部分107a以及该第二部分107b之间形成一开口区140，以分隔该第一部分107a与该第二部分107b。
该金属层107的该第一部分107a设置于该主动区110的一部分之上并沿其延伸，该金属层107的该第二部分107b设置于该主接面区120的一部分与该边缘区130的一部分之上并沿其延伸。
该多晶硅层105的该第二部分105b以及该金属层107的该第二部分107b通过该层间介电层106中的一开口106a相互连接。在本实施例中，该多晶硅层105的该第二部分105b以及该金属层107的该第二部分107b被配置为电连接至一栅极G。此外，该金属层107的该第二部分107b被作为该碳化硅半导体元件100的一栅极通路(gate runner)/一栅极总线区(gate bus region)。如图2所示，该金属层107的该第二部分107b是横向地向外延伸而超出该多晶硅层105的该第二部分105b。该栅极通路围绕地延伸在该主动区110之外并将该栅极G连接到一共同栅极触点或一栅极垫片。
本方法的技术效果在于，该碳化硅半导体元件100的该栅极通路设置在该主动区110之外的区域中。具体而言，该栅极通路设置在该主接面区120以及该边缘区130之上而不占据该主动区110。因此，该主动区110的有效尺寸相对于现有的碳化硅半导体元件可以更大，从而更有效地降低栅极电阻。
此外，该多晶硅层105的该第二部分105b以及该金属层107的该第二部分107b分别作为一第一场板以及一第二场板，以提供双层场板。据此，相对于现有的碳化硅半导体元件，本发明的该碳化硅半导体元件100的崩溃电压可以进一步提高。
参阅图3，为本发明第二实施例的碳化硅半导体元件100的剖面示意图。在本实施例中，仅该多晶硅层105的该第二部分105b电连接至该栅极G。该金属层107的该第一部分107a与该第二部分107b彼此电连接，该金属层107电连接至一源极S并与该多晶硅层105的该第一部分105a和该第二部分105b形成电气隔离。图4为本发明第三实施例的碳化硅半导体元件100的剖面示意图，在本实施例中，该金属层107的该第二部分107b与该多晶硅层105的该第二部分105b电连接至该源极S。
图5为本发明第四实施例的碳化硅半导体元件100的剖面示意图。在本实施例中，该多晶硅层105包括设置在该主动区110上方的该第一部分105a以及设置在该主接面区120以及该边缘区130上方的该第二部分105b，如上述实施例所述。然而，该金属层107仅形成于该主动区110的一顶部，即该金属层107并未延伸至该边缘区130。在本实施例中，该金属层107电连接至该源极S，而该多晶硅层105的该第二部分105b电连接至该栅极G。如图5所示，该金属层107与该多晶硅层105的该第一部分105a以及该第二部分105b形成电气隔离(electrically isolated)。该多晶硅层105相互连接未示于图5。
图6为本发明第五实施例的碳化硅半导体元件100的剖面示意图。在本实施例中，该金属层107包括设置在该主动区110上方的该第一部分107a以及设置在该主接面区120和该边缘区130上方的该第二部分107b，如上述实施例所述。该金属层107的该第一部分107a以及该第二部分107b彼此电连接，且该金属层107电连接至该源极S。然而，该多晶硅层105仅形成于该主动区110之上，即该多晶硅层105没有延伸到该边缘区130。在本实施例中，该多晶硅层105电连接至该栅极G。该金属层107与该多晶硅层105电隔离，该多晶硅层105与栅极垫片的相互连接未示于图6。
【符号说明】
100：碳化硅半导体元件
101：碳化硅基板
102：漂移层
103：晶体管单元
103a：第一阱区
103b：源区
103c：掺杂区
104：绝缘层
105：多晶硅层
105a：第一部分
105b：第二部分
106：层间介电层
106a：开口
107：金属层
107a：第一部分
107b：第二部分
108：第二阱区
109：保护环
110：主动区
120：主接面区
130：边缘区
140：开口区
G：栅极
S：源极。

Claims (7)

1.一种碳化硅半导体元件，其特征在于，包括：
一碳化硅基板，具有一第一导电类型；
一漂移层，具有该第一导电类型且设置于该碳化硅基板上；
一主动区，形成于该漂移层，该主动区包括多个晶体管单元；
一终端区，形成于该漂移层且围绕该主动区；
一绝缘层，设置于该漂移层上；
一多晶硅层，设置于该绝缘层上，该多晶硅层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分；
一层间介电层，设置于该多晶硅层上；以及
一金属层，设置于该层间介电层上，该金属层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分；
其中，该多晶硅层的该第二部分以及该金属层的该第二部分中的至少一个被配置为电连接至一栅极以及一源极中的至少一个。
2.根据权利要求1所述的碳化硅半导体元件，其特征在于，该金属层的该第二部分是横向地延伸而超出该多晶硅层的该第二部分。
3.根据权利要求1所述的碳化硅半导体元件，其特征在于，该金属层的该第二部分以及该多晶硅层的该第二部分是电连接至该栅极。
4.一种碳化硅半导体元件，其特征在于，包括：
一碳化硅基板，具有一第一导电类型；
一漂移层，具有该第一导电类型且设置于该碳化硅基板上；
一主动区，形成于该漂移层，该主动区包括多个晶体管单元；
一终端区，形成于该漂移层且围绕该主动区；
一绝缘层，设置于该漂移层上；
一多晶硅层，设置于该绝缘层上，该多晶硅层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分，该多晶硅层的该第二部分被配置为连接至一栅极以及一源极中的至少一个；
一层间介电层，设置于该多晶硅层上；以及
一金属层，设置于该层间介电层上。
5.根据权利要求4所述的碳化硅半导体元件，其特征在于，该金属层以及该多晶硅层的该第二部分电连接到该栅极。
6.一种碳化硅半导体元件，其特征在于，包括：
一碳化硅基板，具有一第一导电类型；
一漂移层，具有该第一导电类型且设置于该碳化硅基板上；
一主动区，形成于该漂移层，该主动区包括多个晶体管单元；
一终端区，形成于该漂移层且围绕该主动区；
一绝缘层，设置于该漂移层上；
一多晶硅层，设置于该绝缘层上；
一层间介电层，设置于该多晶硅层上；
一金属层，设置于该层间介电层上，该金属层包括一设置于该主动区上方的第一部分以及一设置于该终端区上方的第二部分，该金属层的该第二部分被配置为连接至一栅极以及一源极中的至少一个。
7.根据权利要求6所述的碳化硅半导体元件，其特征在于，该金属层的该第二部分以及该多晶硅层是电连接至该栅极。
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