CN116779664A - IGBT chip with interelectrode capacitance structure and manufacturing method thereof - Google Patents
IGBT chip with interelectrode capacitance structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 122
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 66
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 61
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 210000000746 body region Anatomy 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- -1 BF2 ions Chemical class 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 13
- 238000002513 implantation Methods 0.000 description 10
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
The application provides an IGBT chip with an inter-electrode capacitance structure and a manufacturing method thereof, wherein the chip comprises the following components: an N-type silicon substrate, a silicon dioxide region, a P-type body region, an N+ emitter, a grid polysilicon region, a top polysilicon layer, a contact hole, a top metal region, an N-type field termination region, a P+ anode region, a Cgs emitter terminal electrode and a Cgs grid terminal electrode; the top polysilicon layer and the silicon dioxide layer formed on the top of the gate polysilicon region form a capacitor structure, and the capacitor structure is respectively connected with the Cgs emitter terminal electrode and the Cgs gate terminal electrode so as to change Cgs while keeping Cgd unchanged. The application provides a novel IGBT structure, wherein a capacitor connected with a grid and an emitter in parallel is formed at the top of a grid polycrystalline silicon region, and the size of Cgs is changed.
Description
Technical Field
The application relates to the technical field of IGBT chip preparation, in particular to an IGBT chip with an inter-electrode capacitance structure and a manufacturing method thereof.
Background
The IGBT is a high-power semiconductor discrete device, combines the advantages of high switching frequency of MOS devices, easiness in control, high current processing capacity of BJT devices and the like, and has wide application in the fields of industrial frequency conversion, consumer electronics, rail transit, new energy, aerospace and the like.
The application range of the IGBT is wide, as shown in fig. 1, and in some application occasions, cgs needs to be adjusted in the occasion of keeping Cgd, and under the condition of not changing the design, the Cgd and Cgs will increase or decrease in equal ratio, so that the effect of keeping Cgd unchanged but changing Cgs cannot be achieved.
Disclosure of Invention
In view of this, the present application provides an IGBT chip having an inter-electrode capacitance structure and a method for manufacturing the same, which are capable of changing the value of Cge while keeping Cgd unchanged.
In order to solve the above-mentioned problems, the present application provides an IGBT chip with an inter-electrode capacitance structure, comprising an N-type silicon substrate, a silicon dioxide region, a P-type body region, an n+ emitter, a gate polysilicon region, a top polysilicon layer, a contact hole, a top metal region, an N-type field termination region, a p+ anode region, a Cgs emitter terminal electrode, and a Cgs gate terminal electrode;
the top polysilicon layer is formed on top of the gate polysilicon region, the top polysilicon layer and the silicon dioxide region together form a capacitor structure, and the capacitor structure is respectively connected with the Cgs emitter electrode and the Cgs gate electrode to change Cgs while keeping Cgd unchanged.
In order to solve the above-mentioned problem, the present application further provides a manufacturing method for manufacturing the IGBT chip with the inter-electrode capacitance structure, the manufacturing method comprising the steps of:
s1, selecting an N-type silicon substrate, depositing silicon dioxide with preset thickness, forming a P-type body region on the N-type silicon substrate through ion implantation, using photoresist as a mask, etching the silicon dioxide to obtain an oxidation mask layer, and removing the photoresist;
s2, taking the oxidation mask layer as a hard mask layer, and removing the hard mask layer after a groove structure is obtained based on dry etching;
s3, oxidizing the groove structure to form a gate oxide layer;
s4, depositing polysilicon to fill the groove structure to form a grid polysilicon region, etching to remove polysilicon on the surface of the N-type silicon substrate, and forming an N+ emitter through ion implantation;
s5, sequentially depositing a silicon dioxide layer and a polysilicon layer, removing part of the silicon dioxide and the polysilicon by photoetching and etching to obtain the silicon dioxide layer and a top polysilicon layer, wherein the top polysilicon layer and the silicon dioxide region jointly form a capacitor structure;
s6, depositing a dielectric layer, etching a contact hole, depositing a top metal layer to connect the N+ emitter and the top polysilicon layer on the silicon dioxide layer, and performing back high-energy ion implantation on the N-type silicon substrate to form an N-type field termination region and a P+ anode region.
In some possible embodiments, the step S1 specifically includes:
selecting an N-type FZ monocrystalline silicon substrate, depositing silicon dioxide with preset thickness, and performing oxide layer growth on the FZ monocrystalline silicon substrate by adopting a wet oxygen process;
forming a P-type body region on the N-type silicon substrate by injecting P-type ions, and performing impurity propulsion after photoresist removal;
and using the photoresist as a mask, then performing silicon dioxide etching to obtain an oxidation mask layer, and removing the photoresist.
In some possible embodiments, the step S2 specifically includes:
silicon dioxide etching hard mask layer is grown based on PECVD deposition, and the hard mask layer is removed after a groove structure is obtained based on dry etching;
in some possible embodiments, the step S3 specifically includes:
and growing a sacrificial oxide layer, removing the sacrificial oxide layer, and growing gate oxide to form a gate oxide layer on the groove structure.
In some possible embodiments, in said step S4:
and forming an N+ emitter through N-type ion implantation.
In some possible embodiments, the step S5 specifically includes:
and depositing silicon dioxide and a polysilicon layer based on PECVD in sequence, removing part of silicon dioxide and polysilicon by photoetching and etching to obtain the silicon dioxide layer and a top polysilicon layer, wherein the top polysilicon layer and the silicon dioxide region jointly form a capacitor structure.
In some possible embodiments, the step S6 specifically includes:
adopting a USG+BPSG double-layer structure as an isolation medium layer;
etching the contact hole to a preset depth, injecting BF2 ions for the first time and B+ ions for the second time in contact Kong Ouyu, and annealing the furnace tube after photoresist removal;
depositing a metal layer on the front surface to a preset thickness so as to connect the N+ emitter and the top polysilicon layer on the silicon dioxide layer;
p+ ions are injected into the back Buffer layer, B+ ions are injected into the back anode, and the furnace tube is annealed to activate impurities, so that an N-type field termination region and a P+ anode region are formed.
The beneficial effects of adopting the embodiment are as follows:
the top polysilicon layer and the silicon dioxide layer formed on the top of the grid polysilicon region form a capacitor structure, and the capacitor structure is respectively connected with the Cgs emitter terminal electrode and the Cgs grid terminal electrode, so that a capacitor connected with the grid and the emitter in parallel is formed, and Cgs is changed while Cgd is unchanged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a conventional IGBT chip in the prior art;
fig. 2 is a schematic diagram illustrating a structural change of an embodiment of an IGBT chip after step S1 in the method for manufacturing an IGBT chip with an inter-electrode capacitance structure according to the present application;
fig. 3 is a schematic diagram illustrating a structural change of an embodiment of an IGBT chip after step S2 is performed in the method for manufacturing an IGBT chip with an inter-electrode capacitance structure according to the present application;
fig. 4 is a schematic diagram illustrating a structural change of an embodiment of an IGBT chip after step S3 is performed in the method for manufacturing an IGBT chip with an inter-electrode capacitance structure according to the present application;
fig. 5 is a schematic diagram illustrating a structural change of an embodiment of an IGBT chip after step S4 is performed in the method for manufacturing an IGBT chip with an inter-electrode capacitance structure according to the present application;
fig. 6 is a schematic diagram illustrating a structural change of an embodiment of an IGBT chip after step S5 in the method for manufacturing an IGBT chip with an inter-electrode capacitance structure according to the present application;
fig. 7 is a schematic diagram illustrating a structural change of an embodiment of an IGBT chip after step S6 in the method for manufacturing an IGBT chip with an inter-electrode capacitance structure according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Before the embodiments are set forth, the related terms related to the present application are explained:
cgd: capacitance of between Gate and Drain, the capacitance between the gate and the drain;
cgs: capacitance of between Gate and Source, i.e. the capacitance between the gate and the source.
The application provides an IGBT chip with an inter-electrode capacitance structure and a manufacturing method thereof, and the IGBT chip is described in detail.
In an embodiment of the present application, referring to fig. 7, an IGBT chip with an inter-electrode capacitance structure is provided, where the IGBT chip with an inter-electrode capacitance structure includes an N type silicon substrate 101, a silicon dioxide region 102, a P type body region 103, an n+ emitter 105, a gate polysilicon region 106, a top polysilicon layer 107, a contact hole 108, a top metal region 109, an N type field stop region 110, a p+ anode region 111, a Cgs emitter terminal electrode 112, and a Cgs gate terminal electrode 113;
the top polysilicon layer 107 formed on top of the gate polysilicon region 106, the top polysilicon layer 107 and the silicon dioxide region 102 together form a capacitor structure, and the capacitor structure is respectively connected to the Cgs emitter electrode 112 and the Cgs gate electrode 113, so as to change Cgs while keeping Cgd unchanged.
It should be noted that, the top polysilicon layer 107 is connected to the Cgs emitter electrode 112, and the silicon dioxide region 102 is connected to the Cgs emitter electrode 112, and only the polysilicon content in the top polysilicon layer 107 or the silicon dioxide content in the silicon dioxide region 102 needs to be changed during the preparation, so that Cgs can be changed while Cgd is unchanged.
Compared with the prior art, the top polysilicon layer and the silicon dioxide layer formed at the top of the grid polysilicon region form a capacitor structure, and the capacitor structure is respectively connected with the Cgs emitter terminal electrode and the Cgs grid terminal electrode, so that a capacitor connected with the grid and the emitter in parallel is formed, and Cgs is changed while Cgd is unchanged.
In an embodiment of the present application, a method for manufacturing an IGBT chip having an inter-electrode capacitance structure is further provided, referring to fig. 2 to 7, which specifically includes the following steps:
s1, selecting an N-type silicon substrate 101, depositing silicon dioxide with preset thickness, forming a P-type body region 103 on the N-type silicon substrate through ion implantation, using photoresist as a mask, performing silicon dioxide etching to obtain an oxidation mask layer 114, and removing the photoresist to obtain a structure diagram shown in FIG. 2;
s2, taking the oxidation mask layer 114 as a hard mask layer, and removing the hard mask layer after obtaining a groove structure based on dry etching to obtain a structure diagram shown in FIG. 3;
s3, oxidizing the groove structure to form a gate oxide layer 104, so as to obtain a structure diagram shown in FIG. 4;
s4, depositing polysilicon to fill the groove structure to form a grid polysilicon region 106, etching to remove polysilicon on the surface of the N-type silicon substrate, and forming an N+ emitter 105 through ion implantation to obtain a structure diagram shown in FIG. 5;
s5, sequentially depositing silicon dioxide and a polysilicon layer, removing part of silicon dioxide and polysilicon by photoetching and etching to obtain a silicon dioxide layer 102 and a top polysilicon layer 107, wherein the top polysilicon layer 107 and the silicon dioxide region 102 together form a capacitor structure, and the structure diagram shown in FIG. 6 is obtained;
s6, depositing a dielectric layer, etching a contact hole 108, depositing a top metal layer 109 to connect the N+ emitter 105 and the top polysilicon layer 107 on the silicon dioxide layer 102, and performing back high-energy ion implantation on the N-type silicon substrate 101 to form an N-type field termination region 110 and a P+ anode region 111, thereby obtaining the structure diagram shown in FIG. 7.
In some possible embodiments, please refer to fig. 2, the step S1 specifically includes:
selecting an N-type FZ monocrystalline silicon substrate, depositing silicon dioxide with preset thickness, and performing oxide layer growth on the FZ monocrystalline silicon substrate 101 by adopting a wet oxygen process, wherein the wafer surface of the FZ monocrystalline silicon substrate is a (100) crystal face, the resistivity is 30-90 Ω & cm, the wet oxygen process temperature is 800-1050 ℃, and the oxide layer thickness is 1-3 mu m;
forming a P-type body region 103 on the N-type silicon substrate 101 by injecting P-type ions, removing photoresist, and performing impurity propulsion, wherein the injected P-type ions are B+ ions, the injection dosage is 8E13-5E14, the injection energy is 80-140keV, the temperature during impurity propulsion is 1000-1200 ℃, and the time is 300-600min;
using the photoresist as a mask, a silicon dioxide etch is performed to obtain an oxide mask layer 114, and the photoresist is removed.
In some possible embodiments, please refer to fig. 3, the step S2 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on PECVD (Plasma Enhanced Chemical Vapor Deposition, a plasma enhanced chemical vapor deposition method), and removing the hard mask layer after a groove structure is obtained based on dry etching, wherein the thickness of the etching hard mask layer is 5000-10000A;
in some possible embodiments, please refer to fig. 4, the step S3 specifically includes:
the sacrificial oxide layer is grown to a thickness of 800-1200A, the sacrificial oxide layer is removed, and gate oxide is grown to form a gate oxide layer 104 in the trench structure to a thickness of 1000-1200A.
In some possible embodiments, please refer to fig. 5, in said step S4:
the N+ emitter 105 is formed by N-type ion implantation, specifically, P+ ions are implanted for the first time, the implantation dosage is 1E15-8E15, the implantation energy is 40-80keV, as+ ions are implanted for the second time, the implantation dosage is 1E15-8E15, the implantation energy is 40-100keV, and the furnace tube is annealed after photoresist removal, the temperature is 800-1000 ℃ and the time is 30-60min.
In some possible embodiments, please refer to fig. 6, the step S5 specifically includes:
depositing a silicon dioxide layer and a polysilicon layer based on PECVD in sequence, and removing part of the silicon dioxide and the polysilicon by photoetching and etching to obtain a silicon dioxide layer 102 and a top polysilicon layer 107; the top polysilicon layer 107 and the silicon dioxide layer 102 form a capacitor structure, and the capacitor structure is respectively connected with the Cgs emitter terminal electrode 112 and the Cgs gate terminal electrode 113, so as to form a capacitor connected in parallel with the gate and the emitter, so as to change Cgs while keeping Cgd unchanged.
In some possible embodiments, please refer to fig. 7, the step S6 specifically includes:
the USG+BPSG double-layer structure is adopted as an isolation medium layer, wherein the total thickness is 9000-12000A;
etching the contact hole 108 to a preset depth, injecting BF2 ions in the contact hole 108 for the first time, injecting B+ ions for the second time, and annealing the furnace tube after photoresist removal; wherein the preset depth is 0.2-0.5 mu m, the implantation dosage of BF2 ions implanted for the first time is 5E14-8E15, the implantation energy is 20-80keV, the implantation dosage of B+ ions implanted for the second time is 1E14-5E15, the implantation energy is 40-100keV, the annealing temperature of the furnace tube is 700-1000 ℃ and the time is 30-60min;
depositing a top metal layer 109 on the front side to a pre-set thickness of 4-8 μm to connect the n+ emitter 105 and the top polysilicon layer 107 on top of the silicon dioxide layer 102;
p+ ions are injected into the back Buffer layer, B+ ions are injected into the back anode, the furnace tube is annealed to activate impurities, and an N-type field termination region 110 and a P+ anode region 111 are formed, wherein the injection dosage of the injected P+ ions is 2E11-1E13, and the injection energy is 200-900keV; the implantation dosage of the implanted B+ ions is 1E12-8E13, and the implantation energy is 20-50keV; the annealing temperature of the furnace tube is 300-500 ℃ and the annealing time is 20-80min.
It should be noted that, by executing the manufacturing method of the steps S1 to S6, the IGBT chip with the inter-electrode capacitance structure of the above embodiment can be obtained, which forms a capacitance structure with the silicon dioxide layer 102 through the top polysilicon layer 107, and the capacitance structure is respectively connected with the Cgs emitter electrode 112 and the Cgs gate electrode 113, so as to form a capacitance connected in parallel with the gate and the emitter, so as to realize changing Cgs while keeping Cgd unchanged; specifically, it is only necessary to change the polysilicon content in the top polysilicon layer 107 or the silicon dioxide content in the silicon dioxide region 102 at the time of preparation, that is, to change Cgs while Cgd is unchanged.
The above describes the IGBT chip with the interelectrode capacitance structure and the method for manufacturing the same, and specific examples are applied to the description of the principle and the implementation of the application, and the description of the above examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (8)
1. The IGBT chip with the inter-electrode capacitance structure is characterized by comprising an N-type silicon substrate, a silicon dioxide region, a P-type body region, an N+ emitter, a grid polycrystalline silicon region, a top polycrystalline silicon layer, a contact hole, a top metal region, an N-type field termination region, a P+ anode region, a Cgs emitter electrode and a Cgs grid electrode;
the top polysilicon layer is formed on top of the gate polysilicon region, the top polysilicon layer and the silicon dioxide region together form a capacitor structure, and the capacitor structure is respectively connected with the Cgs emitter electrode and the Cgs gate electrode to change Cgs while keeping Cgd unchanged.
2. A method for manufacturing the IGBT chip with the interelectrode capacitance structure as claimed in claim 1, characterized in that the method comprises the steps of:
s1, selecting an N-type silicon substrate, depositing silicon dioxide with preset thickness, forming a P-type body region on the N-type silicon substrate through ion implantation, using photoresist as a mask, etching the silicon dioxide to obtain an oxidation mask layer, and removing the photoresist;
s2, taking the oxidation mask layer as a hard mask layer, and removing the hard mask layer after a groove structure is obtained based on dry etching;
s3, oxidizing the groove structure to form a gate oxide layer;
s4, depositing polysilicon to fill the groove structure to form a grid polysilicon region, etching to remove polysilicon on the surface of the N-type silicon substrate, and forming an N+ emitter through ion implantation;
s5, sequentially depositing a silicon dioxide layer and a polysilicon layer, removing part of the silicon dioxide and the polysilicon by photoetching and etching to obtain the silicon dioxide layer and a top polysilicon layer, wherein the top polysilicon layer and the silicon dioxide region jointly form a capacitor structure;
s6, depositing a dielectric layer, etching a contact hole, depositing a top metal layer to connect the N+ emitter and the top polysilicon layer on the silicon dioxide layer, and performing back high-energy ion implantation on the N-type silicon substrate to form an N-type field termination region and a P+ anode region.
3. The method according to claim 2, wherein the step S1 specifically includes:
selecting an N-type FZ monocrystalline silicon substrate, depositing silicon dioxide with preset thickness, and performing oxide layer growth on the FZ monocrystalline silicon substrate by adopting a wet oxygen process;
forming a P-type body region on the N-type silicon substrate by injecting P-type ions, and performing impurity propulsion after photoresist removal;
and using the photoresist as a mask, then performing silicon dioxide etching to obtain an oxidation mask layer, and removing the photoresist.
4. The method according to claim 2, wherein the step S2 specifically includes:
and growing a silicon dioxide etching hard mask layer based on PECVD deposition, and removing the hard mask layer after obtaining a groove structure based on dry etching.
5. The method according to claim 2, wherein the step S3 specifically includes:
and growing a sacrificial oxide layer, removing the sacrificial oxide layer, and growing gate oxide to form a gate oxide layer on the groove structure.
6. The method according to claim 2, wherein in the step S4:
and forming an N+ emitter through N-type ion implantation.
7. The method according to claim 2, wherein the step S5 specifically includes:
and depositing silicon dioxide and a polysilicon layer based on PECVD in sequence, removing part of silicon dioxide and polysilicon by photoetching and etching to obtain the silicon dioxide layer and a top polysilicon layer, wherein the top polysilicon layer and the silicon dioxide region jointly form a capacitor structure.
8. The method according to claim 2, wherein the step S6 specifically includes:
adopting a USG+BPSG double-layer structure as an isolation medium layer;
etching the contact hole to a preset depth, injecting BF2 ions for the first time and B+ ions for the second time in contact Kong Ouyu, and annealing the furnace tube after photoresist removal;
depositing a metal layer on the front surface to a preset thickness so as to connect the N+ emitter and the top polysilicon layer on the silicon dioxide layer;
p+ ions are injected into the back Buffer layer, B+ ions are injected into the back anode, and the furnace tube is annealed to activate impurities, so that an N-type field termination region and a P+ anode region are formed.
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