CN116779660A - Low-loss IGBT structure for inhibiting voltage reverse-turn phenomenon and preparation method - Google Patents
Low-loss IGBT structure for inhibiting voltage reverse-turn phenomenon and preparation method Download PDFInfo
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The application provides a low-loss IGBT structure for inhibiting voltage reverse folding phenomenon and a preparation method thereof, belonging to the field of semiconductor power devices, wherein a P-type barrier layer is additionally arranged on the upper side of a collector N-type region on the basis of the existing structure, the P-type barrier layer and the collector N-type region are stacked on the right side of a collector P+ region, and a collector trapezoid convex hull is embedded in the stacked structure of the collector N-type region and the P-type barrier layer; the self-adaptive MOS structure is formed by the N-type buffer layer, the collector N-type region, the P-type barrier layer and the collector trapezoid convex hull, wherein the N-type buffer layer forms a source region of the MOS structure, the collector N-type region forms a drain region, the P-type barrier layer forms a base region, and the collector trapezoid convex hull forms a control gate. The application avoids voltage reverse phenomenon in the early stage of conduction without additionally introducing a back side gate control electrode, provides an electron extraction path which is self-adaptively widened along with the rising of the collector voltage during turn-off, further shortens turn-off time and reduces conduction loss.
Description
Technical Field
The application belongs to the technical field of semiconductor power devices, and particularly relates to a low-loss IGBT structure for inhibiting voltage reverse phenomenon and a preparation method thereof.
Background
Insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs) have since their birth evolved towards increasing their operating frequency, withstand voltage levels, current densities, reducing their turn-on voltage drops, switching losses, etc., which are contradictory, one of the trade-off relationships of greatest interest in the industry being turn-on voltage drop V ce And turn-off loss E off 。
The conduction voltage drop of the IGBT is lower due to the conduction modulation effect of the drift region during conduction, but the conduction modulation also causes that extra time is needed to eliminate carriers of the drift region during turn-off of the device, so that larger tailing current is generated, the turn-off time of the device is prolonged, and turn-off loss is increased.
The addition of an N-doped region on the collector side to provide an extraction path for electrons can speed up device turn-off, and this structure simultaneously embeds a reverse freewheeling diode into the IGBT structure, and thus is also referred to as a reverse turn-on IGBT (Reverse Conducting IGBT, RCIGBT), the structure of which is shown in fig. 1. But this structure creates a new problem: in the initial conduction stage, as the collector N+ region is connected with the N-type buffer region, the P+/Nbbuffer junction is short-circuited, the device works in an MOS mode, holes cannot be injected into the drift region by the anode P+ region, the drift region has no conductivity modulation effect, and the on-resistance is large. With the current enhancement, the P+/Nbbuffer junction is turned on, the device is converted into an IGBT mode from a MOS mode, the current is suddenly increased, a snapback (voltage foldback) phenomenon occurs, and a negative differential resistance region (NDR) with increased current and reduced voltage is generated, so that the parallel connection of the devices is not facilitated.
Disclosure of Invention
In order to solve the problems in the background technology, the application provides a novel IGBT structure and a preparation method thereof, and a similar MOS structure is formed by adding a P-type barrier layer and a trapezoid convex hull of a collector electrode on the collector electrode side.
The first aspect of the present application provides a low-loss IGBT structure for suppressing voltage reverse phenomenon, comprising a collector, the upper side of the collector being directly connected to a collector p+ region and a collector N-type region; the collector P+ region and the collector N-type region are provided with an N-type buffer layer, an N-type drift region, a P-type base region, an emitter P+ region, an emitter N+ region, a grid and an emitter in a stacked mode, and the collector P+ region and the collector N-type region are characterized in that: a P-type barrier layer is additionally arranged on the upper side of the collector N-type region, the collector N-type region and the P-type barrier layer are stacked on the right side of the collector P+ region, the height of the collector N-type region is equal to that of the P+ region, and a collector trapezoid convex hull is embedded in a stacked structure of the collector N-type region and the P-type barrier layer; the self-adaptive MOS structure is formed by the N-type buffer layer, the collector N-type region, the P-type barrier layer and the collector trapezoid convex hull, wherein the N-type buffer layer forms a source region of the MOS structure, the collector N-type region forms a drain region of the MOS structure, the P-type barrier layer forms a base region of the MOS structure, and the collector trapezoid convex hull forms a control gate of the MOS structure.
Preferably, the collector trapezoidal convex hull structure is located at the center of the stacking structure of the P-type barrier layer and the collector N-type region, and comprises a metal electrode and an oxide layer, the thickness of the top of the oxide layer is thicker than that of two sides, and a collector is arranged below the collector trapezoidal convex hull.
Preferably, the P-type barrier layer has a doping concentration less than that of the collector P+ region and is at 10 15 ～10 17 Between the measuring stages.
Preferably, the thickness of the P-type barrier layer is 1/2 to 2/3 of the thickness of the collector p+ region, so as to ensure the barrier width to electrons and achieve a good barrier effect.
Preferably, the collector trapezoidal convex hull should be between 1 and 3 microns above the P-type barrier layer to deposit a thick enough oxide layer on top to shield the collector convex hull from electrons in the N-type buffer layer.
The second aspect of the present application provides a method for manufacturing a low-loss IGBT structure that suppresses a voltage rollback phenomenon, comprising the steps of:
providing a component formed by sequentially stacking a substrate and a drift layer from bottom to top, and preparing a groove structure on the drift layer through spin coating, exposure, development and dry etching processes;
growing a gate oxide layer on the side wall of the groove sequentially through a furnace tube thermal oxidation process, and filling polycrystal by using low-pressure chemical vapor deposition equipment to form a gate;
forming a P-type base region, an emitter P+ region and a heavily doped emitter N+ region respectively through ion implantation and heat treatment;
generating an interlayer dielectric emitter metal by adopting a thin film deposition technology;
after a substrate is thinned by adopting a thinning process, an N-type buffer layer, a collector P+ region, a P-type barrier layer and a collector N-type region are formed by ion implantation and heat treatment;
forming a ladder groove structure by adopting a photoetching and etching process;
forming a ladder groove oxide layer by adopting a chemical vapor deposition CVD process;
and filling the trapezoid groove by adopting a metal evaporation process to form the back contact collector metal with the collector trapezoid convex hull.
Compared with the prior art, the application has the following advantages and beneficial effects:
according to the application, the P-type barrier layer and the trapezoid convex hulls of the collector electrode are designed to form a MOS-like structure with the N-type drift region and the N-type region of the collector electrode, so that the MOS-like closing at the initial stage of device conduction can be realized on the premise of not introducing an additional back gate control electrode, electrons in the drift region and the buffer region are blocked from directly flowing to the collector electrode by the P-type barrier layer, and the voltage reverse-turn snapback phenomenon is inhibited; when the switch is turned off in the period, the MOS-like part is turned on to provide a self-adaptive extraction channel for electrons, so that the turn-off speed is increased, and the turn-off loss is reduced. Compared with the prior art, the application avoids introducing an extra grid control electrode on the back of the device, effectively inhibits the voltage turn-back phenomenon when the RCIGBT device is turned on without increasing the difficulty of device control, effectively reduces the tailing current when the device is turned off, and reduces the turn-off loss of the device.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will be given simply with reference to the accompanying drawings, which are used in the description of the embodiments or the prior art, it being evident that the following description is only one embodiment of the application, and that other drawings can be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a conventional RC-IGBT structure.
Fig. 2 is a schematic diagram of the IGBT structure of the present application.
Fig. 3 is a graph of the shielding effect of different thickness oxide layers on gate voltage.
Fig. 4 is a schematic diagram of an equivalent circuit of an IGBT structure of the present application.
Fig. 5 is a schematic diagram of electron hole distribution at the initial turn-on stage of the IGBT structure according to the present application.
Fig. 6 is a schematic diagram of electron hole distribution when the IGBT structure of the application is turned on.
FIG. 7 is a graph showing the inhibitory effect of SnapBack of the present application.
Fig. 8 is a schematic diagram of electron hole extraction paths when the IGBT structure of the application is turned off.
Fig. 9 is a schematic flow chart of the first half of the IGBT structure fabrication according to the present application.
Fig. 10 is a schematic flow chart of the second half of the IGBT structure fabrication according to the present application.
Detailed Description
The technical solutions in the specific embodiments of the present application are clearly and completely described below with reference to the accompanying drawings in the present application.
As shown in fig. 2, the present application provides a low-loss IGBT structure for suppressing voltage reverse phenomenon, comprising a collector 1, the upper side of the collector 1 is directly connected to a collector p+ region 2 and a collector N-type region 4; the improvement is that a P type barrier layer 5 is additionally arranged on the upper side of the collector N type region 4, the collector P+ region 2 and the collector N type region 4 are stacked on the right side of the collector P+ region 2, the height of the collector P+ region 2 is equal to that of the collector P+ region 2, and a collector trapezoid convex hull 6 is embedded in a stacked structure of the collector N type region 4 and the P type barrier layer 5; the N-type buffer layer 3, the collector N-type region 4, the P-type barrier layer 5 and the collector trapezoid convex hull 6 form a self-adaptive MOS-like structure, wherein the N-type buffer layer 3 forms a source region of the MOS-like structure, the collector N-type region 4 forms a drain region of the MOS-like structure, the P-type barrier layer 5 forms a base region of the MOS-like structure, and the collector trapezoid convex hull 6 forms a control gate of the MOS-like structure. The collector trapezoid convex hull 6 is located in the center of the stacking structure of the P-type barrier layer 5 and the collector N-type region 4, and comprises a metal electrode and an oxide layer, the thickness of the top of the oxide layer is thicker than that of the two sides, namely the thickness of the two sides of the oxide layer is thinner, the top of the oxide layer is thicker, and the collector 1 is arranged below the collector trapezoid convex hull 6.
The doping concentration of the P-type barrier layer 5 is smaller than that of the collector P+ region, and is 10 15 ～10 17 The thickness between the measuring stages is not less than 2 micrometers in the range of 1/2 to 1/3 of the thickness of the collector P+ region so as to ensure the barrier width to electrons and play a good role in blocking.
Referring to fig. 3, the collector trapezoidal convex hull 6 should be deeper than the P-type barrier layer by 1-3 microns into the N-type buffer layer to deposit a thick enough oxide layer on top to shield the effect of collector voltage on electrons in the N-type buffer layer.
Working principle: referring to fig. 1, the conventional RCIGBT structure should satisfy the relationship V in the unipolar conduction mode CE ＝I C ·(R ch +R d +R Buf +R SA ) Wherein V is CE For collector 1 emitter 12 voltage drop, I c For collector 1 current, R ch R is the equivalent resistance of an emitter channel d Is the equivalent resistance of the N-type drift region 7, R Buf Is N-type buffer layer 3 equivalent resistance, R SA Is the equivalent resistance of the collector N-type region 4. PN junction voltage drop V formed by collector P+ region 2 and N type buffer layer 3 PN Satisfy V PN ＝I C ·R SA When V PN When 0.7V is reached, the device switches to bipolar on state. Defining the voltage value at this time as V SB The following steps are: V SB and V is equal to PN The closer the NDR, the smaller the NDR. When the P-type barrier layer 5 is added, the barrier is equivalent to a high-barrier region for electrons, which is equivalent to a large resistance and R SA In series, get->And->Approach 0, V SB Approximately equal to V PN The voltage folding phenomenon disappears.
Referring to fig. 4 to 7, in the initial stage of device turn-on, the voltage of the gate 11 rises to the threshold voltage, an inversion layer is formed in the P-type base region 8, the channel is opened, and electrons are at the collector 1 voltage V C Is injected from the emitter n+ region 10 into the N-type drift region 7 and flows to the N-type buffer layer 3. Because the collector voltage is smaller in the initial conduction stage, a PN junction formed by the collector P+ region 2 and the N-type buffer layer 3 is not opened, meanwhile, a MOS-like structure formed by the N-type buffer layer 3, the collector N-type region 4, the P-type barrier layer 5 and the collector trapezoid convex hull 6 is also not opened, electrons are prevented from directly flowing from the N-type buffer layer 3 to the collector 1 by the P-type barrier layer 5, holes cannot be injected into the N-type drift region 7 by the collector P+ region 2, and the electrons and the holes are accumulated on two sides of the PN junction. With V C The electron holes accumulated on two sides of the PN junction are more and more, the potential difference is rapidly increased, when the potential difference is more than 0.7V, electrons rapidly flow from the N-type buffer layer 3 to the collector 1, holes are injected from the P+ region 2 of the collector in a large quantity, the device directly enters a bipolar conduction mode, and the phenomenon of voltage reverse snapback is eliminated.
Referring to fig. 8, since the collector 1 voltage V during the turn-off of the IGBT device C The blocking voltage will rise and then the collector 1 current will start to drop, so that the MOS-like is in an on state during the off-state, and the electron channel in the P-type barrier layer 5 provides an extraction path for electrons in the N-type drift region 7. Considering that the metal electrode of the collector has a gate control function in the MOS-like structure, the gate drain voltage is approximate, the electric field force borne by electrons has vertical directional component force due to the design of the trapezoidal convex hull 6 of the collector, the electron extraction efficiency is improved, and the manufacture is easier. And at V C In the rising process, inversion layers in the P-type barrier layer 5 are continuously accumulated, the MOS-like channel is self-adaptively widened, the electron extraction speed is increased, the trailing current of the device is greatly weakened, the turn-off speed is improved, and the turn-off loss is effectively reduced.
Referring to fig. 9 and 10, the preparation method of the IGBT structure provided by the embodiment of the application is as follows:
providing an assembly composed of a substrate base and a Drift layer (Drift) which are sequentially stacked from bottom to top, and preparing a groove structure on the Drift layer through processes such as spin coating, exposure, development, dry etching and the like, as shown in diagrams (a) to (c) in fig. 9.
And growing a gate oxide layer on the side wall of the groove sequentially through a furnace tube thermal oxidation process, and filling polycrystal by using low-pressure chemical vapor deposition equipment to form a gate, wherein the gate is shown in a graph (d) in fig. 9.
The P-type base region, the emitter p+ region, and the heavily doped emitter n+ region are formed by ion implantation and heat treatment, respectively, as shown in fig. 9 (e) to (g).
An interlayer dielectric emitter metal is produced using a thin film deposition technique, as shown in figure 9, diagram (h).
After the substrate is thinned by adopting a thinning process, an N-type buffer layer, a collector P+ region and a P-type barrier layer) and a collector N-type region are formed by ion implantation and heat treatment; as shown in fig. 10 (i) to (l).
And forming a ladder groove structure by adopting photoetching and etching processes, as shown in a graph (m) in fig. 10.
A CVD (chemical vapor deposition) process is used to form the mesa oxide layer as shown in fig. 10 (n).
The metal evaporation process is used to fill the terraced slot and form the metal of the back contact collector (1) with the trapezoidal convex hull of the collector, as shown in figure 10 (o).
The foregoing description, in conjunction with the accompanying drawings, fully illustrates the specific embodiments of the application so as to enable those skilled in the art to practice them. Portions and features of some embodiments may be included in, or substituted for, those of others. In the present application, the terms "first," "second," and the like are used merely to distinguish one element from another element, and do not require or imply any actual relationship or order between the elements. Indeed the first element could also be termed a second element and vice versa. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such structure, apparatus, or device. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a structure, apparatus or device comprising the element. In the application, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred.
The terms "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like herein refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description herein and to simplify the description, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application. In the description herein, unless otherwise specified and limited, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, mechanically or electrically coupled, may be in communication with each other within two elements, may be directly coupled, or may be indirectly coupled through an intermediary, as would be apparent to one of ordinary skill in the art. In the present application, the term "plurality" means two or more, unless otherwise indicated.
The above description is only for the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations may be made by those skilled in the art, and it should be apparent that various modifications, variations, equivalents, etc. may be made without inventive faculty for those skilled in the art, and are intended to be included within the scope of the present application.
Claims (6)
1. A low-loss IGBT structure for inhibiting voltage reverse folding phenomenon comprises a collector (1), wherein the upper side of the collector (1) is directly connected with a collector P+ region (2) and a collector N-type region (4); the collector P+ region (2) and the collector N-type region (4) are provided with an N-type buffer layer (3), an N-type drift region (7), a P-type base region (8), an emitter P+ region (9), an emitter N+ region (10), a grid electrode (11) and an emitter (12) in a stacked mode, and the collector P+ region is characterized in that: a P-type barrier layer (5) is additionally arranged on the upper side of the collector N-type region (4), the collector N-type region and the P-type barrier layer are stacked on the right side of the collector P+ region (2), the height of the collector N-type region is equal to that of the P+ region (2), and a collector trapezoid convex hull (6) is embedded in a stacked structure of the collector N-type region (4) and the P-type barrier layer (5); the self-adaptive MOS structure is formed by the N-type buffer layer (3), the collector N-type region (4), the P-type barrier layer (5) and the collector trapezoid convex hull (6), wherein the N-type buffer layer (3) forms a source region of the MOS structure, the collector N-type region (4) forms a drain region of the MOS structure, the P-type barrier layer (5) forms a base region of the MOS structure, and the collector trapezoid convex hull (6) forms a control gate of the MOS structure.
2. A low-loss IGBT structure for suppressing voltage foldback according to claim 1, wherein: the collector trapezoid convex hull (6) structure is located in the center of the stacking structure of the P-type barrier layer (5) and the collector N-type region (4), and comprises a metal electrode and an oxide layer, the thickness of the top of the oxide layer is thicker than that of two sides, and a collector (1) is arranged below the collector trapezoid convex hull (6).
3. A low-loss IGBT structure for suppressing voltage foldback according to claim 1, wherein: the doping concentration of the P-type barrier layer (5) is smaller than that of the collector P+ region (2) and is 10 15 ～10 17 Between the measuring stages.
4. A low-loss IGBT structure for suppressing voltage foldback according to claim 1, wherein: the thickness of the P-type barrier layer (5) is 1/2 to 2/3 of the thickness of the collector P+ region (2), so that the barrier width to electrons is ensured, and a good barrier effect is achieved.
5. A low-loss IGBT structure for suppressing voltage foldback according to claim 1, wherein: the collector trapezoidal convex hull (6) should be between 1 and 3 microns higher than the P-type barrier layer (5) to deposit a thick enough oxide layer on top for shielding the collector convex hull (6) from electrons in the N-type buffer layer (3).
6. The preparation method of the low-loss IGBT structure for inhibiting the voltage reverse-turn phenomenon is characterized by comprising the following steps of:
providing a component formed by sequentially stacking a substrate and a drift layer from bottom to top, and preparing a groove structure on the drift layer through spin coating, exposure, development and dry etching processes;
growing a gate oxide layer on the side wall of the groove sequentially through a furnace tube thermal oxidation process, and filling polycrystal by using low-pressure chemical vapor deposition equipment to form a gate (11);
forming a P-type base region (8), an emitter P+ region (9) and a heavily doped emitter N+ region (10) respectively through ion implantation and heat treatment;
generating interlayer dielectric emitter (12) metal by adopting a thin film deposition technology;
after a substrate is thinned by adopting a thinning process, an N-type buffer layer (3), a collector P+ region (2), a P-type barrier layer (5) and a collector N-type region (4) are formed by ion implantation and heat treatment;
forming a ladder groove structure by adopting a photoetching and etching process;
forming a ladder groove oxide layer by adopting a chemical vapor deposition CVD process;
and filling the ladder groove by adopting a metal evaporation process to form the metal of the back contact collector (1) with the collector trapezoidal convex hull (6).
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