CN116760368A - Pre-amplifier circuit of low noise comparator and low noise comparator - Google Patents

Pre-amplifier circuit of low noise comparator and low noise comparator Download PDF

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Publication number
CN116760368A
CN116760368A CN202311065519.3A CN202311065519A CN116760368A CN 116760368 A CN116760368 A CN 116760368A CN 202311065519 A CN202311065519 A CN 202311065519A CN 116760368 A CN116760368 A CN 116760368A
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China
Prior art keywords
electrically connected
nmos tube
control switch
tube
output end
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CN202311065519.3A
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CN116760368B (en
Inventor
王汉卿
汪荔
李雪民
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Suzhou Linghui Lixin Technology Co ltd
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Suzhou Linghui Lixin Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

The invention discloses a pre-amplifier circuit of a low-noise comparator and the low-noise comparator, and belongs to the technical field of comparators. The pre-amplifier circuit includes: the input circuit is a complementary input pair consisting of two NMOS (N-channel metal oxide semiconductor) tubes and two PMOS (P-channel metal oxide semiconductor) tubes; the power supply circuit is a mirror current source consisting of an NMOS tube and a PMOS tube; the isolation circuit is a folded cascode stage consisting of two PMOS tubes; the load circuit, two capacitors and four load NMOS tubes, wherein the grid electrodes of the two NMOS tubes are connected with the common mode feedback circuit, so that parasitic capacitance of an output node can be reduced, and low-voltage design is facilitated; alternatively, the load circuit is composed of two capacitors and six load NMOS transistors, and the load NMOS transistors use a cross-coupling structure without an additional common mode feedback circuit. The invention can improve the gain and speed of the comparator and reduce the input noise of the comparator.

Description

Pre-amplifier circuit of low noise comparator and low noise comparator
Technical Field
The invention belongs to the technical field of comparators, and particularly relates to a pre-amplifier circuit of a low-noise comparator and the low-noise comparator.
Background
The comparator is composed of a pre-amplifier and a latch, wherein the pre-amplifier is mainly used for reducing the influence of dynamic errors of the latch, such as Offset voltage of the latch, which is equivalent to the input and can be attenuated by the gain of the pre-amplifier, the pre-amplifier usually selects one stage to three stages according to the requirement, and the Offset voltage of the pre-amplifier can be reduced through Auto-zero.
As shown in fig. 1, in the conventional preamplifier circuit, a PMOS transistor 1 and a PMOS transistor 2 are input pairs, a PMOS transistor 3 is a current source, and NMOS transistors 4 to 9 are load MOS transistors; the NMOS tube 4 and the NMOS tube 5 are respectively combined with the first capacitor C1 and the second capacitor C2, and an auto-zero method is used for reducing the offset voltage of the comparator; in the auto-zero operation mode, the function switch az is closed, the input switch azb is opened, the input pair PMOS transistor 1 and PMOS transistor 2 are shorted to the common mode voltage VCM, the offset voltage is stored in the capacitor C1 and the capacitor C2, in the comparison operation mode, the function switch az is opened, the input switch azb is closed, the offset voltage is inhibited from being attenuated by the NMOS transistor 4 and the NMOS transistor 5, the transconductance of the preamplifier circuit is determined by the input pair PMOS transistor 1 and PMOS transistor 2, and the gain and the speed of the comparator adopting the preamplifier circuit are limited, so that a preamplifier circuit capable of improving the gain and the speed of the comparator and reducing the input noise of the comparator is needed.
The information disclosed in the background section of the invention is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a pre-amplifier circuit of a low-noise comparator and the low-noise comparator, which can improve the gain and speed of the comparator and reduce the input noise of the comparator.
In order to achieve the above object, the present invention provides a pre-amplifier circuit and a pre-amplifier circuit of a low noise comparator, and a low noise comparator.
According to a first aspect of the present invention, there is provided a preamplifier circuit of a low noise comparator, comprising:
the input circuit is used for receiving and amplifying the first input signal and the second input signal of the pre-amplifier and reducing input noise;
a current source circuit for providing a bias current to the input circuit;
the isolation circuit is used for isolating the input circuit from the load circuit and enabling the input circuit and the load circuit to be biased at different voltages;
the load circuit is used for outputting the amplified first input signal and the second input signal and counteracting offset voltage and flicker noise of the pre-amplifier;
and a control switch for selectively receiving/not receiving the first input signal and the second input signal through the control switch, and selectively turning on/off an Auto-zero function of the preamplifier through the control switch.
Optionally, the current source circuit includes:
the first PMOS tube and the first NMOS tube;
the grid electrode of the first PMOS tube is electrically connected with a first bias voltage, the source electrode of the first PMOS tube is electrically connected with the power supply end VDD, and the drain electrode of the first PMOS tube is electrically connected with the input circuit;
the grid electrode of the first NMOS tube is electrically connected with the second bias voltage, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first PMOS tube is electrically connected with the input circuit.
Optionally, the input circuit includes:
the second PMOS tube, the third PMOS tube, the second NMOS tube, the third NMOS tube, the first control switch, the second control switch, the third control switch and the fourth control switch;
the grid electrode of the second PMOS tube is electrically connected with one end of the first control switch, the source electrode of the second PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube;
the grid electrode of the third PMOS tube is electrically connected with one end of the second control switch, the source electrode of the third PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube;
the grid electrode of the second NMOS tube is electrically connected with one end of the first control switch and one end of the third control switch, and the source electrode of the second NMOS tube is electrically connected with the drain electrode of the first NMOS tube;
the grid electrode of the third NMOS tube is electrically connected with one end of the second control switch and one end of the fourth control switch, and the source electrode of the third NMOS tube is electrically connected with the drain electrode of the first NMOS tube;
the other end of the first control switch is electrically connected with the positive input end, the other end of the second control switch is electrically connected with the negative input end, and the other end of the third control switch is electrically connected with the other end of the fourth control switch.
Optionally, the isolation circuit includes:
a fourth PMOS tube and a fifth PMOS tube;
the grid electrode of the fourth PMOS tube is electrically connected with the third bias voltage, the source electrode of the fourth PMOS tube is electrically connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is electrically connected with the negative output end;
the grid electrode of the fifth PMOS tube is electrically connected with the third bias voltage, the source electrode of the fifth PMOS tube is electrically connected with the drain electrode of the third PMOS tube, and the drain electrode of the fifth PMOS tube is electrically connected with the positive output end.
Optionally, the load circuit includes:
the first capacitor, the second capacitor, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the fifth control switch and the sixth control switch;
one end of the first capacitor is electrically connected with the grid electrode of the fourth NMOS tube and one end of the fifth control switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is electrically connected with the grid electrode of the fifth NMOS tube and one end of the sixth control switch, and the other end of the second capacitor is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is electrically connected with the negative output end;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with the positive output end;
the grid electrode of the sixth NMOS tube is electrically connected with the common mode feedback voltage end, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is electrically connected with the negative output end;
the grid electrode of the seventh NMOS tube is electrically connected with the common mode feedback voltage end, and the source electrode of the seventh NMOS tube is grounded; the drain electrode of the seventh NMOS tube is electrically connected with the positive output end;
the other end of the fifth control switch is electrically connected with the negative output end, and the other end of the sixth control switch is electrically connected with the positive output end.
Optionally, the load circuit includes:
the first capacitor, the second capacitor, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the fifth control switch and the sixth control switch;
one end of the first capacitor is electrically connected with the grid electrode of the fourth NMOS tube and one end of the fifth control switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is electrically connected with the grid electrode of the fifth NMOS tube and one end of the sixth control switch, and the other end of the second capacitor is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is electrically connected with the negative output end;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with the positive output end;
the grid electrode of the sixth NMOS tube is electrically connected with the negative output end, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is electrically connected with the negative output end;
the grid electrode of the seventh NMOS tube is electrically connected with the positive output end, the source electrode of the seventh NMOS tube is grounded, and the drain electrode of the seventh NMOS tube is electrically connected with the positive output end;
the grid electrode of the eighth NMOS tube is electrically connected with the positive output end, the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is electrically connected with the negative output end;
the grid electrode of the ninth NMOS tube is electrically connected with the negative output end, the source electrode of the ninth NMOS tube is grounded, and the drain electrode of the ninth NMOS tube is electrically connected with the positive output end;
the other end of the fifth control switch is electrically connected with the negative output end, and the other end of the sixth control switch is electrically connected with the positive output end.
Optionally, the method further comprises:
a reset switch for resetting the preamplifier circuit;
one end of the reset switch is electrically connected with the positive output end, and the other end of the reset switch is electrically connected with the negative output end.
Optionally, the method further comprises:
a common mode feedback circuit for generating a common mode voltage and outputting to the pre-amplifier circuit;
the positive input end of the common mode feedback circuit is electrically connected with the positive output end, the negative input end of the common mode feedback circuit is electrically connected with the negative output end, and the output end of the common mode feedback circuit is electrically connected with the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube.
According to a second aspect of the present invention, there is provided a low noise comparator comprising:
at least one pre-amplifier comprising a pre-amplifier circuit of the low noise comparator of any of the first aspects;
and the latch is used for latching the result of the comparator.
Optionally, when there are a plurality of the preamplifiers in the comparator, the preamplifiers are cascaded and the preamplifiers of the preamplifiers are identical.
The invention has the beneficial effects that: the complementary input pair consisting of the second PMOS tube, the third PMOS tube, the second NMOS tube and the third NMOS tube increases the transconductance of the input, compared with the common single-input pair structure, the gain can be obviously improved, the speed of the comparator is improved by approximately 2 times, and meanwhile, the input noise of the comparator is reduced; the folded cascode stage formed by the fourth PMOS tube and the fifth PMOS tube increases the output impedance, the gain and the swing of the preamplifier circuit; the load tube can stably output common-mode voltage by using the common-mode feedback circuit so as to reduce parasitic capacitance of an output node, thereby being beneficial to low-voltage design; the load tube uses a cross-coupled structure to provide an output common-mode voltage without an additional common-mode feedback circuit.
The system of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 shows a schematic diagram of a prior art preamplifier circuit according to the invention.
Fig. 2 shows a schematic diagram of a preamplifier circuit of a low noise comparator according to embodiment 1 of the invention.
Fig. 3 shows a schematic diagram of a preamplifier circuit of a low noise comparator according to embodiment 2 of the invention.
Fig. 4 shows a schematic diagram of a low noise comparator according to embodiment 3 of the present invention.
Fig. 5 shows a schematic diagram of a low noise comparator according to embodiment 3 of the present invention.
Fig. 6 shows a timing diagram of a low noise comparator according to embodiment 3 of the present invention.
Description of the reference numerals
1. PMOS, 2, PMOS, 3, NMOS, 4, NMOS, 5, NMOS, 6, NMOS, 7, NMOS, 8, NMOS, 9, NMOS, C1, first capacitor, C2, second capacitor, az, function switch azb, input switch, IP, positive input, IN, negative input, OP, positive output, ON, negative output, M1, first PMOS, M2, first NMOS, M3, second PMOS, M4, third PMOS, M5, second NMOS, M6, third NMOS, M7, fourth PMOS, M8, fifth PMOS, M9, fourth NMOS, M10, fifth NMOS pipe, M11, sixth NMOS pipe, M12, seventh NMOS pipe, M13, eighth NMOS pipe, M14, ninth NMOS pipe, azb, first control switch, azb2, first control switch, az1, third control switch, az2, fourth control switch, az3, fifth control switch, az4, sixth control switch, vbias1, first bias voltage, vbias2, second bias voltage, vbias3, third bias voltage, GND, ground terminal, VDD, power terminal, reset switch, vcm, common mode voltage, vcmfb, common mode feedback voltage.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are illustrated in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
A pre-amplifier circuit of a low noise comparator according to the present invention comprises:
the input circuit is used for receiving and amplifying the first input signal and the second input signal of the pre-amplifier and reducing input noise;
a current source circuit for supplying a bias current to the input circuit;
the isolation circuit is used for biasing the input circuit and the load circuit at different voltage values;
the load circuit is used for outputting the amplified first input signal and the amplified second input signal and counteracting offset voltage and flicker noise of the pre-amplifier;
and a control switch for selectively receiving/not receiving the first input signal and the second input signal by the control switch, and selectively turning on/off an Auto-zero function of the pre-amplifier by the control switch.
Specifically, the input circuit comprises two complementary input pairs formed by MOS tubes, wherein a first input signal is input into a first complementary input pair formed by 1 PMOS tube and 1 NMOS tube, and a second input signal is input into a second complementary input pair formed by 1 PMOS tube and 1 NMOS tube, so that the transconductance of the input can be increased; the current source circuit comprises a mirror current source composed of 1 PMOS tube and 1 NMOS tube, and is used for providing a current source for the input circuit; the isolation circuit comprises a folding cascode stage consisting of 2 PMOS tubes and is used for isolating the input circuit and the load circuit, so that the input circuit and the load circuit have different bias voltages; the load circuit comprises Auto-zero composed of 2 capacitors, 2 NMOS tubes and corresponding control switches, and is used for counteracting offset voltage and flicker noise of the comparator; the load circuit also comprises a common mode feedback function, which is realized by 2 NMOS tubes and the common mode feedback circuit, so that the pre-amplifier can output a stable common mode voltage, the parasitic capacitance of the output end of the pre-amplifier can be reduced, and the low-voltage design is facilitated; or, the load circuit in fig. 1 is also used, the load tube is in a cross-coupled structure, and an additional common-mode feedback circuit is not needed to provide the output common-mode voltage, but the parasitic capacitance of the output is increased, and meanwhile, the output common-mode voltage is limited to a gate-source voltage VGS, which is unfavorable for ultra-low voltage design.
In one example, a current source circuit includes:
the first PMOS tube and the first NMOS tube;
the grid electrode of the first PMOS tube is electrically connected with the first bias voltage, the source electrode of the first PMOS tube is electrically connected with the power supply end VDD, and the drain electrode of the first PMOS tube is electrically connected with the input circuit;
the grid electrode of the first NMOS tube is electrically connected with the second bias voltage, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first PMOS tube is electrically connected with the input circuit.
Specifically, the mirror current source is formed by the first PMOS tube and the first NMOS tube, so that a proper bias current is provided for the input circuit, and when the input first bias voltage and the input second bias voltage are constant, the mirror current source is a constant current source.
In one example, the input circuit includes:
the second PMOS tube, the third PMOS tube, the second NMOS tube, the third NMOS tube, the first control switch, the second control switch, the third control switch and the fourth control switch;
the grid electrode of the second PMOS tube is electrically connected with one end of the first control switch, the source electrode of the second PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube;
the grid electrode of the third PMOS tube is electrically connected with one end of the second control switch, the source electrode of the third PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube;
the grid electrode of the second NMOS tube is electrically connected with one end of the first control switch and one end of the third control switch, and the source electrode of the second NMOS tube is electrically connected with the drain electrode of the first NMOS tube;
the grid electrode of the third NMOS tube is electrically connected with one end of the second control switch and one end of the fourth control switch, and the source electrode of the third NMOS tube is electrically connected with the drain electrode of the first NMOS tube;
the other end of the first control switch is electrically connected with the positive input end, the other end of the second control switch is electrically connected with the negative input end, and the other end of the third control switch is electrically connected with the other end of the fourth control switch.
Specifically, the second PMOS transistor, the second NMOS transistor, the third PMOS transistor, and the third NMOS transistor form a complementary input pair, configured to receive and amplify the first input signal and the second input signal; when the first control switch and the second control switch are in an automatic-zero working mode, the first control switch and the second control switch are in an open state, the third control switch and the fourth control switch are in a closed state, and at the moment, the second PMOS tube, the second NMOS tube, the third PMOS tube and the third NMOS tube are short-circuited to output common-mode voltage; when the comparison working mode is adopted, the first control switch and the second control switch are in a closed state, the third control switch and the fourth control switch are in an open state, the first input signal is input to the second PMOS tube and the second NMOS tube, and the second input signal is input to the third PMOS tube and the third NMOS tube.
In one example, an isolation circuit includes:
a fourth PMOS tube and a fifth PMOS tube;
the grid electrode of the fourth PMOS tube is electrically connected with the third bias voltage, the source electrode of the fourth PMOS tube is electrically connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is electrically connected with the negative output end;
the grid electrode of the fifth PMOS tube is electrically connected with the third bias voltage, the source electrode of the fifth PMOS tube is electrically connected with the drain electrode of the third PMOS tube, and the drain electrode of the fifth PMOS tube is electrically connected with the positive output end.
Specifically, the fourth PMOS tube and the fifth PMOS tube are connected to a folding cathode, the third bias voltage is the gate voltage of the fourth PMOS tube and the fifth PMOS tube, the source of the fourth PMOS tube is connected to the working points of the second PMOS tube and the second NMOS tube, the source of the fifth PMOS tube is connected to the working points of the third PMOS tube and the third NMOS tube, the drain of the fourth PMOS tube is electrically connected to the negative output terminal, the drain of the fifth PMOS tube is electrically connected to the positive output terminal, and the third bias voltage is used for isolating the input circuit and the load circuit, so that the input circuit and the load circuit are biased at different voltages.
In one example, a load circuit includes:
the first capacitor, the second capacitor, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the fifth control switch and the sixth control switch;
one end of the first capacitor is electrically connected with the grid electrode of the fourth NMOS tube and one end of the fifth control switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is electrically connected with the grid electrode of the fifth NMOS tube and one end of the sixth control switch, and the other end of the second capacitor is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is electrically connected with the negative output end;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with the positive output end;
the grid electrode of the sixth NMOS tube is electrically connected with the common mode feedback voltage end, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is electrically connected with the negative output end;
the grid electrode of the seventh NMOS tube is electrically connected with the common mode feedback voltage end, the source electrode of the seventh NMOS tube is grounded, and the drain electrode of the seventh NMOS tube is electrically connected with the positive output end;
the other end of the fifth control switch is electrically connected with the negative output end, and the other end of the sixth control switch is electrically connected with the positive output end.
Specifically, an auto-zero function is realized through the first capacitor, the second capacitor, the fourth NMOS tube, the fifth control switch and the sixth control switch, when the auto-zero function is in an auto-zero working mode, the fifth control switch and the sixth control switch are closed, zero bias voltage of the preamplifier is amplified and stored on the first capacitor and the second capacitor, when the auto-zero function is in a comparison working mode, the fifth control switch and the sixth control switch are opened, and voltages in the first capacitor and the second capacitor are used for canceling the zero bias voltage; the sixth NMOS tube and the seventh NMOS tube are in common mode feedback, so that a stable common mode voltage is output by the comparator, the grid voltages of the sixth NMOS tube and the seventh NMOS tube are the common mode voltage provided by the common mode feedback circuit, the common mode feedback circuit is used for generating the common mode voltage and outputting the common mode voltage to the pre-amplifier circuit, the input end of the common mode feedback circuit is respectively and electrically connected with the positive output end and the negative output end of the pre-amplifier circuit, and the output end of the common mode feedback circuit is electrically connected with the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube.
In one example, a load circuit includes:
the first capacitor, the second capacitor, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the fifth control switch and the sixth control switch;
one end of the first capacitor is electrically connected with the grid electrode of the fourth NMOS tube and one end of the fifth control switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is electrically connected with the grid electrode of the fifth NMOS tube and one end of the sixth control switch, and the other end of the second capacitor is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is electrically connected with the negative output end;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with the positive output end;
the grid electrode of the sixth NMOS tube is electrically connected with the negative output end, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is electrically connected with the negative output end;
the grid electrode of the seventh NMOS tube is electrically connected with the positive output end, the source electrode of the seventh NMOS tube is grounded, and the drain electrode of the seventh NMOS tube is electrically connected with the positive output end;
the grid electrode of the eighth NMOS tube is electrically connected with the positive output end, the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is electrically connected with the negative output end;
the grid electrode of the ninth NMOS tube is electrically connected with the negative output end, the source electrode of the ninth NMOS tube is grounded, and the drain electrode of the ninth NMOS tube is electrically connected with the positive output end;
the other end of the fifth control switch is electrically connected with the negative output end, and the other end of the sixth control switch is electrically connected with the positive output end.
Specifically, the load circuit is the same as the load circuit in the prior art in fig. 1, and is composed of 2 capacitors, 6 NMOS transistors and 2 control switches, the eighth NMOS transistor and the ninth NMOS transistor are in cross-coupled structures, the output common-mode voltage is determined by the diode-coupled MOS transistors, that is, the gate-source voltage VGS, and the load circuit has the advantages that an additional common-mode feedback circuit is not required to provide the output common-mode voltage, the parasitic capacitance of the output is increased, and meanwhile, the output common-mode voltage is limited to one gate-source voltage VGS, which is unfavorable for ultra-low voltage design.
In one example, further comprising:
a reset switch for resetting the preamplifier circuit;
one end of the reset switch is electrically connected with the positive output end, and the other end of the reset switch is electrically connected with the negative output end.
Specifically, the reset switch is used for periodically shorting the output of the preamplifier, and after each time the comparator completes a result latch, the reset switch is turned on and off again, so that the output of the preamplifier is reset and ready to start the next comparison operation.
In one example, further comprising:
a common mode feedback circuit for generating a common mode voltage and outputting to the preamplifier circuit;
the positive input end of the common mode feedback circuit is electrically connected with the positive output end of the pre-amplifier, the negative input end of the common mode feedback circuit is electrically connected with the negative output end of the pre-amplifier, and the output end of the common mode feedback circuit is electrically connected with the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube.
Specifically, the pre-amplifier circuit is externally connected with a common mode feedback circuit to obtain a common mode feedback voltage, wherein the common mode feedback voltage is used for controlling an output common mode voltage of the pre-amplifier circuit, and the definition of the output common mode voltage is (VOP+VON)/2, wherein VOP is a positive output voltage, and VON is a negative output voltage; if the current of the power supply end is not matched with the current of the ground end, the common-mode voltage moves, so that the circuit deviates from the normal working voltage, and the common-mode feedback is used for controlling the output common-mode voltage to be a fixed value; the benefit of using a common mode feedback circuit to stabilize the output common mode voltage is that the parasitic capacitance of the output node can be reduced because none of the gates of the load tubes are tied to the output, while at the same time facilitating low voltage design.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
Example 1
As shown in fig. 2, the present embodiment provides a preamplifier circuit of a low noise comparator, including:
a power supply circuit comprising: the first PMOS tube M1 and the first NMOS tube M2 are mirror current sources, the grid electrode of the first PMOS tube M1 is electrically connected with the first bias voltage Vbias1, the source electrode of the first PMOS tube M1 is electrically connected with the power supply end VDD, and the drain electrode of the first PMOS tube M1 is electrically connected with the input circuit; the grid electrode of the first NMOS tube M2 is electrically connected with the second bias voltage Vbias2, the source electrode of the first NMOS tube M2 is grounded GND, and the drain electrode of the first PMOS tube M1 is electrically connected with the input circuit;
an input circuit comprising: the second PMOS tube M3, the third PMOS tube M4, the second NMOS tube M5, the third NMOS tube M6, the first control switch azb1, the second control switch azb2, the third control switch az1 and the fourth control switch az2; the second PMOS tube M3, the third PMOS tube M4, the second NMOS tube M5 and the third NMOS tube M6 are complementary input pairs; the grid electrode of the second PMOS tube M3 is electrically connected with one end of the first control switch azb, the source electrode of the second PMOS tube M3 is electrically connected with the drain electrode of the first PMOS tube M1, and the drain electrode of the second PMOS tube M3 is electrically connected with the drain electrode of the second NMOS tube M5; the grid electrode of the third PMOS tube M4 is electrically connected with one end of the second control switch azb, the source electrode of the third PMOS tube M4 is electrically connected with the drain electrode of the first PMOS tube M1, and the drain electrode of the third PMOS tube M4 is electrically connected with the drain electrode of the third NMOS tube M6; the grid electrode of the second NMOS tube M5 is electrically connected with one end of the first control switch azb1 and one end of the third control switch az1, and the source electrode of the second NMOS tube M5 is electrically connected with the drain electrode of the first NMOS tube M2; the grid electrode of the third NMOS tube M6 is electrically connected with one end of the second control switch azb and one end of the fourth control switch az2, and the source electrode of the third NMOS tube M6 is electrically connected with the drain electrode of the first NMOS tube M2; the other end of the first control switch azb1 is electrically connected with the positive input end IP, the other end of the second control switch azb is electrically connected with the negative input end IN, and the other end of the third control switch az1 is electrically connected with the other end of the fourth control switch az2;
an isolation circuit, comprising: the grid electrode of the fourth PMOS tube M7 is electrically connected with the third bias voltage Vbias3, the source electrode of the fourth PMOS tube M7 is electrically connected with the drain electrode of the second PMOS tube M3, and the drain electrode of the fourth PMOS tube M7 is electrically connected with the negative output end ON; the grid electrode of the fifth PMOS tube M8 is electrically connected with the third bias voltage Vbias3, the source electrode of the fifth PMOS tube M8 is electrically connected with the drain electrode of the third PMOS tube M4, and the drain electrode of the fifth PMOS tube M8 is electrically connected with the positive output end OP;
a load circuit, comprising: the first capacitor C1, the second capacitor C2, the fourth NMOS tube M9, the fifth NMOS tube M10, the sixth NMOS tube M11, the seventh NMOS tube M12, the fifth control switch installation az3 and the sixth control switch az4; one end of the first capacitor C1 is electrically connected with the grid electrode of the fourth NMOS tube M9 and one end of the fifth control switch az3, and the other end of the first capacitor C1 is grounded to GND; one end of the second capacitor C2 is electrically connected with the grid electrode of the fifth NMOS tube M10 and one end of the sixth control switch az4, and the other end of the second capacitor C2 is grounded to GND; the source electrode of the fourth NMOS tube M9 is grounded GND, and the drain electrode of the fourth NMOS tube M9 is electrically connected with the negative output end ON; the source electrode of the fifth NMOS tube M10 is grounded GND, and the drain electrode of the fifth NMOS tube M10 is electrically connected with the positive output end OP; the grid electrode of the sixth NMOS tube M11 is electrically connected with the common mode feedback voltage end Vcmfb, the source electrode of the sixth NMOS tube M11 is grounded GND, and the drain electrode of the sixth NMOS tube M11 is electrically connected with the negative output end ON; the grid electrode of the seventh NMOS tube M12 is electrically connected with the common mode feedback voltage end Vcmfb, and the source electrode of the seventh NMOS tube M12 is grounded GND; the drain electrode of the seventh NMOS tube M12 is electrically connected with the positive output end OP; the other end of the fifth control switch az3 is electrically connected with the negative output end ON, and the other end of the sixth control switch az4 is electrically connected with the positive output end OP;
one end of the reset switch reset is electrically connected with the positive output end OP, and the other end of the reset switch reset is electrically connected with the negative output end ON;
the positive input end of the common mode feedback circuit is electrically connected with the positive output end OP, the negative input end of the common mode feedback circuit is electrically connected with the negative output end ON, and the output end Vcmfb of the common mode feedback circuit is electrically connected with the grid electrode of the sixth NMOS tube M11 and the grid electrode of the seventh NMOS tube M12.
Example 2
As shown in fig. 3, the present embodiment provides a preamplifier circuit of a low noise comparator, including:
a power supply circuit comprising: the first PMOS tube M1 and the first NMOS tube M2 are mirror current sources, the grid electrode of the first PMOS tube M1 is electrically connected with the first bias voltage Vbias1, the source electrode of the first PMOS tube M1 is electrically connected with the power supply end VDD, and the drain electrode of the first PMOS tube M1 is electrically connected with the input circuit; the grid electrode of the first NMOS tube M2 is electrically connected with the second bias voltage Vbias2, the source electrode of the first NMOS tube M2 is grounded GND, and the drain electrode of the first PMOS tube M1 is electrically connected with the input circuit;
an input circuit comprising: the second PMOS tube M3, the third PMOS tube M4, the second NMOS tube M5, the third NMOS tube M6, the first control switch azb1, the second control switch azb2, the third control switch az1 and the fourth control switch az2; the second PMOS tube M3, the third PMOS tube M4, the second NMOS tube M5 and the third NMOS tube M6 are complementary input pairs; the grid electrode of the second PMOS tube M3 is electrically connected with one end of the first control switch azb, the source electrode of the second PMOS tube M3 is electrically connected with the drain electrode of the first PMOS tube M1, and the drain electrode of the second PMOS tube M3 is electrically connected with the drain electrode of the second NMOS tube M5; the grid electrode of the third PMOS tube M4 is electrically connected with one end of the second control switch azb, the source electrode of the third PMOS tube M4 is electrically connected with the drain electrode of the first PMOS tube M1, and the drain electrode of the third PMOS tube M4 is electrically connected with the drain electrode of the third NMOS tube M6; the grid electrode of the second NMOS tube M5 is electrically connected with one end of the first control switch azb1 and one end of the third control switch az1, and the source electrode of the second NMOS tube M5 is electrically connected with the drain electrode of the first NMOS tube M2; the grid electrode of the third NMOS tube M6 is electrically connected with one end of the second control switch azb and one end of the fourth control switch az2, and the source electrode of the third NMOS tube M6 is electrically connected with the drain electrode of the first NMOS tube M2; the other end of the first control switch azb1 is electrically connected with the positive input end IP, the other end of the second control switch azb is electrically connected with the negative input end IN, and the other end of the third control switch az1 is electrically connected with the other end of the fourth control switch az2;
an isolation circuit, comprising: the grid electrode of the fourth PMOS tube M7 is electrically connected with the third bias voltage Vbias3, the source electrode of the fourth PMOS tube M7 is electrically connected with the drain electrode of the second PMOS tube M3, and the drain electrode of the fourth PMOS tube M7 is electrically connected with the negative output end ON; the grid electrode of the fifth PMOS tube M8 is electrically connected with the third bias voltage Vbias3, the source electrode of the fifth PMOS tube M8 is electrically connected with the drain electrode of the third PMOS tube M4, and the drain electrode of the fifth PMOS tube M8 is electrically connected with the positive output end OP;
a load circuit, comprising: the first capacitor C1, the second capacitor C2, the fourth NMOS tube M9, the fifth NMOS tube M10, the sixth NMOS tube M11, the seventh NMOS tube M12, the eighth NMOS tube M13, the ninth NMOS tube M14, the fifth control switch installation az3 and the sixth control switch az4; one end of the first capacitor C1 is electrically connected with the grid electrode of the fourth NMOS tube M9 and one end of the fifth control switch az3, and the other end of the first capacitor C1 is grounded to GND; one end of the second capacitor C2 is electrically connected with the grid electrode of the fifth NMOS tube M10 and one end of the sixth control switch az4, and the other end of the second capacitor C2 is grounded to GND; the source electrode of the fourth NMOS tube M9 is grounded GND, and the drain electrode of the fourth NMOS tube M9 is electrically connected with the negative output end ON; the source electrode of the fifth NMOS tube M10 is grounded GND, and the drain electrode of the fifth NMOS tube M10 is electrically connected with the positive output end OP; the grid electrode of the sixth NMOS tube M11 is electrically connected with the negative output end ON, the source electrode of the sixth NMOS tube M11 is grounded GND, and the drain electrode of the sixth NMOS tube M11 is electrically connected with the negative output end ON; the grid electrode of the seventh NMOS tube M12 is electrically connected with the positive output end OP, and the source electrode of the seventh NMOS tube M12 is grounded GND; the drain electrode of the seventh NMOS tube M12 is electrically connected with the positive output end OP; the grid electrode of the eighth NMOS tube M13 is electrically connected with the positive output end OP, the source electrode of the eighth NMOS tube M13 is grounded GND, and the drain electrode of the eighth NMOS tube M13 is electrically connected with the negative output end ON; the grid electrode of the ninth NMOS tube M14 is electrically connected with the negative output end ON, and the source electrode of the ninth NMOS tube M14 is grounded GND; the drain electrode of the ninth NMOS tube M14 is electrically connected with the positive output end OP; the other end of the fifth control switch az3 is electrically connected with the negative output end ON, and the other end of the sixth control switch az4 is electrically connected with the positive output end OP;
one end of the reset switch reset is electrically connected with the positive output end OP, and the other end of the reset switch reset is electrically connected with the negative output end ON.
Example 3
The present embodiment provides a low noise comparator including:
a preamplifier including the preamplifier circuit of the low noise comparator described in embodiment 1 or embodiment 2;
a latch for latching a result of the comparator;
the pre-amplifier is mainly used for reducing the influence of the dynamic error of the latch, for example, offset voltage Offset of the latch is equivalent to the input and can be attenuated by Gain (Gain) of the pre-amplifier, and the Offset/Gain is used for reducing the Offset voltage Offset of the latch; the pre-amplification stage usually selects one stage to three stages according to the requirement, and the offset voltage of the pre-amplifier can be reduced through Auto-zero; when a plurality of preamplifiers are arranged in one comparator, the preamplifiers are cascaded, and the circuits of the preamplifiers are identical;
as shown in fig. 4, the low noise comparator includes a pre-amplifier A1 and a latch L, the pre-amplifier stage being one stage;
as shown in fig. 5, the low noise comparator includes a pre-amplifier A1, a pre-amplifier A2, and a latch L, and the pre-amplifier stage is two stages;
before the comparator enters a comparison function, auto-zero is firstly performed, a third control switch az1, a fourth control switch az2, a fifth control switch az3 and a sixth control switch az4 are closed, a first control switch azb and a second control switch azb are opened, an auto-zero working mode is entered at this time, a second PMOS tube M3, a third PMOS tube M4, a second NMOS tube M5 and a third NMOS tube M6 are short-circuited together, and zero bias voltage of the comparator is amplified and stored on a first capacitor C1 and a second capacitor C2;
then comparing, closing the first control switch azb and the second control switch azb, opening the third control switch az1, the fourth control switch az2, the fifth control switch az3 and the sixth control switch az4, entering a comparison working mode, connecting the second PMOS tube M3 and the second NMOS tube M5 to the positive input end IP, connecting the third PMOS tube M4 and the third NMOS tube M6 to the negative input end IN, amplifying the input signal to the output end through an input circuit, namely amplifying the first input signal to the negative output end ON through the second PMOS tube M3 and the second NMOS tube M5, amplifying the second input signal to the positive output end OP through the third PMOS tube M4 and the third NMOS tube M6, and canceling the zero bias voltage by the voltage ON the capacitor C1 and the capacitor C2;
the signals output by the negative output end ON and the positive output end OP are finally latched by the digital latch L, and the timing chart of the comparator of the present embodiment is shown in fig. 6;
after the latching is completed, the output of the comparator can be periodically shorted by closing the control switch reset, namely, the output of the comparator is reset;
after the comparator finishes one result latch, the output of the comparator is reset each time, and the next comparison is ready to be started; for each comparison, the signal pre-amplified by the comparator is finally latched by the digital latch L.
The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.

Claims (10)

1. A pre-amplifier circuit of a low noise comparator, comprising:
the input circuit is used for receiving and amplifying the first input signal and the second input signal of the pre-amplifier and reducing input noise;
a current source circuit for providing a bias current to the input circuit;
the isolation circuit is used for isolating the input circuit from the load circuit and enabling the input circuit and the load circuit to be biased at different voltages;
the load circuit is used for outputting the amplified first input signal and the second input signal and counteracting offset voltage and flicker noise of the pre-amplifier;
and a control switch for selectively receiving/not receiving the first input signal and the second input signal through the control switch, and selectively turning on/off an Auto-zero function of the preamplifier through the control switch.
2. The low noise comparator pre-amplifier circuit according to claim 1, wherein the current source circuit comprises:
the first PMOS tube and the first NMOS tube;
the grid electrode of the first PMOS tube is electrically connected with a first bias voltage, the source electrode of the first PMOS tube is electrically connected with the power supply end VDD, and the drain electrode of the first PMOS tube is electrically connected with the input circuit;
the grid electrode of the first NMOS tube is electrically connected with the second bias voltage, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first PMOS tube is electrically connected with the input circuit.
3. The low noise comparator pre-amplifier circuit of claim 2, wherein the input circuit comprises:
the second PMOS tube, the third PMOS tube, the second NMOS tube, the third NMOS tube, the first control switch, the second control switch, the third control switch and the fourth control switch;
the grid electrode of the second PMOS tube is electrically connected with one end of the first control switch, the source electrode of the second PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube;
the grid electrode of the third PMOS tube is electrically connected with one end of the second control switch, the source electrode of the third PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube;
the grid electrode of the second NMOS tube is electrically connected with one end of the first control switch and one end of the third control switch, and the source electrode of the second NMOS tube is electrically connected with the drain electrode of the first NMOS tube;
the grid electrode of the third NMOS tube is electrically connected with one end of the second control switch and one end of the fourth control switch, and the source electrode of the third NMOS tube is electrically connected with the drain electrode of the first NMOS tube;
the other end of the first control switch is electrically connected with the positive input end, the other end of the second control switch is electrically connected with the negative input end, and the other end of the third control switch is electrically connected with the other end of the fourth control switch.
4. A low noise comparator preamplifier circuit according to claim 3, wherein the isolation circuit comprises:
a fourth PMOS tube and a fifth PMOS tube;
the grid electrode of the fourth PMOS tube is electrically connected with the third bias voltage, the source electrode of the fourth PMOS tube is electrically connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is electrically connected with the negative output end;
the grid electrode of the fifth PMOS tube is electrically connected with the third bias voltage, the source electrode of the fifth PMOS tube is electrically connected with the drain electrode of the third PMOS tube, and the drain electrode of the fifth PMOS tube is electrically connected with the positive output end.
5. The low noise comparator pre-amplifier circuit according to claim 4, wherein the load circuit comprises:
the first capacitor, the second capacitor, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the fifth control switch and the sixth control switch;
one end of the first capacitor is electrically connected with the grid electrode of the fourth NMOS tube and one end of the fifth control switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is electrically connected with the grid electrode of the fifth NMOS tube and one end of the sixth control switch, and the other end of the second capacitor is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is electrically connected with the negative output end;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with the positive output end;
the grid electrode of the sixth NMOS tube is electrically connected with the common mode feedback voltage end, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is electrically connected with the negative output end;
the grid electrode of the seventh NMOS tube is electrically connected with the common mode feedback voltage end, and the source electrode of the seventh NMOS tube is grounded; the drain electrode of the seventh NMOS tube is electrically connected with the positive output end;
the other end of the fifth control switch is electrically connected with the negative output end, and the other end of the sixth control switch is electrically connected with the positive output end.
6. The low noise comparator pre-amplifier circuit according to claim 4, wherein the load circuit comprises:
the first capacitor, the second capacitor, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the fifth control switch and the sixth control switch;
one end of the first capacitor is electrically connected with the grid electrode of the fourth NMOS tube and one end of the fifth control switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is electrically connected with the grid electrode of the fifth NMOS tube and one end of the sixth control switch, and the other end of the second capacitor is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is electrically connected with the negative output end;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with the positive output end;
the grid electrode of the sixth NMOS tube is electrically connected with the negative output end, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is electrically connected with the negative output end;
the grid electrode of the seventh NMOS tube is electrically connected with the positive output end, and the source electrode of the seventh NMOS tube is grounded; the drain electrode of the seventh NMOS tube is electrically connected with the positive output end;
the grid electrode of the eighth NMOS tube is electrically connected with the positive output end, the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is electrically connected with the negative output end;
the grid electrode of the ninth NMOS tube is electrically connected with the negative output end, and the source electrode of the ninth NMOS tube is grounded; the drain electrode of the ninth NMOS tube is electrically connected with the positive output end;
the other end of the fifth control switch is electrically connected with the negative output end, and the other end of the sixth control switch is electrically connected with the positive output end.
7. The low noise comparator pre-amplifier circuit according to claim 5 or 6, further comprising:
a reset switch for resetting the preamplifier circuit;
one end of the reset switch is electrically connected with the positive output end, and the other end of the reset switch is electrically connected with the negative output end.
8. The low noise comparator pre-amplifier circuit of claim 5, further comprising:
a common mode feedback circuit for generating a common mode voltage and outputting to the pre-amplifier circuit;
the positive input end of the common mode feedback circuit is electrically connected with the positive output end, the negative input end of the common mode feedback circuit is electrically connected with the negative output end, and the output end of the common mode feedback circuit is electrically connected with the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube.
9. A low noise comparator, the low noise comparator comprising:
at least one pre-amplifier comprising a pre-amplifier circuit of the low noise comparator of any one of claims 1-8;
and the latch is used for latching the result of the comparator.
10. The low noise comparator according to claim 9, wherein when there are a plurality of said preamplifiers in said comparator, a plurality of said preamplifiers are cascaded and said preamplifier circuits of a plurality of said preamplifiers are identical.
CN202311065519.3A 2023-08-23 2023-08-23 Pre-amplifier circuit of low noise comparator and low noise comparator Active CN116760368B (en)

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