CN116754884A - Interference detection circuit, electrostatic discharge protection circuit and battery protection chip - Google Patents

Interference detection circuit, electrostatic discharge protection circuit and battery protection chip Download PDF

Info

Publication number
CN116754884A
CN116754884A CN202311060871.8A CN202311060871A CN116754884A CN 116754884 A CN116754884 A CN 116754884A CN 202311060871 A CN202311060871 A CN 202311060871A CN 116754884 A CN116754884 A CN 116754884A
Authority
CN
China
Prior art keywords
detection
circuit
interference
signal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311060871.8A
Other languages
Chinese (zh)
Other versions
CN116754884B (en
Inventor
高兴波
唐永生
黄立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Lipson Microelectronics Co ltd
Original Assignee
Chengdu Lipson Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Lipson Microelectronics Co ltd filed Critical Chengdu Lipson Microelectronics Co ltd
Priority to CN202311060871.8A priority Critical patent/CN116754884B/en
Priority to CN202311411929.9A priority patent/CN117452110A/en
Publication of CN116754884A publication Critical patent/CN116754884A/en
Application granted granted Critical
Publication of CN116754884B publication Critical patent/CN116754884B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/4285—Testing apparatus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00308—Overvoltage protection

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The embodiment of the invention provides an interference detection circuit, an electrostatic discharge protection circuit and a battery protection chip, and relates to the technical field of integrated circuits, wherein the interference detection circuit comprises: the invention takes the existing semiconductor element comprising the PN junction as the detection element based on the characteristic, and the interference judging sub-circuit judges whether the detection element is interfered based on the leakage magnitude of the detection element when the detection element is cut off, so that the condition that the circuit is affected by the interference signal can be quickly detected.

Description

Interference detection circuit, electrostatic discharge protection circuit and battery protection chip
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an interference detection circuit, an electrostatic discharge protection circuit and a battery protection chip.
Background
With the increasing sophistication, complexity and versatility of circuitry, such as integrated circuits, the circuitry is susceptible to such things as radio frequency and electromagnetic interference, such that its performance and circuit stability are affected.
The existing circuit system cannot quickly and automatically detect the interference signal, and the interference signal is detected by means of an external interference detector, so that the problems of accuracy and timeliness of interference detection exist, and the design of an anti-interference circuit of the back-end circuit is challenged.
Disclosure of Invention
The embodiment of the invention provides an interference detection circuit, an electrostatic discharge protection circuit and a battery protection chip, which can at least rapidly and self-detect interference signals and overcome the problems.
From a first aspect, an embodiment of the present invention discloses an interference detection circuit, including:
a detection element including a PN junction for receiving an interference signal;
and an interference judging sub-circuit for judging whether the detection element is interfered or not based on the leakage magnitude of the detection element when the detection element is cut off.
In one embodiment of the present invention, the interference determination sub-circuit includes: the device comprises a sampling module and a comparison module;
the sampling module generates a detection signal based on the leakage of the detection element when the detection element is cut off;
the comparison module judges whether the detection element is interfered or not based on the detection signal and the detection threshold value, and outputs an interference sign signal when the detection element is determined to be interfered.
In an embodiment of the invention, the sampling module includes a first resistor element connected in series with the detecting element, and generates the detection signal based on the leakage of the first resistor element and the detecting element when the first resistor element and the detecting element are turned off.
In an embodiment of the invention, a connection node between the first resistive element and the detection element is used for generating the detection signal.
In an embodiment of the invention, the sampling module includes a first MOS device connected in series with the detecting device, and generates the detecting signal based on the leakage current when the first MOS device and the detecting device are turned off.
In an embodiment of the present invention, a drain terminal or a source terminal of the first MOS device is connected in series with the detecting device, and a gate terminal of the first MOS device is connected to the drain terminal or an external input voltage Vb capable of turning on the first MOS device;
wherein, the detection signal is generated based on the leakage current when the first MOS element and the detection element are cut off.
In an embodiment of the present invention, the drain terminal or the source terminal of the first MOS device is used for being connected to the detection device, and is used for generating the detection signal.
In one embodiment of the present invention, the sampling module includes a capacitive element and a reset unit;
the capacitive element is connected in series with the detection element, and receives leakage current flowing out of the detection element to generate a detection signal;
the reset unit resets the voltage of the capacitive element to an initial state at preset time intervals.
In an embodiment of the present invention, the comparison module includes a load element and a second MOS element; the detection threshold is a conduction threshold of the second MOS element;
The load element is connected with the source end or the drain end of the second MOS element to form a series circuit, and the gate end of the second MOS element controls whether the series circuit is conducted or not based on the detection signal and the conduction threshold value so as to output an interference mark signal.
In one embodiment of the present invention, the load element is a resistor.
In one embodiment of the present invention, the comparison module includes:
a threshold voltage generation subunit for generating a detection threshold;
and the comparator is used for comparing the detection signal with a detection threshold value to output an interference mark signal.
In an embodiment of the present invention, the interference detection circuit further includes: a buffer sub-circuit;
the buffer sub-circuit is used for enhancing the interference sign signal output by the interference judging sub-circuit when the detection element is determined to be interfered and outputting the enhanced interference sign signal.
From a second aspect, an embodiment of the present invention further discloses an electrostatic discharge protection circuit, including:
one or more ESD modules for electrostatic discharge protection of a target voltage;
the interference detection circuit provided by the embodiment of the invention, wherein the interference mark signal output by the interference detection circuit is used for representing the risk of the ESD module being influenced by the interference signal;
and the functional module is related to the target voltage, and stops working or switches working states when receiving the interference sign signal.
In an embodiment of the present invention, the detection element in the interference detection circuit has the same structure as the ESD module.
In one embodiment of the invention, the detection element is smaller in size than the ESD module.
In an embodiment of the present invention, in the interference detection circuit, a high voltage or a low voltage connected after the sampling module and the detection element are connected in series is a target voltage.
In an embodiment of the present invention, in the interference detection circuit, the high voltage and the low voltage connected after the sampling module is connected in series with the detection element are not related to the target voltage.
From a third aspect, an embodiment of the present invention further discloses a battery protection chip, including: the electrostatic discharge protection circuit according to the embodiment of the invention; the target voltage is the voltage of the overcurrent detection end of the chip.
In an embodiment of the invention, the functional module is at least one of a charging overcurrent detection module, a discharging overcurrent detection module and a short circuit detection module.
The embodiment of the invention has the following advantages:
the embodiment of the invention provides an interference detection circuit, which comprises: the invention takes the existing semiconductor element comprising the PN junction as the detection element based on the characteristic, and the interference judging sub-circuit judges whether the detection element is interfered based on the leakage magnitude of the detection element when the detection element is cut off, so that the condition that the rapid self-detection circuit is influenced by the interference signal is detected;
The embodiment of the invention provides an electrostatic discharge protection circuit, which comprises: one or more ESD modules for electrostatic discharge protection of a target voltage; the interference detection circuit provided by the embodiment of the invention, wherein the interference mark signal output by the interference detection circuit is used for representing the risk of the ESD module being influenced by the interference signal; and the functional module is related to the target voltage, stops working or switches working states when receiving the interference sign signal, so that the influence of the interference signal on the working stability of the functional module and the accuracy of related detection results is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention.
FIG. 1 is a block diagram of an interference detection circuit of the present invention;
FIG. 2 is a schematic diagram of an interference detection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the interference detection circuit of the embodiment shown in FIG. 2;
FIG. 4 is a second schematic circuit diagram of the interference detection circuit of the embodiment shown in FIG. 2;
FIG. 5 is a third schematic circuit diagram of the interference detection circuit of the embodiment of FIG. 2;
FIG. 6 is a block diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention;
FIG. 7 is a block diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention;
FIG. 8 is a block diagram of a battery protection chip according to an embodiment of the invention;
fig. 9 is a block diagram schematically illustrating a battery protection chip according to another embodiment of the present invention.
Reference numerals illustrate:
10-an interference detection circuit; 11-detecting element, 12-interference judging sub-circuit, 13-buffer sub-circuit; 121-sampling module, 122-comparing module, 1211-first resistance element, 1212-first MOS element, 1221-load element, 1222-second MOS element;
20-an electrostatic discharge protection circuit; 21-ESD module, 22-functional module;
30-battery protection chip.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The present invention provides an interference detection circuit 10, as shown in fig. 1, comprising:
A detection element 11 including a PN junction for receiving an interference signal;
the interference determination sub-circuit 12 determines whether or not the detection element 11 is interfered based on the magnitude of leakage when the detection element 11 is turned off.
The PN junction has unidirectional conduction characteristics, when high voltage is connected to the N end of the PN junction and low voltage is connected to the P end of the PN junction, the PN junction is reversely biased to be in an off state, the equivalent resistance of the PN junction is infinite, and no or only tiny current flows to the P end when the PN junction is in the off state, and the PN junction is called PN junction leakage in the case. When the PN junction of the detection element 11 receives an interference signal, the leakage current of the PN junction increases rapidly, and the equivalent resistance thereof becomes small. The present invention uses a conventional semiconductor element including a PN junction as the detection element 11 based on this characteristic, and controls the detection element 11 to be in an off state to receive an interference signal in the off state, and the interference judging sub-circuit 12 is connected to the detection element 11, and can recognize whether the detection element 11 is interfered by judging the magnitude of the leakage of the detection element 11.
Compared with the prior art, the invention does not need to rely on an external interference detector to detect the interference signal, does not need to design a complex interface circuit to realize connection with the interference detector, and can save circuit area and cost.
There are many semiconductor elements including PN junctions including, but not limited to, diodes, transistors, MOS transistors, etc. The embodiment of the present invention can use any semiconductor element including a PN junction as the detection element 11 and connect the detection element 11 between high and low voltages so that the detection element 11 receives an interference signal in an off state. For example, if the detection element 11 is a diode, the anode of the diode is connected to a low voltage and the cathode is connected to a high voltage, so that the diode is turned off. For example, if the detection element 11 is an NMOS transistor, the source (N-doped) and the gate of the NMOS transistor may be commonly connected to a low voltage (e.g. grounded), and then the source (N-doped) may be connected to a high voltage (e.g. VDD) to form a GGNMOS, where the potential of the P-type substrate (or P-type well) of the NMOS transistor is lower than the potential of the source, so that the detection element 11 is in an off state based on the same principle as that the GGNMOS is used as an ESD protection device. For example, the detection element 11 is an NPN bipolar transistor, the base (P-type) and emitter (N-type) of which are connected to a low voltage, and the collector (N-type) is connected to a high voltage, so as to be in an off state.
Since the detection element 11 including the PN junction is connected between the high voltage and the low voltage to be in the off state, when there is an interference signal, the leakage current of the PN junction is remarkably increased and the equivalent resistance thereof becomes small. Based on this principle, the present invention can design different interference judging sub-circuits 12.
In an embodiment of the present invention, as shown in fig. 2, the interference determination subcircuit 12 may include a sampling module 121 and a comparing module 122; the sampling module 121 generates a detection signal based on the leakage of electricity when the detection element 11 is turned off; the comparison module 122 judges whether the detection element 11 is interfered based on the detection signal and the detection threshold value, and outputs an interference flag signal when it is determined that the detection element 11 is interfered. In the present embodiment, the sampling module 121 includes at least an element connected in series with the detection element 11 to generate a detection signal based on the leakage of electricity when the detection element 11 is turned off.
The detection signal may be a voltage signal or a current signal, and if the detection signal is a detection voltage, the detection threshold is a voltage threshold corresponding to the detection voltage; if the detection signal is a detection current, the detection threshold is a current threshold corresponding to the detection current.
The element connected in series with the detection element 11 may be a resistor, a MOS transistor, a capacitor, or the like. In fig. 2, a high voltage connected to the detection element 11 and the sampling module 121 after being connected in series is represented by a power supply voltage VDD, a low voltage is represented by a common ground voltage VSS, a PN junction in the detection element 11 is represented by a diode, and a signal output by the comparison module 122 is represented by OUT, wherein when the detection element 11 is disturbed, the signal OUT output by the comparison module 122 is valid, and represents the disturbance flag signal.
In some possible implementations, the sampling module 121 includes a first resistive element 1211 in series with the detection element 11, and generates the detection signal based on leakage of the first resistive element 1211 when the detection element 11 is turned off.
In this embodiment, the first resistor 1211 is connected to the series circuit in which the detection element 11 is located, and the first resistor 1211 may be directly connected to the detection element 11 or indirectly connected to the detection element 11 through a device such as a first MOS device 1212 described below.
If a plurality of first resistor elements 1211 are connected in series with the detecting element 11, a node between the plurality of first resistor elements 1211 may be used to output a detecting signal, for example, after the two first resistor elements 1211 are connected in series with the detecting element 11, an intermediate node voltage of the two first resistor elements 1211 may be used as the detecting signal; for example, a voltage difference across at least one first resistive element 1211 among the plurality of first resistive elements 1211 is used as the detection signal. Of course, as shown in fig. 3, a first resistor 1211 may be connected in series with the detecting element 11, and a connection node between the first resistor 1211 and the detecting element 11 may be used to generate the detecting signal.
The implementation principle of the detection signal output after the first resistor element 1211 is connected in series with the detection element 11 in the off state, which can characterize whether the detection element 11 receives the interference signal, is described below, and will not be repeated herein.
In some possible implementations, the sampling module 121 includes a first MOS element 1212 in series with the detection element 11, and generates the detection signal based on leakage when the first MOS element 1212 and the detection element 11 are turned off.
Further, as shown in fig. 4 or fig. 5, the drain terminal or the source terminal of the first MOS device 1212 is connected in series with the detection device 11, and the gate terminal of the first MOS device 1212 is connected to the drain terminal thereof or to the external input voltage Vb capable of turning on the first MOS device 1212; wherein, the detection signal is generated based on the leakage current when the first MOS element 1212 and the detection element 11 are turned off.
In this implementation manner, the first MOS element 1212 may be a PMOS tube or an NMOS tube, where a source or a drain of the first MOS element 1212 is connected to a serial circuit where the detection element 11 is located, and the source or the drain of the first MOS element 1212 may be directly connected to the detection element 11 or indirectly connected to the detection element 11 through a resistor, for example.
If a plurality of first MOS devices 1212 are connected in series with the detection device 11, a detection signal can be output by using a connection node between any two of the first MOS devices 1212. For example, two first MOS elements 1212 and the detecting element 11 are disposed in the same series circuit, wherein the drain and gate of the first MOS element 1212 (for convenience of description, the first MOS element 1212 is referred to as a) are commonly connected to the power supply voltage VDD, the source of the first MOS element 1212 (for convenience of description, the first MOS element 1212 is referred to as B) is connected to the drain and gate of the second first MOS element 1212, the source of the second first MOS element 1212 is connected to the detecting element 11, the detecting element 11 is grounded, and in this example, the source of a may be used as an output node of the sampling module 121 to generate the detecting signal, or the source of B may be used as an output node of the sampling module 121 to generate the detecting signal.
Alternatively, a source or drain of the first MOS device 1212 may be connected in series with the detecting device 11, and a gate of the first MOS device 1212 may be connected to a drain thereof or to an external input voltage Vb capable of turning on the first MOS device 1212, and the drain or source of the first MOS device 1212 connected to the detecting device 11 may be used to generate the detecting signal. For example, in fig. 4 and 5, the drain terminal of the first MOS device 1212 is directly connected to the detection device 11, and the detection signal is generated from the drain terminal of the first MOS device 1212.
The implementation principle that the detection signal output after the first MOS element 1212 is connected in series with the detection element 11 in the off state can represent whether the detection element 11 receives the interference signal may be referred to the following description, which is not repeated herein.
Since the circuit structure of the sampling module 121 connected to the detection element 11 is unchanged, when the detection element 11 is disturbed to cause an increase in leakage current, the detection signal is also increased or decreased.
In some possible implementations (not shown), sampling module 121 includes a capacitive element and a reset unit; a capacitive element connected in series with the detection element 11, the capacitive element receiving a leakage current flowing out of the detection element 11 to generate a detection signal; the reset unit resets the voltage of the capacitive element to an initial state at preset time intervals. In this embodiment, the capacitive element is connected to the P-terminal of the detecting element 11 to receive the leakage current flowing out of the detecting element 11, and the leakage current charges the capacitive element, so that the output voltage of the capacitive element changes, and when the detecting element 11 receives the leakage current due to the interference signal, the output voltage of the capacitive element changes significantly, so that the output voltage of the capacitive element can be used as the detection signal. Since the detection element 11 also generates a small leakage current when the interference signal is not received, the continuous charging of the capacitive element by the small leakage current may cause the output voltage of the capacitive element to reach the detection threshold, thereby misjudging. In order to avoid misjudgment of interference, the sampling module 121 of this implementation manner further includes a reset unit, where the reset unit resets (e.g. may use a manner of discharging the capacitive element) the voltage of the capacitive element to an initial state according to a preset time interval, where the preset time interval should be less than a duration of the foregoing minute leakage current to charge the capacitive element so that the output voltage of the capacitive element reaches the detection threshold.
In some possible implementations, as shown in fig. 3-5, the comparison module 122 includes a load element 1221 and a second MOS element 1222, wherein the detection threshold is an on threshold of the second MOS element 1222; the load element 1221 and the source or drain of the second MOS element 1222 are connected to form a series circuit, and the gate of the second MOS element 1222 controls whether the series circuit is turned on or not based on the detection signal and the on threshold thereof to output an interference flag signal. In this implementation, the detection signal is input to the gate terminal of the second MOS element 1222, and whether the second MOS element 1222 is turned on or not can be controlled based on whether the difference between the detection signal and the source terminal of the second MOS element 1222 exceeds the turn-on threshold, so as to realize whether the series circuit is turned on or not. Since the output voltage of the load element 1221 or the voltage of the connection node of the load element 1221 and the second MOS element 1222 is definitely different when the series circuit is conductive or non-conductive, the present embodiment may use the voltage signal of the connection node of the load element 1221 and the second MOS element 1222 or the voltage signal output by the load element 1221 as the interference flag signal.
The second MOS device 1222 may be implemented as an NMOS device or as a PMOS device. Since the NMOS has a higher G potential than S potential, its VGS is generally represented by a positive voltage, the PMOS has a higher S potential than G potential, and its VGS is generally represented by a negative voltage. For ease of description, the on threshold of the second MOS element 1222 to which the present invention refers should be understood as the absolute value of VGS.
The interference flag signal may be designed to be output when the series circuit is conductive or to be output when the series circuit is non-conductive, and the interference detection circuit 10 may be designed based on practical application, so as to determine the signal waveform of the interference flag signal.
The load element 1221 may be a resistor, a MOS transistor, a capacitor, or the like. In the examples of fig. 3-5, the load element 1221 and the second MOS element 1222 form a series circuit connected between the power supply voltage and ground, and the invention is not limited with respect to whether the load element 1221 or the second MOS element 1222 is grounded in the series circuit.
Based on the foregoing implementations, the output of the interference flag signal will be described using some of the circuits shown in fig. 3-5 as examples.
In an example, as shown in fig. 3, the sampling module 121 is a first resistor 1211, where one end of the first resistor 1211 is connected to a power voltage, the other end is connected to an N-terminal of the detecting element 11, and a P-terminal of the detecting element 11 is connected to a common ground Voltage (VSS), and one end of the first resistor 1211 connected to the detecting element 11 is used for outputting a detection signal. The comparison module 122 includes a load element 1221 and a second MOS element 1222, the second MOS element 1222 being PMOS, the source terminal of which is connected to the power supply voltage VDD, the gate terminal of which is connected to the detection signal, and the drain terminal of which is grounded through the load element 1221.
When the detecting element 11 is not disturbed, the equivalent resistance of the detecting element 11 is infinite because the detecting element 11 is turned off, the circuit where the first resistive element 1211 and the detecting element 11 are located corresponds to an open circuit, and although only a very small leakage current is generated on the detecting element 11 at this time, the leakage current is not large enough to pull down the voltage of the intermediate node between the first resistive element 1211 and the detecting element 11, so that the detecting signal is substantially equal to VDD at this time. Since the detection signal is substantially equal to VDD, the difference between the detection signal and the source terminal of the second MOS element 1222 is smaller than the detection threshold VGS, the second MOS element 1222 will not be turned on either, the voltage of the connection node of the load element 1221 and the second MOS element 1222 is pulled to 0 potential, and the load element 1221 and the second MOS element 1222 form a series circuit to output a low-level signal OUT, indicating that the detection element 11 is not disturbed.
When the detection element 11 receives the interference signal, the leakage current generated in the detection element 11 increases instantaneously, the equivalent resistance of the detection element 11 decreases sharply, the voltage at the connection node between the first resistor element 1211 and the detection element 11 is pulled down rapidly, that is, the detection signal is pulled down, the difference between the detection signal and the source terminal of the second MOS element 1222 increases and exceeds the detection threshold VGS, at this time, the load element 1221 and the second MOS element 1222 form a series circuit to be turned on, the voltage at the connection node between the load element 1221 and the second MOS element 1222 is raised, and the output signal OUT is at a high level (interference flag signal), indicating that the detection element 11 is interfered.
In another example, the second MOS element 1222 may also be implemented as an NMOS with the other circuits shown in fig. 3 unchanged, with the interference flag signal set to a low level. When the detection element 11 is not disturbed, the detection signal is substantially equal to VDD, the second MOS element 1222 is turned on, and the voltage output of the connection node of the load element 1221 and the second MOS element 1222 is high, indicating that the detection element 11 is not disturbed; when the detection element 11 receives the interference signal, the leakage current generated on the detection element 11 increases instantaneously, the voltage of the connection node between the first resistor element 1211 and the detection element 11 is pulled down rapidly, that is, the detection signal is pulled down rapidly, the difference between the detection signal and the source terminal of the second MOS element 1222 is smaller than the detection threshold VGS, the second MOS element 1222 is turned off, the voltage of the connection node between the load element 1221 and the second MOS element 1222 is pulled to 0 potential, and at this time, a low-level interference flag signal is output on the load element 1221, which indicates that the detection element 11 is interfered. The power consumption in this way is higher and is generally not preferred.
In still another example, in the case where the other circuit shown in fig. 3 is unchanged, if the N terminal of the detecting element 11 is connected to the power supply voltage and the P terminal is connected to the common ground voltage through the first resistor element 1211, the first resistor element 1211 generates the detecting signal based on the leakage current flowing out of the detecting element 11. When the detection element 11 is disturbed, the generated detection signal of the first resistance element 1211 increases significantly. The second MOS element 1222 may be implemented by using an NMOS, the difference between the detection signal and the source terminal of the second MOS element 1222 is greater than VGS, the second MOS element 1222 is turned on, so that the series circuit is turned on, the voltage of the connection node between the load element 1221 and the second MOS element 1222 is raised, and a high-level interference flag signal is output, which indicates that the detection element 11 is interfered.
In yet another example, regarding the scheme of fig. 4, the first MOS device 1212 and the second MOS device 1222 are implemented as PMOS, and the first MOS device 1212 and the second MOS device 1222 form a common-gate current mirror structure. The source terminal of the first MOS element 1212 is connected to the power supply voltage VDD, the gate terminal and the drain terminal are connected to the N terminal of the detection element 11, and the P terminal of the detection element 11 is connected to the common ground voltage VSS.
When the detecting element 11 is not interfered, the equivalent resistance of the detecting element 11 is infinite, the circuits where the first MOS element 1212 and the detecting element 11 are located are equivalent to open circuits, at this time, the source terminal, the gate terminal and the drain terminal of the first MOS element 1212 are substantially the same in potential, that is, the detecting signal output from the gate terminal of the first MOS element 1212 is substantially equal to VDD, the second MOS element 1222 is not turned on, the voltage of the connection node between the load element 1221 and the second MOS element 1222 is pulled to 0 potential, at this time, the load element 1221 and the second MOS element 1222 form a series circuit to output a low level, which indicates that the detecting element 11 is not interfered.
When the detection element 11 receives the interference signal, the leakage current generated in the detection element 11 increases instantaneously, the equivalent resistance of the detection element 11 decreases sharply, the potential of the gate terminal and the drain terminal of the first MOS element 1212 is lowered, the first MOS element 1212 and the second MOS element 1222 are turned on, the second MOS element 1222 duplicates the current of the circuit in which the first MOS element 1212 and the detection element 11 are located, and the load element 1221 outputs a high-level interference flag signal based on the duplicated current, indicating that the detection element 11 is interfered.
In yet another example, unlike fig. 4, in the scheme shown in fig. 5, the gate terminal of the first MOS element 1212 may be connected to the external input voltage Vb, and the first MOS element 1212 is turned on slightly under the action of the input voltage Vb, but the equivalent resistance of the detection element 11 is infinite when the detection element 11 is not interfered, and at this time, the detection signal output by the drain terminal of the first MOS element 1212 is also substantially close to VDD, so that the second MOS element 1222 cannot be turned on; when the detection element 11 receives the interference signal, the drain terminal potential of the first MOS element 1212 is pulled down, so that the difference between the detection signal and the source terminal of the second MOS element 1222 is greater than VGS thereof, the second MOS element 1222 is turned on, and finally the voltage of the connection node between the load element 1221 and the second MOS element 1222 is raised, and a high-level interference flag signal is output, indicating that the detection element 11 is interfered.
In some possible implementations (not shown), the comparison module 122 includes a threshold voltage generation subunit and a comparator: the threshold voltage generation subunit is used for generating a detection threshold value; the comparator is used for comparing the detection signal with a detection threshold value to output an interference mark signal. Based on the description similar to the foregoing, when the detection element 11 is disturbed to cause an increase in leakage current, the detection signal also changes, and by comparing the detection signal with the detection threshold value, it can be effectively recognized whether the detection element 11 is disturbed, thereby outputting the disturbance flag signal when the detection element 11 is disturbed.
If the detection signal is greater than the detection threshold value, the detection element 11 is interfered, and the logic signal output by the comparator when the detection signal is greater than the detection threshold value is used as the interference mark signal; if the detection signal is smaller than the detection threshold value, which indicates that the detection element 11 is interfered, the logic signal output by the comparator is used as the interference flag signal when the detection signal is smaller than the detection threshold value.
Based on the foregoing, it can be seen that when the detection element 11 is affected by the interference signal, the high potential of the detection element 11 is pulled down, and the low potential is pulled down. Thus, in some other embodiments, the present invention may directly connect the interference determination subcircuit 12 with the high voltage or the low voltage connected to the detecting element 11, and determine whether the detecting element 11 is interfered by determining whether the high potential is significantly pulled down or whether the low potential is significantly pulled up, and outputting an interference flag signal when the high potential is significantly pulled down or the low potential is significantly pulled up. In a specific circuit, the interference judging sub-circuit 12 may include a comparing module 122; the detection element 11 is connected between the voltage a and the voltage B to be in an off state; the comparison module 122 determines whether the detection element 11 is disturbed based on the voltage a or the voltage B and the threshold voltage. The threshold voltage is set on the basis of the voltage a or the voltage B to be significantly different from the leakage caused by the non-interference signal.
In an embodiment of the present invention, as shown in fig. 1 and 2, the interference detection circuit 10 of the present invention may further include: a buffer sub-circuit 13; the buffer sub-circuit 13 is configured to enhance and output the interference flag signal output by the interference determination sub-circuit 12 when it is determined that the detection element 11 is interfered.
Based on the interference detection circuit 10 provided by the embodiment of the invention, the condition that the circuit is influenced by the interference signal can be detected quickly, and in practical application, the interference detection circuit 10 can be combined with some target circuits which are easily influenced by the interference signal, so that the target circuits do some processing based on the interference mark signal output by the interference detection circuit 10, and the influence of the interference on the target circuits is reduced.
For example, existing integrated circuits are always under threat of ESD (Electro-Static discharge), and thus some existing chip circuits are commonly provided with ESD modules 21 for electrostatic discharge protection. The ESD module 21 is connected between two high and low voltages to form a cut-off channel, so as to avoid the influence of static discharge on the normal operation of the chip circuit. However, when the ESD module 21 is interfered by radiation such as radio frequency or electromagnetic wave, the generated leakage current will become larger instantaneously, and the leakage current will cause the two high and low voltages connected to the ESD module 21 to be affected, such as the high voltage is pulled down and the low voltage is pulled up, thereby affecting the operation stability of the functional module based on the high voltage or the low voltage and the accuracy of the related detection result.
In view of this, the present invention provides an electrostatic discharge protection circuit 20, as shown in fig. 6 and 7, the electrostatic discharge protection circuit 20 comprising:
one or more ESD modules 21 for electrostatic discharge protection of a target voltage;
in the interference detection circuit 10 according to the embodiment of the present invention, the interference flag signal output by the interference detection circuit 10 is used to characterize the risk of the ESD module 21 being affected by the interference signal;
and a function module 22 associated with the target voltage, the function module 22 stopping operation or switching the operation state when receiving the interference flag signal.
As shown in fig. 6 and 7, the interference detection circuit 10 includes a detection element 11 including a PN junction for receiving an interference signal, and an interference determination sub-circuit 12, and the interference determination sub-circuit 12 determines whether the detection element 11 is interfered based on the magnitude of leakage when the detection element 11 is turned off, and outputs an interference flag signal when it is determined that the detection element 11 is interfered. The relevant explanation of the interference detection circuit 10 may be referred to the foregoing, and will not be repeated here. The ESD protection circuit 20 of the present invention has the above-mentioned interference detection circuit 10, when the interference detection circuit 10 outputs the interference flag signal, it indicates that the ESD module 21 is at risk of being affected by the interference signal, at this time, the functional module 22 stops working or switches working states when receiving the interference flag signal, so that the target voltage significantly changes due to the influence of the interference signal on the ESD module 21, and thus the influence on the functional module 22 is reduced.
In the present invention, the target voltage may be a high voltage or a low voltage to which the ESD module 21 is connected. For example, the ESD module 21 is connected between the power supply voltage VDD and the voltage to be measured Vx, where Vx is the target voltage when Vx is lower than VDD. For example, the ESD module 21 is connected between the voltage to be measured Vx and the common ground voltage, where the voltage to be measured Vx is a high voltage, which is a target voltage according to the present invention.
In the interference detection circuit 10 of the present invention, the high-low voltage to which the circuit of the detection element 11 is connected may be the same as or different from the ESD module 21. For example, one or more ESD modules 21 are connected between the supply voltage VDD and a target voltage, or between the target voltage and a common ground voltage; in the interference detection circuit 10, the sampling module 121 and the detection element 11 are connected in series and then can be connected between the power voltage VDD and the target voltage, or between the target voltage and the common ground voltage, or between the power voltage VDD and the common ground voltage VSS.
In some possible implementations, as shown in fig. 6, in the interference detection circuit 10, the high voltage or the low voltage connected after the sampling module 121 is connected in series with the detection element 11 is the target voltage. In the ESD protection circuit, the voltage to which the ESD module is connected is generally the port voltage of the chip, so the target voltage of the ESD module to be subjected to the ESD protection also belongs to a port voltage, such as an overcurrent detection terminal (indicated by a VM terminal in the drawing). Because the port voltage such as the target voltage is easier to receive or is more sensitive to the interference signal, in order to effectively and timely detect the interference signal, one end of the sampling module connected in series with the detection element is connected with the target voltage.
In some possible implementations, as shown in fig. 7, in the interference detection circuit 10, the high voltage and the low voltage connected after the sampling module 121 is connected in series with the detection element 11 are uncorrelated with the target voltage. It can be understood that the high voltage or the low voltage directly or indirectly connected after the sampling module 121 is connected in series with the detecting element 11 is not the target voltage, so as to reduce the influence of the leakage current on the target voltage during the interference detection stage as much as possible. If the target voltage is the voltage Vx to be measured, the sampling module 121 and the detecting element 11 are connected in series and then connected between the power voltage VDD and the common ground voltage VSS.
In some possible implementations, the detection element 11 in the disturbance detection circuit 10 is identical in structure to the ESD module 21 (not shown). Because the detection element 11 and the ESD module 21 have the same structure, the receiving capability of the detection element 11 and the ESD module 21 for the interference signal can be infinitely close, so that when the detection element 11 receives the interference signal, the high probability ESD module 21 also receives the interference signal, and in this case, the interference flag signal output by the interference detection circuit 10 can more effectively represent the risk that the ESD module 21 is affected by the interference signal.
In some possible implementations, the detection element 11 is smaller in size than the ESD module 21, which is advantageous for saving circuit area. Particularly, in the case where the detection element 11 in the interference detection circuit 10 has the same structure as the conventional ESD module 21, a larger chip area can be saved by adopting the detection element 11 of a smaller size. If both the ESD module 21 and the detection element 11 are implemented with GGNMOS, the detection element 11 may be implemented with GGNMOS having a smaller size.
Based on the same inventive concept, the present invention also provides a battery protection chip 30, as shown in fig. 8 and 9, including: an electrostatic discharge protection circuit 20 according to an embodiment of the present invention; the target voltage is the voltage of the overcurrent detection terminal (indicated by a VM terminal in the drawing) of the chip.
As shown in fig. 8 and 9, the electrostatic discharge protection circuit 20 includes:
one or more ESD modules 21 for electrostatic discharge protection of the voltage of the overcurrent detection terminal, the one or more ESD modules 21 being connected between the power supply voltage VDD and the voltage of the overcurrent detection terminal (represented by a VM terminal in the drawing);
the interference detection circuit 10 according to the embodiment of the present invention, wherein the interference detection circuit 10 includes a detection element 11 including a PN junction for receiving an interference signal, and an interference determination sub-circuit 12, the interference determination sub-circuit 12 determines whether the detection element 11 is interfered based on a leakage magnitude when the detection element 11 is turned off, and outputs an interference flag signal when it is determined that the detection element 11 is interfered, and the interference flag signal output by the interference detection circuit 10 is used for characterizing that the ESD module 21 is at risk of being affected by the interference signal;
And a function module 22 related to the voltage of the overcurrent detection terminal, wherein the function module 22 stops working or switches working states when receiving the interference sign signal.
The explanation about the esd protection circuit 20 is referred to the foregoing, and will not be repeated here.
In fig. 8 and fig. 9, the difference is that, in fig. 8, the interference judging sub-circuit 12 is connected in series with the detecting element 11 and then connected between the power supply voltage VDD and the voltage of the overcurrent detecting end (indicated by a VM terminal in the drawing), so that the detecting element 11 can effectively and timely receive the interference signal, and further, the electrostatic discharge protection circuit 20 performs a corresponding process of stopping the operation of the functional module 22 related to the voltage of the overcurrent detecting end or switching the operation state of the functional module 22 related to the voltage of the overcurrent detecting end; in fig. 9, the disturbance determination sub-circuit 12 is connected in series with the detection element 11 and then connected between the power supply voltage VDD and the common ground voltage VSS, so as to reduce the influence of the leakage current on the over-current detection terminal voltage during the disturbance detection stage as much as possible.
The current battery protection chip 30 is generally provided with a charging overcurrent detection module, a discharging overcurrent detection module, a short circuit detection module and the like, and the charging overcurrent detection module, the discharging overcurrent detection module and the short circuit detection module all detect the voltage of the overcurrent detection end and then compare the detected voltage with the respective detection threshold values, so as to judge whether the battery is charged overcurrent, discharged overcurrent, short circuit and the like. The functional module 22 of the embodiment of the present invention may be at least one of a charge overcurrent detection module, a discharge overcurrent detection module, and a short circuit detection module.
In the battery protection chip 30, one or more ESD modules 21 may be connected between the over-current detection terminal and the common ground terminal, or may be connected between the power voltage VDD and the over-current detection terminal, and when the ESD module 21 is affected by an interference signal such as a radio frequency, the one or more ESD modules 21 generate a larger leakage current, and the leakage current flows to the over-current detection terminal to make its voltage become larger or flows to a lower potential to pull the voltage of the over-current detection terminal down. In this case, the voltages detected by the charge overcurrent detection module, the discharge overcurrent detection module and the short circuit detection module are inaccurate, and thus the accuracy of judging whether the battery is charged overcurrent, discharged overcurrent and short circuit respectively is affected. According to the embodiment of the invention, when the interference sign signal is output by the interference detection circuit 10, the ESD module 21 is characterized by the risk of being affected by the interference signal, and at least one of the electric overcurrent detection module, the discharge overcurrent detection module and the short circuit detection module related to the voltage of the overcurrent detection end stops working when receiving the interference sign signal, so that the influence of the interference signal on the respective functions of the ESD module can be effectively reduced.
Since the interference signal such as radio frequency is generally intermittent or understood to be periodic, the time of a single application to the ESD module 21 is short, and the trigger time of the short circuit detection is short, so that the influence of the interference signal on the short circuit detection module is the greatest, preferably, the functional module 22 is at least a short circuit detection module. And stopping working when the short circuit detection module receives the interference sign signal so as to avoid the short circuit of the erroneous judgment circuit. Meanwhile, because the duration of the interference signal is shorter, when the interference signal disappears, the interference detection circuit 10 will not output the interference sign signal or the output signal will turn over, so that the short circuit detection module will recover to the normal working state, and the short circuit detection function of the short circuit detection module will not be affected.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The foregoing has outlined rather broadly the more detailed description of the invention in order that the detailed description of the invention that follows may be better understood, and in order that the present contribution to the art may be better appreciated. While various modifications of the embodiments and applications of the invention will occur to those skilled in the art, it is not necessary and not intended to be exhaustive of all embodiments, and obvious modifications or variations of the invention are within the scope of the invention.

Claims (19)

1. An interference detection circuit, comprising:
a detection element including a PN junction for receiving an interference signal;
and the interference judging sub-circuit is used for judging whether the detection element is interfered or not based on the leakage magnitude of the detection element when the detection element is cut off.
2. The interference detection circuit of claim 1, wherein,
The interference judging sub-circuit includes: the device comprises a sampling module and a comparison module;
the sampling module generates a detection signal based on the leakage of the detection element when the detection element is cut off;
the comparison module judges whether the detection element is interfered or not based on the detection signal and a detection threshold value, and outputs an interference sign signal when the detection element is determined to be interfered.
3. The tamper detection circuit of claim 2, wherein the sampling module includes a first resistive element in series with the detection element, the detection signal being generated based on leakage of current when the first resistive element and the detection element are turned off.
4. The interference detection circuit of claim 3, wherein,
wherein a connection node between the first resistive element and the detection element is used to generate the detection signal.
5. The tamper detection circuit of claim 2, wherein the sampling module includes a first MOS element in series with the detection element, the detection signal being generated based on leakage of current when the first MOS element and the detection element are turned off.
6. The tamper detection circuit of claim 5, wherein,
The drain end or the source end of the first MOS element is used for being connected in series with the detection element, and the gate end of the first MOS element is used for being connected with the drain end of the first MOS element or with an external input voltage Vb which can enable the first MOS element to be conducted;
and generating the detection signal based on the leakage when the first MOS element and the detection element are cut off.
7. The tamper detection circuit of claim 6, wherein,
the drain terminal or the source terminal of the first MOS element connected with the detection element is used for generating the detection signal.
8. The interference detection circuit of claim 2, wherein,
the sampling module comprises a capacitive element and a reset unit;
the capacitive element is connected in series with the detection element, and receives leakage current flowing out of the detection element to generate the detection signal;
the reset unit resets the voltage of the capacitive element to an initial state at preset time intervals.
9. The interference detection circuit of any one of claims 2-8 wherein,
the comparison module comprises a load element and a second MOS element; the detection threshold is a conduction threshold of the second MOS element;
The load element is connected with the source end or the drain end of the second MOS element to form a series circuit, and the gate end of the second MOS element controls whether the series circuit is conducted or not based on the detection signal and the conduction threshold value so as to output the interference sign signal.
10. The interference detection circuit of claim 9, wherein,
the load element is a resistor.
11. The interference detection circuit of any one of claims 2-8 wherein,
the comparison module comprises:
a threshold voltage generation subunit for generating the detection threshold;
and the comparator is used for comparing the detection signal with the detection threshold value so as to output the interference mark signal.
12. The interference detection circuit according to claim 1 or 2, wherein,
further comprises: a buffer sub-circuit;
the buffer sub-circuit is used for outputting the interference sign signal which is output by the interference judging sub-circuit after the interference judging sub-circuit is determined to be interfered by the detection element.
13. An electrostatic discharge protection circuit, comprising:
one or more ESD modules for electrostatic discharge protection of a target voltage;
the tamper detection circuit of any one of claims 1-12, wherein a tamper flag signal output by the tamper detection circuit is used to characterize the ESD module as being at risk of being affected by a tamper signal;
And the functional module is related to the target voltage, and stops working or switches working states when the functional module receives the interference sign signal.
14. The electrostatic discharge protection circuit of claim 13, wherein,
the detection element in the interference detection circuit has the same structure as the ESD module.
15. The electrostatic discharge protection circuit of claim 13 or 14, wherein,
the detection element has a size smaller than the ESD module.
16. The electrostatic discharge protection circuit of claim 13, wherein,
in the interference detection circuit, the high voltage or the low voltage connected after the sampling module is connected with the detection element in series is the target voltage.
17. The electrostatic discharge protection circuit of claim 13, wherein,
in the interference detection circuit, the high voltage and the low voltage connected after the sampling module and the detection element are connected in series are not related to the target voltage.
18. A battery protection chip, comprising: the electrostatic discharge protection circuit of any one of claims 13-17; the target voltage is the voltage of the overcurrent detection end of the chip.
19. The battery protection chip of claim 18, wherein the battery protection chip comprises a plurality of battery cells,
the functional module is at least one of a charging overcurrent detection module, a discharging overcurrent detection module and a short circuit detection module.
CN202311060871.8A 2023-08-22 2023-08-22 Interference detection circuit, electrostatic discharge protection circuit and battery protection chip Active CN116754884B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202311060871.8A CN116754884B (en) 2023-08-22 2023-08-22 Interference detection circuit, electrostatic discharge protection circuit and battery protection chip
CN202311411929.9A CN117452110A (en) 2023-08-22 2023-08-22 Interference detection circuit and battery protection chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311060871.8A CN116754884B (en) 2023-08-22 2023-08-22 Interference detection circuit, electrostatic discharge protection circuit and battery protection chip

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202311411929.9A Division CN117452110A (en) 2023-08-22 2023-08-22 Interference detection circuit and battery protection chip

Publications (2)

Publication Number Publication Date
CN116754884A true CN116754884A (en) 2023-09-15
CN116754884B CN116754884B (en) 2023-11-10

Family

ID=87955850

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202311060871.8A Active CN116754884B (en) 2023-08-22 2023-08-22 Interference detection circuit, electrostatic discharge protection circuit and battery protection chip
CN202311411929.9A Pending CN117452110A (en) 2023-08-22 2023-08-22 Interference detection circuit and battery protection chip

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202311411929.9A Pending CN117452110A (en) 2023-08-22 2023-08-22 Interference detection circuit and battery protection chip

Country Status (1)

Country Link
CN (2) CN116754884B (en)

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0241653A (en) * 1988-07-22 1990-02-09 American Teleph & Telegr Co <Att> Converter circuit
JP3050240U (en) * 1997-12-26 1998-06-30 鴻文 陳 Electromagnetic radiation measurement device
JPH11326418A (en) * 1998-05-07 1999-11-26 Matsushita Electric Ind Co Ltd Electromagnetic radiation measuring device, and measuring system
CN2482093Y (en) * 2000-12-19 2002-03-13 胜利石油管理局临盘采油厂 Anti-interference indicating lamp for power plant or transformer substation
US20030040278A1 (en) * 2001-08-22 2003-02-27 Iliadis Agisilaos A. System and method for protecting devices from interference signals
CN2671235Y (en) * 2003-10-21 2005-01-12 华为技术有限公司 Protector against electrostatics
CN2671286Y (en) * 2003-11-06 2005-01-12 华为技术有限公司 Diode circuit for protection of ESD
CN101347025A (en) * 2005-10-27 2009-01-14 高通股份有限公司 A method and apparatus for monitoring other channel interference in wireless communication system
US20110121865A1 (en) * 2009-11-25 2011-05-26 Freescale Semiconductor, Inc. Systems and methods for detecting interference in an integrated circuit
CN106483371A (en) * 2016-12-01 2017-03-08 威胜集团有限公司 EMP attack N detection means, detection method and its electric energy meter that makes
US20170131336A1 (en) * 2012-12-28 2017-05-11 Illinois Tool Works Inc. In-tool ESD Events Selective Monitoring Method And Apparatus
CN206594214U (en) * 2016-12-01 2017-10-27 威胜集团有限公司 Transient electric field and electromagnetic field attack detecting circuit and its electric energy meter being made
CN113567716A (en) * 2021-08-04 2021-10-29 珠海格力电器股份有限公司 Detection circuit, detection system and detection equipment
US20220384419A1 (en) * 2021-05-25 2022-12-01 Stmicroelectronics Sa Passive electrostatic-discharge sensor and method for detecting electrostatic discharges
CN115542868A (en) * 2021-06-29 2022-12-30 标致雪铁龙汽车股份有限公司 Method for avoiding electrostatic discharge interference in a vehicle
US20230187436A1 (en) * 2021-07-05 2023-06-15 Changxin Memory Technologies, Inc. Electrostatic protection circuit and chip

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0241653A (en) * 1988-07-22 1990-02-09 American Teleph & Telegr Co <Att> Converter circuit
JP3050240U (en) * 1997-12-26 1998-06-30 鴻文 陳 Electromagnetic radiation measurement device
JPH11326418A (en) * 1998-05-07 1999-11-26 Matsushita Electric Ind Co Ltd Electromagnetic radiation measuring device, and measuring system
CN2482093Y (en) * 2000-12-19 2002-03-13 胜利石油管理局临盘采油厂 Anti-interference indicating lamp for power plant or transformer substation
US20030040278A1 (en) * 2001-08-22 2003-02-27 Iliadis Agisilaos A. System and method for protecting devices from interference signals
CN2671235Y (en) * 2003-10-21 2005-01-12 华为技术有限公司 Protector against electrostatics
CN2671286Y (en) * 2003-11-06 2005-01-12 华为技术有限公司 Diode circuit for protection of ESD
CN101347025A (en) * 2005-10-27 2009-01-14 高通股份有限公司 A method and apparatus for monitoring other channel interference in wireless communication system
US20110121865A1 (en) * 2009-11-25 2011-05-26 Freescale Semiconductor, Inc. Systems and methods for detecting interference in an integrated circuit
US20170131336A1 (en) * 2012-12-28 2017-05-11 Illinois Tool Works Inc. In-tool ESD Events Selective Monitoring Method And Apparatus
CN106483371A (en) * 2016-12-01 2017-03-08 威胜集团有限公司 EMP attack N detection means, detection method and its electric energy meter that makes
CN206594214U (en) * 2016-12-01 2017-10-27 威胜集团有限公司 Transient electric field and electromagnetic field attack detecting circuit and its electric energy meter being made
US20220384419A1 (en) * 2021-05-25 2022-12-01 Stmicroelectronics Sa Passive electrostatic-discharge sensor and method for detecting electrostatic discharges
CN115542868A (en) * 2021-06-29 2022-12-30 标致雪铁龙汽车股份有限公司 Method for avoiding electrostatic discharge interference in a vehicle
US20230187436A1 (en) * 2021-07-05 2023-06-15 Changxin Memory Technologies, Inc. Electrostatic protection circuit and chip
CN113567716A (en) * 2021-08-04 2021-10-29 珠海格力电器股份有限公司 Detection circuit, detection system and detection equipment

Also Published As

Publication number Publication date
CN116754884B (en) 2023-11-10
CN117452110A (en) 2024-01-26

Similar Documents

Publication Publication Date Title
US8238068B2 (en) Electrical over-stress detection circuit
CN101783343B (en) Electro-static discharge protective circuit and integrated circuit
CN109841607A (en) The power clamp for Electrostatic Discharge protection of circuit with control clamper time-out behavior
CN110120660B (en) Overvoltage/energy protection device
CN112186726B (en) ESD protection circuit, power supply and chip
CN101588062A (en) Protection circuit for semiconductor integrated circuit and driving method therefor
CN110912098B (en) Circuit for preventing electrostatic discharge ESD protection from causing leakage current under power-off
US8964341B2 (en) Gate dielectric protection
US20040057172A1 (en) Circuit for protection against electrostatic discharge
US10461529B2 (en) Trigger circuitry for electrostatic discharge (ESD) protection
CN116754884B (en) Interference detection circuit, electrostatic discharge protection circuit and battery protection chip
CN113839374A (en) ESD power protection circuit, working power supply and chip
US8755156B2 (en) Structure of protection of an integrated circuit against electrostatic discharges
US11495955B2 (en) Rectifier triggering techniques
CN219740340U (en) Reset circuit, chip and electronic equipment
SG193090A1 (en) Latch up detection
US10554203B1 (en) Radio frequency detection circuit
US20230017232A1 (en) Electro-static discharge protection circuit and chip
US20050133868A1 (en) [electro-static discharge protection circuit for dual-polarity input/output pad]
US20180115156A1 (en) Semiconductor integrated circuit and semiconductor device including the same
CN106098683A (en) A kind of esd protection circuit
US8879221B2 (en) ESD protection without latch-up
TWI813055B (en) Short circuit protection circuit, electronic device and operation method thereof
CN116896363B (en) NMOS control circuit and battery protection chip
CN217607483U (en) ESD protection circuit, MCU chip and BMS chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant