CN116737642A - SPI (serial peripheral interface) master device, interrupt method and system - Google Patents

SPI (serial peripheral interface) master device, interrupt method and system Download PDF

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Publication number
CN116737642A
CN116737642A CN202310822054.5A CN202310822054A CN116737642A CN 116737642 A CN116737642 A CN 116737642A CN 202310822054 A CN202310822054 A CN 202310822054A CN 116737642 A CN116737642 A CN 116737642A
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spi
master device
spi master
pin
sclk
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黄钧
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Beijing Ziguang Xinneng Technology Co Ltd
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Beijing Ziguang Xinneng Technology Co Ltd
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Priority to CN202310822054.5A priority Critical patent/CN116737642A/en
Publication of CN116737642A publication Critical patent/CN116737642A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)

Abstract

The embodiment of the application discloses SPI master equipment, an interruption method and a system, wherein the SPI master equipment comprises the following steps: the SPI pin comprises an SCLK pin; the SPI master equipment and the corresponding SPI slave equipment are communicated through an SPI bus; an SCLK pin of the SPI master device is connected with an SCLK pin of the SPI slave device; when the SCLK pin of the SPI master device outputs a signal, the SCLK pin is used for setting clock information for the SPI slave device; and the controller is used for determining that the SPI slave device initiates an interrupt request when the SCLK pin of the SPI master device inputs a signal. Multiplexing SCLK pin, sampling signal of SCLK pin to judge whether SPI slave device initiates interrupt request. The SPI master device receives the interrupt signal of the SPI slave device, and the GPIO port is not needed to pass through, so that one GPIO port of the SPI master device can be saved, and the hardware resource of the SPI master device is saved.

Description

SPI (serial peripheral interface) master device, interrupt method and system
Technical Field
The application relates to the technical field of signal interruption, in particular to SPI (serial peripheral interface) master equipment, an interruption method and an interruption system.
Background
Currently, many devices communicate via a serial peripheral interface (SPI, serial Peripheral Interface), such as between a control chip and a touch screen sensor, between a control chip and a temperature sensor, and between a control chip and an analog to digital converter. For example, interrupts include: detecting an interruption of pen down from the touch screen sensor; high temperature alarm interrupt from temperature sensor; an alarm interrupt generated by insufficient electric quantity of the real-time clock chip, a conversion completion interrupt from the analog-to-digital converter, and the like.
In the prior art, an interruption is implemented between an SPI master device and an SPI slave device through a General-purpose input/output (GPIO), and the SPI slave device sends an interruption signal to the GPIO of the SPI master device, commonly called an SPI external interruption.
The SPI slave device triggers a GPIO implementation interrupt which is irrelevant to an SPI module of the SPI master device, and a controller CPU of the SPI master device receives the interrupt and processes the interrupt in a GPIO interrupt processing function. The interrupt implementation requires a GPIO, which occupies a GPIO of the SPI master device, possibly resulting in insufficient GPIO ports.
Disclosure of Invention
In view of this, the embodiments of the present application provide an SPI master device, an interrupt method, and a system, which can save the number of GPIOs without using GPIOs, and are simple and easy to implement.
The embodiment of the application provides SPI master equipment, which comprises the following components: the SPI pin comprises an SCLK pin;
the SPI master equipment and the corresponding SPI slave equipment are communicated through an SPI bus;
an SCLK pin of the SPI master device is connected with an SCLK pin of the SPI slave device;
when the SCLK pin of the SPI master device outputs a signal, the SCLK pin is used for setting clock information for the SPI slave device;
and the controller is used for determining that the SPI slave device initiates an interrupt request when the SCLK pin of the SPI master device inputs a signal.
Preferably, the SPI master device further comprises: a counter;
the counter is used for counting pulses of signals of an SCLK pin of the SPI master device, and informing the controller when judging that the SPI master device receives an interrupt request initiated by the SPI slave device according to a counting result; the counter counts pulses at a frequency higher than the frequency of the clock information.
Preferably, the counter counts pulses at an even multiple of the frequency in the clock information;
the counter is specifically configured to count a high level or a rising edge of a signal of an SCLK pin of the SPI master device to obtain a first value, and count a high level or a rising edge of a signal of an SCLK pin of the SPI master device to obtain a second value; and in the sampling period of pulse counting by the counter, if the first value is not equal to the second value, judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment.
Preferably, the SPI master device further comprises: a counter; the SPI pins comprise chip selection pins;
the counter is used for counting pulses of signals of an SCLK pin of the SPI master device and informing a controller of a counting result;
and the controller judges that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment when the signal of the chip selection pin is invalid and the counting result is received.
Preferably, the SPI master device further comprises: a register;
the register is used for setting IO driving capability, interrupt enabling, notification controller enabling and interrupt marks of SCLK pin of SPI master device.
Preferably, four bits in the register are used to set eight gears of the IO drive capability of the SCLK pin of the SPI master.
Preferably, the SPI slave device is an analog-to-digital converter;
and the controller is also used for reading the analog-to-digital conversion result from the analog-to-digital converter when the analog-to-digital converter is determined to initiate the interrupt request.
The embodiment of the application provides an interruption method of SPI master equipment, which comprises the following steps:
detecting whether an input signal exists on an SCLK pin of the SPI master device;
when an input signal exists on the SCLK pin of the SPI master device, the SPI slave device is determined to initiate an interrupt request.
Preferably, when the SCLK pin of the SPI master device has an input signal, determining that the SPI slave device initiates the interrupt request specifically includes:
pulse counting is carried out on the signal of the SCLK pin of the SPI master device;
judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment according to the counting result; the frequency of the pulse count is higher than the frequency of the clock information of the SPI slave device.
Preferably, the frequency of the pulse count is an even multiple of the frequency of the clock information of the SPI slave device;
when an input signal exists on an SCLK pin of the SPI master device, determining that the SPI slave device initiates an interrupt request specifically comprises:
counting the high level or rising edge of the signal of the SCLK pin of the SPI master device to obtain a first value, and counting the high level or rising edge of the signal of the SCLK pin of the SPI master device to obtain a second value;
and in the sampling period of pulse counting by the counter, if the first value is not equal to the second value, judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment.
Preferably, when the SCLK pin of the SPI master device has an input signal, determining that the SPI slave device initiates the interrupt request specifically includes:
when the signal of the chip selection pin of the SPI master device is invalid and the input signal exists on the SCLK pin of the SPI master device, the SPI master device is judged to receive the interrupt request initiated by the SPI slave device.
The application also provides an SPI system, comprising: SPI slave device and SPI master device introduced above;
the SCLK pin of the SPI slave device initiates an interrupt request to the SCLK pin of the SPI master device.
From this, the embodiment of the application has the following beneficial effects:
when the SPI master device provided by the embodiment of the application receives the interrupt of the SPI slave device, the SPI master device does not need to be realized through a GPIO port alone, but an SCLK pin is multiplexed, and whether the SPI slave device initiates an interrupt request is judged by sampling the signal of the SCLK pin. The SPI master device receives the interrupt signal of the SPI slave device, and the GPIO port is not needed to pass through, so that one GPIO port of the SPI master device can be saved, and the hardware resource of the SPI master device is saved.
Drawings
FIG. 1 is a schematic diagram of an SPI master device and an SPI slave device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an interrupt between an SPI master device and an SPI slave device according to a conventional method;
FIG. 3 is a schematic diagram of another SPI master device provided by an embodiment of the present application;
fig. 4 is a schematic diagram of an SPI slave device as an analog-to-digital converter according to an embodiment of the present application;
fig. 5 is a flowchart of an interruption method of an SPI master device according to an embodiment of the present application.
Detailed Description
In order to facilitate understanding of the technical solution of the embodiments of the present application, technical terms related to the embodiments of the present application will be described first.
SPI is a high-speed, full duplex, synchronous communication bus, and occupies only four wires on the pins of the chip, saving the pins of the chip. SPI works in master-slave mode, typically with one master and one or more slaves, requiring at least 4 wires, MISO (master data in), MOSI (master data out), SCLK (clock) and CS (chip select), respectively.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of embodiments of the application will be rendered by reference to the appended drawings and appended drawings.
Referring to fig. 1, a schematic diagram of an SPI master device and an SPI slave device according to an embodiment of the present application is shown.
The SPI master device 100 provided in the embodiment of the present application includes: a controller (not shown), an SPI pin, and an SCLK pin; the SPI pins include four, MISO, MOSI, SCLK and CS, respectively. Where MISO and MOSI are communication pins. SCLK is the clock pin and CS is the chip select pin.
The SPI master device 100 and the corresponding SPI slave device 200 are communicated through an SPI bus, and communication data is mainly realized through MISO and MOSI pins; MISO is a data input pin and MOSI is a data output pin.
The SCLK pin of SPI master device 100 connects to the SCLK pin of SPI slave device 200; typically, SCLK of SPI master 100 is an output pin, and when the SCLK pin of SPI master 100 outputs a signal, it is used to set clock information, such as clock polarity, operating frequency, rising edge or falling edge sampling, for SPI slave 200, which is configured by SPI master 100 in an initialized manner, and is not changed during operation.
In order to implement the interruption of the SPI master 100 by the SPI slave 200, the SPI slave 200 may pull up or pull down the level of the SCLK pin of the SPI master 100 for a period of time, i.e., the SCLK pin of the SPI master 100 is used as an input pin when interrupted by the SPI slave.
A controller for determining that the SPI slave device 200 initiates an interrupt request when the SCLK pin of the SPI master device 100 inputs a signal. For example, SPI master 100 may sample and count SCLK of SPI master 100 with a higher frequency than the clock frequency of SCLK, calculate the actual width of high and/or low levels, or count rising or falling edges, determine whether SCLK is changing, and an interrupt is generated by SPI slave 200.
For example, the clock frequency of the SPI bus is 75MHz, and the clock frequency of SCLK of the SPI master device 100 is 75MHz and the frequency obtained by dividing 32 is 2.34MHz. When the SPI master 100 interrupts sampling the SCLK, it may sample at a clock frequency of 75MHz, i.e. 16 times the SCLK output signal. The foregoing is merely illustrative, and the embodiment of the present application is not limited to a specific embodiment, as long as the sampling frequency is higher than the clock frequency when SCLK works.
The embodiment of the application is not particularly limited to the types of the SPI master device and the SPI slave device, for example, the SPI slave device is an analog-to-digital converter, and when the analog-to-digital converter finishes converting data, an interrupt request is initiated to the SPI master device, and the SPI master device reads an analog-to-digital conversion result from the analog-to-digital converter. In addition, the SPI slave device may also be various types of sensors, such as a touch screen sensor, a temperature sensor, a power sensor, and the like.
When the SPI master device provided by the embodiment of the application receives the interrupt of the SPI slave device, the SPI master device does not need to be realized through a GPIO port alone, but an SCLK pin is multiplexed, and whether the SPI slave device initiates an interrupt request is judged by sampling the signal of the SCLK pin. The SPI master device receives the interrupt signal of the SPI slave device, and the GPIO port is not needed to pass through, so that one GPIO port of the SPI master device can be saved, and the hardware resource of the SPI master device is saved.
To distinguish the conventional technology, reference may be made to fig. 2, which is a schematic diagram of an interrupt between an SPI master device and an SPI slave device of a conventional type.
One GPIO pin of SPI slave device 200 is connected to one GPIO pin of SPI master device 100, and SPI slave device 200 interrupts SPI master device 100 through the GPIO pin. While SCLK of SPI master 100 serves only as a signal output pin and not as a signal input pin.
The following describes the working principle in detail with reference to the accompanying drawings.
Referring to fig. 3, a schematic diagram of another SPI master device according to an embodiment of the present application is shown.
The SPI master device provided by the embodiment of the application further comprises: a counter 101;
the counter 101 is configured to perform pulse counting on a signal of an SCLK pin of the SPI master device, and notify the controller when the SPI master device determines that the SPI master device receives an interrupt request initiated by the SPI slave device according to a counting result; the frequency at which counter 101 counts pulses is higher than the frequency of the clock information, i.e., the frequency of counter 101 is higher than the operating frequency of SCLK of the SPI master device.
Counter 101 may implement high and low counts, as well as rising and falling edge counts, for SCLK as an input pin. Specifically, counter 101 may pulse count the signal of the SCLK pin with a sampling clock.
The sampling clock is provided by baud rate generator 102 of the SPI master device, and the division factor may be set to control the clock frequency of the SCLK output signal.
When the counter 101 counts, it is possible to realize the counting of the high level by identifying the rising edge and the counting of the low level by identifying the falling edge. For example, the signal low before and high after the signal indicates a rising edge, and the first number N1 of the high level counts starts to count; the high signal and the low signal are indicated as a falling edge, the N1 counting is finished and the low level counting is started at the same time, and the counting is started at a second value N2. The N2 count is ended at the next rising edge, and the cycle is repeated.
For example, in the SPI master device provided in the embodiment of the present application, the frequency of pulse counting performed by the counter is an even multiple of the frequency in the clock information; the present application is exemplified by even-numbered times, odd-numbered times, or even-numbered times for the sake of simplicity of calculation, and is not particularly limited. However, for accurate sampling, the frequency of the counter is generally greater than the clock frequency of the SCLK output signal, and the greater the sampling the more accurate.
The counter is specifically configured to count a high level or a rising edge of a signal of an SCLK pin of the SPI master device to obtain a first value, and count a high level or a rising edge of a signal of an SCLK pin of the SPI master device to obtain a second value; and in the sampling period of pulse counting by the counter, if the first value is not equal to the second value, judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment.
For example, at a sampling frequency of 75MHz, the output signal of SCLK is 2.34MHz, and when there is no interruption in normal condition, the first value N1 and the second value N2 are equal, both being 16.
If either the rising or falling edge is not always taken (level is unchanged), this indicates that the SPI bus is idle and there is no clock signal.
Edge is first taken, but N1 greater than 16 or N2 greater than 16 indicates that SCLK is pulled high or low by the SPI slave device when idle.
It should be appreciated that when the SPI slave interrupts, a signal may be output clamping the SCLK pin of the SPI master, e.g., clamping the SCLK pin of the SPI master for a period of time, e.g., clamping for half a sampling period, which would change the number of N1 or N2. After half a period of clamping, the SPI slave device releases the clamp on the SCLK pin of the SPI master device.
Typically, the signal duty cycle of SCLK is 50%.
If N1 and N2 are always normal, a subsequent occurrence of greater or less than 16 indicates that the SPI bus is pulled high or low by the SPI slave device during normal operation.
If n1=n2=16, N1 and N2 are cleared to zero, and the next sampling period is continued.
The above 16 is merely an example, and an actual product generally has an error, and thus 16 may be relaxed to 17 or 15, etc. I.e. between 17-15 is considered normal, there is no interruption of the SPI from the device.
In addition to counting high and low as described above, a chip select signal may be used to determine whether an interrupt request from the SPI slave device has been received.
The SPI master device provided by the embodiment of the application is characterized in that the SPI pins of the SPI master device comprise chip selection pins.
And the counter is used for counting the pulse of the signal of the SCLK pin of the SPI master device and informing the counting result to the controller.
And the controller judges that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment when the signal of the chip selection pin is invalid and the counting result is received.
If the chip selection pin of the SPI master device is invalid, the SPI master device is idle, SCLK of the SPI master device has no signal output, and if the SLCK pin has signal input, the interrupt request from the SPI slave device is indicated.
In addition, the SPI master device provided by the embodiment of the application further includes: a register 103;
register 103 is used to set the IO drive capability, interrupt enable, notify controller enable, and interrupt flags of the SCLK pin of the SPI master.
For example, four bits in the register are used to set eight gears of the IO drive capability of the SCLK pin of the SPI master.
bit [3:0] is used to set the IO drive capability setting of the SCLK pin. Four bits are set to 8 gears, the minimum driving current is 1mA, and the maximum driving current is 8mA.
bit [4:4] is used to control whether SCLK interrupt input function is enabled, default value 0, not enabled.
bit [5:5] is used for controlling whether to inform CPU after detecting SCLK interrupt, default value 1, send.
And a bit [6:6] interrupt trigger flag for identifying whether SCLK interrupt input exists.
The embodiment of the application does not particularly limit whether the register is newly added or the reserved bit field of the original control register of the SPI main equipment is utilized.
The SCLK interrupt input of the SPI master device provided by the embodiment of the application can be used as an independent interrupt to be sent to the CPU of the SPI master device, and can be combined with other interrupt sources of the SPI master device to be distinguished by adding an interrupt type.
Referring to fig. 4, a schematic diagram of an SPI slave device according to an embodiment of the present application is an analog-to-digital converter.
In the SPI master device 100 provided by the embodiment of the present application, the SPI slave device 200 is an analog-to-digital converter ADC;
and the controller is also used for reading the analog-to-digital conversion result from the analog-to-digital converter when the analog-to-digital converter is determined to initiate the interrupt request.
For example, the RDY pin (Data Ready) of SPI slave 200 connects to the SCLK pin of the SPI master through a resistor.
RDY indicates that the ADC conversion is complete, i.e., the data ready output pin, active low, open drain output.
And when the SPI bus is idle at the beginning, the SCLK is high level, and data is read after the ADC conversion is completed. After the conversion is completed, RDY pulls SCLK of SPI master low, and an interrupt is generated after being recognized by SPI master 100. The SPI master device 100 reads the conversion result of the ADC.
The use of the manual of SPI slave 200 is referred to as properly adjusting the IO drive capability of SCLK or adjusting the resistance of the RDY connection, avoiding that the normal output of the SCLK clock is disturbed by the RDY signal. Although the glitch rarely occurs, after the chip select CS active SPI bus begins to operate, RDY will switch to a high impedance state, SCLK will typically be output after a delay period after the chip select is active.
Based on the foregoing embodiment, an embodiment of the present application is further provided, and the following detailed description is provided with reference to the accompanying drawings.
Referring to fig. 5, the flowchart of an interruption method of an SPI master device according to an embodiment of the present application is shown.
The interrupt method of the SPI master device provided by the embodiment of the application comprises the following steps:
s501: the SCLK pin of the SPI master device is checked for the presence of an input signal.
In general, the SCLK of the SPI master is an output pin, and when the SCLK pin of the SPI master outputs a signal, the SCLK pin is used to set clock information for the SPI slave, for example, clock polarity, operating frequency, rising edge or falling edge sampling, etc., where the above clock information is configured by the SPI master, and is not changed during operation.
S502: when an input signal exists on the SCLK pin of the SPI master device, the SPI slave device is determined to initiate an interrupt request.
According to the interrupt method provided by the embodiment of the application, when receiving the interrupt of the SPI slave device, the interrupt is not needed to be realized through a GPIO port alone, an SCLK pin is multiplexed, and whether the SPI slave device initiates an interrupt request is judged by sampling the signal of the SCLK pin. The SPI master device receives the interrupt signal of the SPI slave device, and the GPIO port is not needed to pass through, so that one GPIO port of the SPI master device can be saved, and the hardware resource of the SPI master device is saved.
When an input signal exists on an SCLK pin of the SPI master device, determining that the SPI slave device initiates an interrupt request specifically comprises:
pulse counting is carried out on the signal of the SCLK pin of the SPI master device;
judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment according to the counting result; the frequency of the pulse count is higher than the frequency of the clock information of the SPI slave device.
The frequency of pulse counting is even times of the frequency of clock information of the SPI slave device;
when an input signal exists on an SCLK pin of the SPI master device, determining that the SPI slave device initiates an interrupt request specifically comprises:
counting the high level or rising edge of the signal of the SCLK pin of the SPI master device to obtain a first value, and counting the high level or rising edge of the signal of the SCLK pin of the SPI master device to obtain a second value;
and in the sampling period of pulse counting by the counter, if the first value is not equal to the second value, judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment.
When an input signal exists on an SCLK pin of the SPI master device, determining that the SPI slave device initiates an interrupt request specifically comprises:
when the signal of the chip selection pin of the SPI master device is invalid and the input signal exists on the SCLK pin of the SPI master device, judging that the SPI master device receives an interrupt request initiated by the SPI slave device
The embodiment of the application also provides an SPI system, which comprises the SPI master device and the SPI slave device, wherein an interrupt request is initiated to the SCLK pin of the SPI master device by the SCLK pin of the SPI slave device.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (12)

1. An SPI master device comprising: the SPI pin comprises an SCLK pin;
the SPI master equipment and the corresponding SPI slave equipment are communicated through an SPI bus;
the SCLK pin of the SPI master device is connected with the SCLK pin of the SPI slave device;
when the SCLK pin of the SPI master device outputs a signal, the SCLK pin is used for setting clock information for the SPI slave device;
and the controller is used for determining that the SPI slave equipment initiates an interrupt request when an SCLK pin of the SPI master equipment inputs a signal.
2. The SPI master device according to claim 1, further comprising: a counter;
the counter is used for counting pulses of signals of an SCLK pin of the SPI master device, and notifying the controller when judging that the SPI master device receives an interrupt request initiated by the SPI slave device according to a counting result; the counter counts pulses at a frequency higher than the frequency of the clock information.
3. The SPI master device according to claim 2, wherein the counter counts pulses at an even multiple of the frequency in the clock information;
the counter is specifically configured to count a high level or a rising edge of a signal of the SCLK pin of the SPI master device to obtain a first value, and count a high level or a rising edge of a signal of the SCLK pin of the SPI master device to obtain a second value; and in the sampling period of pulse counting by the counter, if the first value is not equal to the second value, judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment.
4. The SPI master device according to claim 1, further comprising: a counter; the SPI pins comprise chip selection pins;
the counter is used for counting pulses of signals of an SCLK pin of the SPI master device and informing the counting result to the controller;
and the controller judges that the SPI master equipment receives the interrupt request initiated by the SPI slave equipment when the signal of the chip selection pin is invalid and the counting result is received.
5. The SPI master device according to any one of claims 1-4, further comprising: a register;
the register is used for setting IO driving capability, interrupt enabling, notification controller enabling and interrupt marks of an SCLK pin of the SPI master device.
6. The SPI master device according to claim 5, wherein four bits in the register are used to set eight gears of the IO drive capability of the SCLK pin of the SPI master device.
7. An SPI master device according to any one of claims 1-4, wherein the SPI slave device is an analog to digital converter;
the controller is further configured to read an analog-to-digital conversion result from the analog-to-digital converter when it is determined that the analog-to-digital converter initiates an interrupt request.
8. An interruption method of an SPI master device, comprising:
detecting whether an input signal exists on an SCLK pin of the SPI master device;
and when an input signal exists on an SCLK pin of the SPI master device, determining that the SPI slave device initiates an interrupt request.
9. The method according to claim 8, wherein the determining that the SPI slave device initiates the interrupt request when the SCLK pin of the SPI master device has an input signal, specifically comprises:
pulse counting is carried out on signals of SCLK pins of the SPI master device;
judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment according to a counting result; the frequency of the pulse count is higher than the frequency of the clock information of the SPI slave device.
10. The method of claim 9, wherein the pulse count has a frequency that is an even multiple of a frequency of clock information of the SPI slave device;
when an input signal exists on an SCLK pin of the SPI master device, determining that the SPI slave device initiates an interrupt request specifically comprises:
counting the high level or rising edge of the signal of the SCLK pin of the SPI master device to obtain a first value, and counting the high level or rising edge of the signal of the SCLK pin of the SPI master device to obtain a second value;
and in the sampling period of pulse counting by the counter, if the first value is not equal to the second value, judging that the SPI master equipment receives an interrupt request initiated by the SPI slave equipment.
11. The method according to claim 9, wherein the determining that the SPI slave device initiates the interrupt request when the SCLK pin of the SPI master device has an input signal, specifically comprises:
and when the signal of the chip selection pin of the SPI master device is invalid and the input signal exists on the SCLK pin of the SPI master device, judging that the SPI master device receives the interrupt request initiated by the SPI slave device.
12. An SPI system, comprising: an SPI slave device and an SPI master device according to any of claims 1-7;
and the SCLK pin of the SPI slave device initiates an interrupt request to the SCLK pin of the SPI master device.
CN202310822054.5A 2023-07-05 2023-07-05 SPI (serial peripheral interface) master device, interrupt method and system Pending CN116737642A (en)

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* Cited by examiner, † Cited by third party
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CN117076373A (en) * 2023-10-16 2023-11-17 北京紫光芯能科技有限公司 Communication method, SPI controller and singlechip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117076373A (en) * 2023-10-16 2023-11-17 北京紫光芯能科技有限公司 Communication method, SPI controller and singlechip
CN117076373B (en) * 2023-10-16 2024-02-27 北京紫光芯能科技有限公司 Communication method, SPI controller and singlechip

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