GB2376856A

GB2376856A - Signal processing system that adds stuff bits to make variable length data stream into integer multiple of byte length

Info

Publication number: GB2376856A
Application number: GB0115226A
Authority: GB
Inventors: Peter Loef; Gregor Swinkels
Original assignee: Omron Europe BV
Current assignee: Omron Europe BV
Priority date: 2001-06-21
Filing date: 2001-06-21
Publication date: 2002-12-24
Anticipated expiration: 2021-06-21
Also published as: GB2376856B; GB0115226D0

Abstract

There is disclosed a signal processing system and a method which allows a device 10 operating on the basis of synchronous communication to communicate with a processor 11. A problem with such systems is that the processor 11 operates in bits of a fixed length (e.g. 8 bits), but signals from the device 10 may be of variable bits length. This problem is solved by adding additional bits to signals from the device 10, so as to make them an integer multiple of a predetermined byte length. The processor 11 is arranged to generate an output signal of variable bit length, the device 10 is arranged to receive the output signal and generate a data signal of a length determined by the output signal, and the processor 11 is arranged to receive the data signal, add thereto one or more additional bits to form a processing signal which is an integer multiple of a predetermined byte length, to divide the processing signal into one or more sub-signals of said predetermined bit length, and to process each of said sub-signals.

Description

SIGNAL PROCESSING SYSTEM The present invention relates to a signal processing system, in which communication via a synchronous serial interface (hereinafter SSI) is controlled from a microprocessor. It is particularly, but not exclusively, concerned where such communication is to a position encoder.

In conventional SSI communication arrangements, there are two control components between the processor and the encoder, which operates via an SSI. The first component, which the encoder communicates directly, is a component for adjusting signal levels to those appropriate for the microprocessor. The second component is a control component. The reason for this component is that the microprocessor necessarily operates in bytes of a fixed length, such as 8 bits, but the signals from the encoder may be of variable bit length. Moreover, although the timing of the microprocessor is carried out on a byte level, the encoder operates with timing on a bit level. Thus, the control component must ensure not only appropriate signal length, but also appropriate timing of the signals. Thus, in the known systems the control component is needed to provide satisfactory communication.

The present invention seeks to modify such an arrangement, to simplify it, and at its most general provides that additional bits are added to the signals from the encoder, to make them an integer multiple of a predetermined byte length.

Therefore according to a first aspect of the invention there may be provided a signal processing system comprising a processor arranged to generate an output signal of variable bit length; a device operating on the basis of synchronous communication arranged to receive the output signal and to generate a data signal of a length determined by the output signal; wherein the processor is arranged to receive the data signal, add thereto one or more additional bits to form a processing signal which is an integer multiple of a predetermined byte length, to divide the processing signal in to one or more sub-signals of said predetermined byte length, and to process each of said sub-signals.

Preferably, this achieved by providing an OR gate external to the microprocessor which receives a pulse input corresponding to the number of bits in signal from the encoder and a second input from the microprocessor which corresponds to the number of bits to be added to that signal to make it a multiple of the byte length.

Thus, the signals from the OR gate are in multiples of

the byte length, and those signals can then be handled by the microprocessor without requiring a separate control component.

The length of the signals from the encoder is normally determined by the microprocessor itself, by combining e. g. in an AND gate a clock signal and an enable signal. The resulting pulse train is passed through the encoder to trigger the transmission of an appropriate number of bits of data from the encoder to the microprocessor.

In a second aspect of the invention there may be provided a signal processing method comprising: generating an output signal of variable bit length; receiving the output signal at a device operating on the basis of synchronous communication and generating a data signal of a length determined by the output signal; receiving the data signal; adding to said data signed one or more additional bits to form a processing signal which is an integer multiple of a predetermined byte length; dividing the processing signal in to one or more sub-signals of said predetermined byte length; and processing each of said sub-signals.

An embodiment of the present invention will now be described in detail, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 is a schematic block diagram of a system incorporating the present invention; Fig. 2 is a schematic diagram showing part of the system of Fig. 1 in more detail; Fig. 3 is a diagram showing the cycle of operation of the microprocessor.

Referring first to Fig. 1, SSI equipment such as an encoder is connected to a microprocessor 11 by a signal shift circuit 12, which adjusts the signals from the microprocessor to the voltage levels required for the encoder 10, and vice versa. Fig. 1 also shows that an AND gate 14 and an OR gate 15 are connected to the microprocessor.

Referring now to Fig. 2, the AND gate 14 provides a pulse train of clock signals to the encoder 10. The microprocessor has two timer pulse units (TPU) 20,21.

The former generates a high frequency clock signal which is passed to the AND gate 14. The latter generates a signal which acts as an enable signal for the clock output, to determine the pulse train duration. Its output is also passed to the AND gate 14. Thus, before sending a pulse train, the TPU 21 has no output, and therefore the AND gate 14 has no output. When the TPU 21 is set to on, then the output of the AND gate 14 corresponds to the pulses from the TPU 20. The pulse

train terminates when the output of the TPU 21 is set to off.

The pulse train from the AND gate 14 passes to a line driver conversion circuit 22, being passed to the signal shift circuit 12. In practical embodiments, the line driven conversion circuit 22 may be physically part of the shift circuit 12. The line driver circuit 22 converts signals to transistor-transistor logic signals (TTL) and acts as isolation. The line driver circuit 22 also inverts the polarities of the pulses, because the clock of the encoder 10 must be high when inactive. The line driver circuit 22 may be achieved by standard RS485/422 receiver/transmitter components which are applied in communications with devices over longer distances. Line driver circuit 22 is a line-driver transmitter.

When the pulse train reaches the encoder 10, the rising edge of each clock signal generates an appropriate data signal which is passed from the encoder 10 to a second line driver circuit 23, which carries out the reverse operation of the line driver circuit 22. Again, the line driver circuit 23 may be physically part of the shift circuit 12 produced from similar components and is a line-driver receiver. The data pulses are then received at a serial communications interface 24 of the microprocessor 11. The interface 21 is in the form of a

universal asynchronous receiver transmitter (UART) such devices are known hardware structures used for serial communications. However, for simplicity, the subsequent description will refer to that interface as a SCI 24.

The SCI 24 can only receive bytes in synchronous mode, i. e. must receive a pulse train being a multiple of the byte length. However, the data signal from the encoder 10 is of variable length. Therefore, it is necessary to generate additional pulses. To do this, the microprocessor generates an output 25 to the OR gate 15 and it also receives the pulse train from the AND gate 14. Thus, the OR gate inputs via an input 26 to the SCI 24 a pulse train length corresponding to a integer multiple of the byte length. Thus, the SCI 24 can process the signal satisfactorily.

On reception of each byte, the SCI can transfer signals to a direct memory access controller (DMA) 27 and hence to a RAM 28. The DMA 27 transfers data from a received buffer to an incremental buffer in the RAM 28.

Instead of generating an interrupt at each byte, a byte by byte transfer is repeated until all bytes from the SCI 24 have been received.

In the embodiment illustrated in Fig. 2, the byte length is 8 bits. Other byte lengths are possible within the present invention.

The microprocessor determines the number of extra pulses needed to be produced from the OR gate 15 on the basis of the length of the pulse train generated by the AND gate 14, from the TPUs 20 and 21, and having an appropriate number of bits.

The sequence of operations carried out by the processor 11 is illustrated in Fig. 3. As can be seen, there are five possible states referred to as the Init state 30, the Idle state 31, the Busy state 32, the Delay state 33, and the Waiting state 34. These will now be described in more detail.

Init state 30 In this state, the software and the MPU and its peripherals are prepared. This means the following : determine the amount of pulses to be sent to the SSI clock output determine the amount of extra pulses to be sent to the SCI's clock input determine the amount of bytes to be received by the SCI configure the DMA controller (mode, number of bytes etc.) configure the SCI (synchronous communication, most significant bit first etc.) prepare timers used for realising delays and for monitoring time-outs

start the state machine software in the Idle state Idle state 31 waiting for a signal requesting a new SSI communication cycle. On this request, the software will do the following: the so-called extra pulses are sent to the SCI's clock the two timer-pulse units are configured to generate the signals required and triggered to start simultaneously Busy state 32 The SSI communication is being executed by the MPU and its peripherals. The software is not involved. When all data is received, an interrupt is requested by the DMA controller. This event triggers the transition to the delay state.

Delay state 33 According to the SSI protocol, a delay is required to safely detect the state of the SSI equipment.

An MPU timer is used to realise the delay, after which a transition is made to the Waiting state.

Waiting state 34 In this state, the data output of the SSI equipment is monitored to tell whether the connected equipment is ready for a next communications cycle.

When the equipment does not signal that it has gone into this ready state within a specified time, an exception is raised because the equipment is not behaving according to the SSI protocol. If the SSI equipment signalled within the specified time that it is ready, a transition is made to the Idle state.

Claims

CLAIMS: 1. A signal processing system comprising; a processor arranged to generate an output signal of variable bit length; a device operating on the basis of synchronous communication arranged to receive the output signal and to generate a data signal of a length determined by the output signal; wherein the processor is arranged to receive the data signal, add thereto one or more additional bits to form a processing signal which is an integer multiple of a predetermined byte length, to divide the processing signal in to one or more sub-signals of said predetermined byte length, and to process each of said sub signals.
2. A system according to claim 1, wherein the processor has an OR gate arranged to receive said data signal and to receive said additional bits, thereby to generate said processing signal.
3. A system according to claim 1 or claim 2, wherein the processor further includes an AND circuit for generating said output signal, the AND circuit being arranged to receive a clock signal and a gating signal,

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the gating signal determining the bit length of the output signal.
4. A system according to any one of the preceding claims, wherein said device is a position encoder.
5. A signal processing method comprising: generating an output signal of variable bit length; receiving the output signal at a device operating on the basis of synchronous communication and generating a data signal of a length determined by the output signal; receiving the data signal; adding to said data signed one or more additional bits to form a processing signal which is an integer multiple of a predetermined byte length; dividing the processing signal in to one or more sub-signals of said predetermined byte length, and processing each of said sub-signals.