CN116736933A - Photon computing array for on-chip large-scale matrix multiplication - Google Patents
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- G02B6/29331—Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means operating by evanescent wave coupling
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Abstract
The invention discloses a photon computing array for on-chip large-scale matrix multiplication operation, which comprises the following components: photon calculation unit based on carrier light absorption effect, cross switch matrix architecture and waveguide coupling device; the photon calculating unit comprises an optical waveguide and an electro-optic modulator; the optical waveguide of each of the photonic computing units is coupled with an adjacent waveguide by the waveguide coupling device that evanescently couples a portion of the optical power from the adjacent input row waveguide, wherein the coupled optical power depends on the length of the portion of the waveguide coupling device that is positioned adjacent to and extends parallel to the adjacent input row waveguide. The photon computing array provided by the invention is a novel photon computing chip technical path, the volume of basic computing units is small, the modulation speed is high, each basic computing unit only has two electrodes, the wiring quantity is small, and the design difficulty and the packaging complexity are low.
Description
Technical Field
The invention relates to the technical field of photon calculation, in particular to a photon calculation array for on-chip large-scale matrix multiplication operation.
Background
As human society enters a big data age, the demands for ultra-fast data processing are increasing for computing power and speed of computer systems. As moore's law approaches physical limits, electronic chips encounter significant challenges in terms of computational speed and power consumption. Traditional matrix operation, for example, chinese patent CN111158636 discloses that a computer is required to store and read the intermediate quantity of the calculated data multiple times, and as the matrix scale is enlarged, the calculation time is also multiplied, and an operation method capable of efficiently implementing large-scale matrix operation is sought.
The photon calculation structure has the characteristics of high speed, parallelism and the like, has outstanding advantages in processing linear calculation, and becomes a hot spot of current international research. The photon calculation chip is built by adopting novel optical materials such as an optical waveguide micro-nano structure, a micro-lens array and the like, and is applied to different scenes.
The photonic computing chip with the networking of the photonic devices is constructed by taking the optical devices as basic units, photons with high speed and low power consumption can be used as carriers of information, and the photonic computing chip is considered as a scheme with the most promising future high-speed, ultra-large-scale, large-data-volume, artificial intelligent computing and brain-like computing, and is expected to promote a new industrial revolution. The silicon-based photoelectronic technology utilizes the unique advantages of photons in terms of speed, bandwidth and interference resistance, has an integrated process compatible with a CMOS process, can break through the development dilemma of an integrated circuit, and further improves the operation capability of a chip. Unlike binary electronic computing systems consisting of 0 and 1, photons have more controllable modulation and multiplexing dimensions, such as phase, wavelength, polarization, mode, etc., and have unique advantages in analog computation and multibit computation, and are very suitable for a large number of parallel computation, which is one of the important directions of the development of integrated circuits in the late-molar age.
The existing photon calculation chip technology path is as follows: photon calculations are implemented by using a mach-zehnder interferometer (MZI) or a micro-ring structure (MMR), and the calculation modes are disclosed in, for example, chinese patents CN115905792 and CN113392965, and the calculation arrays formed based on these techniques are disclosed in, for example, chinese patents CN10407644 and CN116107037, but these techniques generally have the following disadvantages:
1. calculating array size limits: the photon calculation chip based on the MZI has larger area of a basic calculation unit, and when a silicon optical platform flows, a mask plate under the area of a conventional wafer is difficult to realize the application level of the calculation array scale.
2. The calculation speed is slow: the method mainly utilizes a thermo-optical tuning principle based on a silicon-based photoelectron technology, and simultaneously has the phenomenon of temperature drift (MMR structure is particularly remarkable) to influence the refractive index of the optical waveguide.
3. Design & encapsulation degree of difficulty is high: the photon calculation chip based on the MZI has more than 10 electrodes per basic calculation unit, the wiring quantity is extremely large, and the design difficulty and the packaging complexity are high.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a photon calculation array for on-chip large-scale matrix multiplication operation.
The aim of the invention is achieved by the following technical scheme:
a photonic computing array for on-chip large-scale matrix multiplication operations, comprising:
a photon calculation unit based on a carrier light absorption effect; the photon calculating unit comprises an optical waveguide and an electro-optic modulator based on light absorption effect, wherein the electro-optic modulator is positioned on the optical waveguide; the electro-optical modulator uses an electric signal as external excitation, and changes the absorption coefficient alpha of the optical waveguide containing free carriers to light by injecting current or applying voltage in the doped region so as to change the concentration of the free carriers (charges or holes), so that the optical signal passing through the optical waveguide is absorbed by the free carriers to realize multiplication operation;
crossbar matrix architecture (Crossbar); the cross switch matrix architecture is formed by crossing a group of input row waveguides which are parallel to each other and a group of output column waveguides which are parallel to each other;
the photonic computing units for multiplication are present at the intersection of each input row waveguide and output column waveguide in the photonic computing array, the optical waveguide of each photonic computing unit being coupled to an adjacent waveguide by a waveguide coupling device which evanescently couples a portion of the optical power from an adjacent input row waveguide, wherein the coupled optical power depends on the length of the portion of the waveguide coupling device which is positioned adjacent to and extends parallel to the adjacent input row waveguide.
Preferably, each of the input row waveguides and the output column waveguides intersecting with the input row waveguide is provided with an intersecting optical waveguide at an intersection point.
Preferably, the input row waveguide is perpendicular to the output column waveguide.
Preferably, the wavelengths of the light of the input optical signals of the input row waveguides of the different rows are different.
Preferably, the input optical signal is used for evenly distributing the optical power of the input optical signal to each photon computing unit on the same row under the action of the waveguide coupling device.
Preferably, the number of rows of the input row waveguides and the number of columns of the output column waveguides of the photon computing array are at least equal to or greater than 2.
Preferably, the size of the photon counting unit is less than 100 μm.
Preferably, the voltage amplitude of the electrical signal as external stimulus is less than 10V for a duration of less than 100 μs.
Preferably, the optical waveguide and the electro-optical modulator may or may not be in the same plane.
Preferably, the input end of the input row waveguide of the photon computing array is connected with a Multiplexer (MUX), and the output end of the output column waveguide is connected with a Demultiplexer (DEMUX).
The beneficial effects of the invention are mainly as follows: the novel photon calculation array for on-chip large-scale matrix multiplication is provided, is a novel photon calculation chip technology path, has smaller basic calculation unit area, and can be applied to the scale of the calculation array by a mask plate under the conventional wafer area;
the modulation speed is high, the modulation speed can be increased to nanosecond level through electric pulse, so that the calculation performance of the photon calculation chip is improved, and meanwhile, the phenomenon of temperature drift is avoided;
each basic computing unit only has 2 electrodes, the wiring quantity is small, and the design difficulty and the packaging complexity are low.
Drawings
The technical scheme of the invention is further described below with reference to the accompanying drawings:
fig. 1: schematic of the photon computing array of the present invention;
fig. 2: an extended application schematic of the photon computing array of the present invention;
fig. 3: a schematic diagram of an embodiment 3*3 photon computing array of the invention;
fig. 4: an extended application schematic of an embodiment 3*3 photon compute array of the invention;
fig. 5: the embodiment of the invention provides a structural schematic diagram of a photon calculation unit.
Fig. 6: the working principle schematic diagram of the photon calculation unit multiplication calculation provided by the embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. The embodiments are not limited to the present invention, and structural, methodological, or functional modifications of the invention from those skilled in the art are included within the scope of the invention.
The invention will be described in detail below with reference to the drawings in connection with embodiments.
As shown in fig. 1, the invention discloses a photon computing array for on-chip large-scale matrix multiplication operation, which comprises a photon computing unit 1 based on carrier light absorption effect, a waveguide coupling device 2 and a Crossbar matrix architecture (Crossbar). Specifically, the crossbar architecture is formed by intersecting a set of input row waveguides 31 and a set of output column waveguides 32 that are parallel to each other; preferably, the input row waveguide 31 is perpendicular to the output column waveguide 32.
The number of rows of the input row waveguides 31 and the number of columns of the output column waveguides 32 of the photonic computing array in the present invention are at least 2 or more. Preferably, each intersection of the input row waveguide 31 and the output column waveguide 32 intersecting with the input row waveguide is provided with an intersecting optical waveguide 4, so as to realize low-loss transmission of optical signals when the waveguides intersect.
There is one photon calculation unit 1 for multiplication at the intersection of each input row waveguide 31 and output column waveguide 32 in the photon calculation array. The photon computing unit 1 comprises an optical waveguide 11 and an electro-optical modulator 12 based on light absorption effects located on the optical waveguide 11; the electro-optical modulator 12 changes the absorption coefficient α of the optical waveguide 11 containing free carriers to the optical signal by injecting a current or applying a voltage to change the concentration of its free carriers (charges or holes) in its doped region using an electric signal as an external stimulus, so that the optical signal passing through the optical waveguide 11 is absorbed by the free carriers, thereby realizing a multiplication operation. The injection current or the applied voltage is mainly in the form of electric pulse, the duration of the electric pulse is in nanosecond level, and meanwhile, the duration of the electric pulse determines the modulation speed of the photon calculation array, so that the calculation performance of the photon calculation array is determined; and meanwhile, the phenomenon of temperature drift is avoided.
The photon calculation array of the invention completes multiplication operation as shown in fig. 5 and 6, and comprises the following steps:
encoding the multiplier value into write signal 108;
mapping the multiplier value to a state of the electro-optic modulator 12 using the write signal 108, the state exhibiting an absorption coefficient α of the optical waveguide for light at different free carrier concentrations;
encoding the multiplicand value into the input optical signal 106;
as the input optical signal 106 passes through the optical absorption region of the electro-optical modulator 12 via said optical waveguide 11, an output signal 107 is generated, wherein the product of the multiplier value and the multiplicand value is encoded in the optical power of the output signal.
Wherein a write signal 108 for changing the concentration of free carriers in the electro-optical modulator 12 is provided by the electrical signal generator 105. The two electrical interconnection devices in the metal layer of the electrical signal generator 105 transmit the generated electrical signal to the doped regions 103a, 103b of the electro-optical modulator 12 via the first contact electrode 104a, the second contact electrode 104b, respectively. The electric signal causes the free carriers to directionally move under the action of the electric field, and the change of parameters of the electric signal can change the concentration of the free carriers in the doped region, so that the absorption coefficient of the optical waveguide containing the free carriers to light is changed. The electro-optical modulator based on the light absorption effect comprises a doped region based on semiconductor doping technology such as ion implantation or high-temperature diffusion and a pair of contact electrodes which form ohmic contact or Schottky contact with the doped region.
The electrical signal generator 105 uses an external electrical signal, i.e. the write signal 108 to map the multiplier value b to the absorption coefficient of light α of the optical waveguide containing free carriers, and the electro-optic modulator 12 injects a current or applies a voltage to change the free carrier concentration (charge or hole) in the doped region, changing the absorption coefficient of light α of the optical waveguide containing free carriers. The energy Pwrite of the external electrical signal has a mapping in the form of a elementary or rational function with the absorption coefficient α of the light, the input optical signal 106 decays inversely proportional to the absorption coefficient α of the light with the optical waveguide containing free carriers, resulting in a multiplication output signal 107 corresponding to the external electrical signal, write signal 108 and input optical signal 106, the output signal pout=α×pin of the optical waveguide 11 being the result of mapping the multiplier value b to α and the multiplicand value a to Pin.
The size of the photon calculation unit of the present invention is less than 100 μm, and preferably, the size of the photon calculation unit is 20 to 30 μm. At present, the size of the photon calculating unit based on the MZI structure is 200-300 mu m, but the size of the photon calculating unit provided by the embodiment is obviously smaller than that of the photon calculating unit, so that the miniaturization and the high integration of the photon calculating unit are realized. With the reduction of the size of a single photon calculation unit, the actual area of each device on a chip is reduced, and when a silicon optical platform flows, an optical mask plate under the area of a conventional wafer (for example, an 8-inch wafer) can support a larger number of photon calculation units to form a photon calculation array with a larger-scale matrix, so that the integration level of the photon calculation chip is improved.
The size of the existing photon calculation array based on the MZI is larger, when a silicon optical platform flows, a mask plate under the area of a conventional wafer (such as an 8-inch wafer) cannot support the 128 x 128 matrix-scale photon calculation array, and the 128 x 128 matrix-scale photon calculation array is a threshold for commercial application.
In this embodiment, the voltage amplitude of the electrical signal is less than 10V and the duration is less than 100 μs. In some preferred embodiments, the electrical signal has a voltage amplitude of less than 5V and a duration of less than 100ns. At present, the modulation speed of the MZI photon calculation unit based on thermo-optical modulation is in the microsecond magnitude, but the electro-optical modulator provided by the embodiment can reach below 100ns and even below 10ns by utilizing the doped semiconductor device, so that the calculation speed of the photon calculation unit is greatly improved. The amplitude of the electric signal is preferably less than 5V, so that the electric signal can be well compatible with the level of the existing electric chip, additional circuit design is not needed, and the electric chip can be directly used for transmitting pulses to modulate the optical signal in the optical computing unit.
In terms of modulator, each calculation unit of the photon calculation array based on the MZI comprises more than 10 electrodes, and the novel photon calculation array for on-chip large-scale matrix multiplication operation provided by the invention has only 2 electrodes, and the difficulty of analysis from the aspects of design and packaging is far smaller than that of the photon calculation array based on the MZI.
In a preferred embodiment of the present invention, the optical waveguide 11 of each of the photon computing units 1 is coupled with an adjacent waveguide through the waveguide coupling device 2, for example: one end of the optical waveguide 11 is coupled to an adjacent input row waveguide 31 through a row waveguide coupling device 21, and the other end is coupled to an adjacent output column waveguide 32 through a column waveguide coupling device 22. The waveguide coupling device 2 evanescently couples a portion of the optical power from the adjacent input row waveguide 31, wherein the coupled optical power depends on the length of the portion of the waveguide coupling device 2 that is positioned adjacent to the input row waveguide 31 and extends parallel to the adjacent input row waveguide 31.
The invention is characterized in that a waveguide coupling device and a Crossbar architecture are adopted to interconnect photon calculation units of single multiplication operation to form a Crossbar architecture so as to realize large-scale matrix multiplication operation. Namely: after each photon calculation unit performs multiplication as described above, the output signal with product is summed over the output column waveguide 32 by the column waveguide coupling device 22, which encodes the sum value to the input signal of the output column waveguide, the column waveguide coupling device ensures that the common factor of the optical power at each wavelength is the same, and the output signal of the input row waveguide and the input signal of the output column waveguide are coupled to generate an output signal, wherein the sum of the product and the sum value is encoded in the optical power of the output signal of the output column waveguide. Of course, the order of the input row waveguide and the output column waveguide is not fixed, and the multiplication operation can be performed by inputting the optical signal through the column waveguide, and the accumulation operation can be performed through the row waveguide and then the output is performed.
The invention realizes low-loss transmission of optical signals between rows and columns of a large-scale matrix through the cross switch matrix architecture, and finally realizes large-scale matrix multiplication operation. In a preferred embodiment, the wavelengths of the light of the input optical signals of the input row waveguides 31 of different rows are different, so that interference phenomenon generated by the light during addition operation is avoided, and the accuracy of photon calculation is affected.
As shown in fig. 1 in particular, the present invention provides a method for performing matrix multiplication in an optical domain, which implements calculation of m×n-order matrices p×u=a:
the method specifically comprises the following steps:
(1) Encoding the weight matrix U into the write signal, for example, inputting the code U11 into the first row and first column of photon calculation units, inputting the code U12 into the first row and second column of photon calculation units, inputting the code U21 into the second row and first column of photon calculation units, and so on;
(2) Mapping the multiplier value to a state of the electro-optic modulator in each photon calculation unit using a write signal, the state representing an absorption coefficient α of the optical waveguide for light;
(3) Encoding the input data matrix P into an input optical signal whose optical power is equally distributed to each of the cells on the same row by the row waveguide coupling device 21; for example, the code P1 is input into the input row waveguide of the first row, the code P2 is input into the input row waveguide of the second row, and so on;
(4) When an input optical signal passes through an optical waveguide and passes through an optical absorption region of an electro-optical modulator of a photon calculation unit, an output signal is generated, wherein the product of a multiplier value and a multiplicand value is encoded in the output signal, the optical power of the output signal is summed on a column waveguide through a column waveguide coupling device 22, and the column waveguide coupling device can make the common factor of the optical power at each wavelength the same;
for example: the output optical power of the first column is:
the common factor in the above formula is 1 +. m * n . And so on.
An extended application of the photon compute array of the present invention is shown in fig. 2. A multiplexer MUX is connected to the input of the input row waveguide 31 of the photonic computing array and a demultiplexer DEMUX is connected to the output of the output column waveguide 32. Each component of the input matrix uses a plurality of optical signals of different wavelengths, and the number of channels of the multiplexer determines the improvement multiple of the computational power of the photon computing array.
Fig. 3 discloses a schematic diagram of an embodiment 3*3 photon computing array, implementing a computing third order matrix P x u=a,
wherein:
101a, 101b, 101c: an input row waveguide;
102a, 102b, 102c: an output column waveguide;
p1, P2, P3: inputting (reading) an optical signal;
a1, A2, A3: outputting a signal;
u11, U12, U13, U21, U22, U23, U31, U32, U33: a photon calculation unit for multiplication;
r11, r12, r13, r21, r22, r23, r31, r32, r33: a row waveguide coupling device;
c11, c12, c13, c21, c22, c23, c31, c32, c33: a column waveguide coupling device;
the method according to the invention can be implemented to calculate the optical power output of the first column as:
the common factor in the above formula is 1/9.
Similarly, FIG. 4 shows an extended application of the photon compute array of the embodiment of FIG. 3. A Multiplexer (MUX) is added at the input of the photon computing array and a Demultiplexer (DEMUX) is added at the output, each component of the input matrix using 3 different wavelengths, increasing the computing power of the photon computing array by a factor of 3.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A photonic computing array for on-chip large-scale matrix multiplication, characterized by: comprising
A photon calculation unit (1) based on a carrier light absorption effect; the photon computing unit (1) comprises an optical waveguide (11) and an electro-optical modulator (12) based on light absorption effect on the optical waveguide (11); the electro-optical modulator (12) uses an electric signal as external excitation, and changes the absorption coefficient alpha of the optical waveguide (11) containing free carriers to light by injecting current or applying voltage in the doped region so as to change the concentration of the free carriers, so that the optical signal passing through the optical waveguide (11) is absorbed by the free carriers to realize multiplication;
a crossbar matrix architecture; the crossbar architecture is formed by intersecting a set of mutually parallel input row waveguides (31) and a set of mutually parallel output column waveguides (32);
the photon computing unit (1) for multiplication is arranged at the intersection point of each input row waveguide (31) and each output column waveguide (32) in the photon computing array,
the optical waveguide (11) of each of the photon computing units (1) is coupled with an adjacent waveguide by a waveguide coupling device (2), the waveguide coupling device (2) evanescently coupling a portion of the optical power from an adjacent input row waveguide (31), wherein the coupled optical power depends on the length of the portion of the waveguide coupling device (2) placed as an adjacent input row waveguide (31) and extending parallel to the adjacent input row waveguide (31).
2. The photonic computing array of claim 1, wherein: an intersecting optical waveguide (4) is provided at the intersection of each of the input row waveguides (31) and the output column waveguides (32) intersecting therewith.
3. The photonic computing array of claim 1, wherein: the input row waveguide (31) is perpendicular to the output column waveguide (32).
4. The photonic computing array of claim 1, wherein: the wavelengths of the light of the input optical signals of the input row waveguides (31) of the different rows are different.
5. The photonic computing array of claim 1, wherein: the input optical signal is enabled to evenly distribute the optical power of the input optical signal to each photon computing unit (1) on the same row under the action of the waveguide coupling device (2).
6. The photonic computing array of claim 1, wherein: the number of rows of input row waveguides (31) and the number of columns of output column waveguides (32) of the photon computing array are at least equal to or greater than 2.
7. The photonic computing array of claim 1, wherein: the size of the photon computing unit (1) is smaller than 100 μm.
8. The photonic computing array of claim 1, wherein: the voltage amplitude of the electrical signal as external excitation is less than 10V and the duration is less than 100 mus.
9. The photonic computing array of claim 1, wherein: the relative positions of the optical waveguide (11) and the electro-optical modulator (12) may or may not be in the same plane.
10. The photonic computing array of any one of claims 1 to 9, wherein: an input end of an input row waveguide (31) of the photon computing array is connected with a Multiplexer (MUX), and an output end of an output column waveguide (32) is connected with a Demultiplexer (DEMUX).
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