CN116888440A

CN116888440A - Optical computing method and system based on high-speed time-gated single photon detector array

Info

Publication number: CN116888440A
Application number: CN202180094202.5A
Authority: CN
Inventors: 斯雷尼尔·萨哈; 阿马汉·埃沙吉
Original assignee: Huawei Technologies Canada Co Ltd
Current assignee: Huawei Technologies Canada Co Ltd
Priority date: 2021-03-10
Filing date: 2021-03-10
Publication date: 2023-10-13
Also published as: WO2022187929A1

Abstract

A Single Photon Avalanche Diode (SPAD) array is divided into sub-arrays, each sub-array being activated in sequence while the remaining sub-arrays are charged. Overall, SPAD arrays are used as continuous operation photodetectors with improved performance, including lower power requirements, lower noise, lower capacitive loading, and other benefits. The system may be integrated in an electro-optic architecture based on electrically modulated optical elements, such as weighted micro-ring resonators, to perform optical calculations, particularly multiply-accumulate operations (MACs), with increased efficiency. Contemplated applications include neuromorphic computing, communications, and other processing-intensive computing.

Description

Optical computing method and system based on high-speed time-gated single photon detector array

RELATED APPLICATIONS

The present application is the first application filed for the present application.

Technical Field

The present application relates generally to the field of optical logic elements, and more particularly to a method and system for measuring photon counts in an electro-optic circuit and generating corresponding electronic and optical signals.

Background

Neural network models have played an important role in machine learning over the last decade, benefiting from significant algorithm innovations and new hardware, in particular graphics processing units (graphical processing unit, GPUs). But today even GPUs are pushed to the limit, so new hardware needs to be developed to accelerate machine learning computations. Various research communities and technical companies, including Google, IBM, intel, microsoft, and amazon, invest significant amounts of funds on massively parallel application-specific integrated circuits (ASICs) to accelerate the computation required by neural network models.

A very promising alternative to GPUs is optical computation using silicon photons, which allows the implementation of photonic circuits integrated with complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) chips for electronic control, and is expected to enable ultra-fast information processing.

Efficient and competitive optical computing hardware architectures are required to implement various attributes of digital optical logic, including low power consumption, high algorithm or computational efficiency, no capacitive loading effects, no cross-talk between signals, high speed operation, high noise margin, and high fan-in/fan-out. The photodetectors used in these structures play an important role in meeting the requirements of optical computing systems.

Some of these structures are referred to as neuromorphic photonic processors, which incorporate a class of photonic hardware accelerators designed to assist in the acquisition, feature extraction, and storage of broadband waveforms. These accelerators manipulate the spectral-temporal distribution of the broadband signal, a task that is difficult to accomplish using analog electronics at wide bandwidths and low losses.

Many challenges are involved in the implementation of photonic computing architectures, including: noise inherent to analog building blocks, limited computational efficiency, nonlinearities associated with photonic components, and scalability are reduced. In order for these architectures to be widely used for optical computing, it is necessary to address these bottleneck problems. This allows for efficient integration of well-defined photonic neurons and neural interconnects on a common photon-electron platform.

In particular, one limitation is that current state-of-the-art Photodetectors (PDs) that can be used as sensitive optical receivers in photonic computing systems have limited responsiveness and suffer from high excessive noise.

Accordingly, there is a need for a detection method or system that can eliminate or reduce one or more of the limitations of the prior art in photon processing by exhibiting higher speed and responsiveness, higher efficiency, less noise, less nonlinearity, and improved scalability.

The purpose of this background information is to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is made that any of the above information constitutes prior art against the present invention.

Disclosure of Invention

The problems involved in the physical implementation of neuromorphic calculations can be solved by introducing single-photon avalanche diodes (SPADs) in the system, especially in the form of an array configuration, as photodetectors. By using a SPAD array, which is subdivided into sub-arrays and each sub-array is activated in turn, such that the array as a whole always has at least one activated sub-array at any given time, the array can be used as a unique photodetector with many benefits over a conventional photodetector. The use of two SPAD arrays at the output of the add-drop configuration of the modulating optics can be used to implement the accumulation portion of the multiply-accumulate optical circuit with consideration of the negative term and the dark count rate inherent to SPADs. Benefits of optical computing include lower energy consumption, higher responsiveness, lower noise and digital domain, and the like.

An aspect of the present disclosure provides a method for detecting an optical input signal by: receiving an optical signal by an optical detector array, the optical detector array divided into a plurality of sub-arrays such that each sub-array comprises a plurality of optical detectors; activating the sub-arrays sequentially by applying a voltage signal to each of the photodetectors of the sub-arrays substantially simultaneously while deactivating and maintaining the photodetectors of the other sub-arrays substantially simultaneously until further repetition of the sequence; and charging the deactivated optical detectors of the array. In an embodiment, each sub-array may be connected to a dedicated counter, and the output of each activated sub-array may represent photon counts. In an embodiment, photon counts of each dedicated counter may be registered in non-transitory memory. In an embodiment, the time gating sequence of activating and deactivating sub-arrays of the array may be repeated indefinitely until stopped. In an embodiment, activating the subarray may include applying a bias voltage to its optical detector and deactivating the subarray may include removing the bias voltage from its optical detector. In one embodiment, activating and deactivating the subarray may be performed by a voltage controlled oscillator, a variable delay block, a pulse width modulator, and a buffer. In one embodiment, each optical detector of the array may be a Single Photon Avalanche Diode (SPAD). In an embodiment, each optical detector of the array may be a superconducting nanowire single photon detector (superconducting nanowire single photon detector, SNSPD).

One aspect of the present disclosure provides a system for performing optical calculations, the system may include: at least one optical waveguide for propagating an optical input signal; at least one row of at least one optical element, each optical element modulated by an electrical input signal, each optical element for producing a corresponding modulated optical output signal from the optical input signal; and at least one Single Photon Avalanche Diode (SPAD) for receiving an optical output signal modulated by the at least one optical element. In an embodiment, a system may include a plurality of SPADs configured as an array of SPADs that receive an optical output signal; the SPAD array may be divided into a plurality of SPAD sub-arrays such that each SPAD sub-array includes at least one SPAD, and each SPAD sub-array may be connected to a time gating circuit for sequentially activating and deactivating the SPAD sub-arrays one at a time; each SPAD sub-array may be connected to a dedicated counter. In an embodiment, a system may include at least one SPAD that may be time gated according to parameters including SPAD activation duration, SPAD deactivation duration, and rate at which activation and deactivation may occur; SPAD activation allows its operation and deactivation allows its charging. In an embodiment, each optical element of the system for performing optical calculations may be a modulated micro ring resonator (modulated microring resonator, MRR) having a drop port (drop port) for transmitting optical signals to a first SPAD array and a pass port (through port) for transmitting optical signals to a second SPAD array; the output of the first SPAD array and the output of the second SPAD array may be received by the same subtractor. In an embodiment, the optical elements of the system for performing optical calculations have drop ports and pass-through ports, and the output from each row of optical elements may be received by a respective subtractor through the first SPAD array and the second SPAD array. In an embodiment, the laser sources may be connected to each subtractor that collects the output of a row of optical elements through the SPAD array, such that each laser source may be modulated by the output of the subtractor. In one embodiment, at least one laser source is modulated by the output of a subtractor and a wavelength division multiplexer (wavelength division multiplexer, WDM) can receive an optical signal from each modulated laser source and multiplex the optical signal into a single output.

Drawings

Fig. 1a shows an electro-optic architecture in which a balanced photodetector is directly connected to an optical modulator.

Fig. 1b shows how neurons can be modeled with micro-ring resonators used in a add-drop configuration.

Fig. 2a is a diagram representing a Broadcast-weight (Broadcast-and-weight) protocol for neuromorphic photons, according to an embodiment.

Fig. 2b shows an architecture for a matrix loading and photon calculation block according to an embodiment.

Fig. 3 is a block diagram of a counting module for a SPAD light detector according to an embodiment.

Fig. 4a illustrates a periodic time-gated burst that is generated to activate time-gated SPAD (TG-SPAD), according to an embodiment.

Fig. 4b shows a hardware configuration for generating a time gate signal according to an embodiment.

Fig. 5 illustrates a TG-SPAD array architecture according to an embodiment.

Fig. 6 shows the architecture of a sub-array (SA) with 16 SPAD photodetectors and its front-end circuitry according to an embodiment.

Fig. 7 shows a front-end circuit for TG-SPADs, which are part of SPAD sub-arrays according to an embodiment, fig. 7 being divided into fig. 7a, fig. 7b, fig. 7c and fig. 7d according to an embodiment.

Fig. 7a shows how voltage signals for operation, time gating, quenching and resetting operations are applied to a light detector according to an embodiment.

Fig. 7b shows how a transistor may be used to detect the voltage on the light detector according to an embodiment.

Fig. 7c shows a circuit for counting the number of detected events according to an embodiment.

Fig. 7d shows a read transistor for addressing a pixel according to an embodiment.

Fig. 8a is a diagram showing how each of the 16 TG-SPAD sub-arrays can be sequentially triggered to be on and off during different time windows according to an embodiment.

Fig. 8b shows a TG-SPAD photodetector array according to an embodiment, wherein each sub-array is connected to a different counter.

Fig. 9 illustrates a modulated Micro Ring Resonator (MRR) in a add-drop configuration, where the pass-through port and drop port are connected to two TG-SPAD arrays, according to an embodiment.

Fig. 10 illustrates an electro-optic architecture for performing dot product using at least one TG-SPAD array according to an embodiment.

FIG. 11 is a schematic diagram of a photonic neural network based on a TG-SPAD array, according to an embodiment.

Fig. 12 is a simplified block diagram of a SPAD-based optical computing system according to an embodiment.

Fig. 13 illustrates the major nonlinearities that may affect the performance of a silicon micro-ring modulator according to an embodiment.

Fig. 14a shows how a Photodiode (PD) can be connected to other electronic circuits according to the prior art.

Fig. 14b shows a Single Photon Avalanche Diode (SPAD) front end circuit according to an embodiment.

It should be noted that throughout the appended drawings, like features are identified by like reference numerals.

Detailed Description

In an embodiment, the problems involved in the physical implementation of neuromorphic computation may be solved by efficiently integrating well-defined photonic neurons and neural interconnects on a common electro-optical platform, in particular by introducing Single Photon Avalanche Diodes (SPADs) in the system, in particular in the form of an array configuration, as photodetectors.

In optical computing and in general, a photodetector may be used as an optical-to-electronic (O/E) converter to detect incoming photons and produce a current or resistance change proportional to the input optical power. In the case of a photoelectric effect in the PN junction, the absorbed incoming photons generate free electron-hole pairs that drift across the junction, producing a power dependent current, known as photocurrent.

In addition to the photodetector, the connection of the optical component to the electronic device may be facilitated by the use of mixed signal integrated circuit blocks, such as digital-to-analog converters (DACs) and analog-to-digital converter (ADCs).

The integration of the improved photodetector to detect individual photons can significantly improve the performance of the optical computing system and reduce the complexity of the electronics.

Neuromorphic photonic systems can exhibit high efficiency, high interconnectivity, and high information density, and can pave the way for ultrafast, high performance, low cost, and complex signal processing. Calculations necessary for neuromorphic calculations include dot product (like multiply-accumulate (MAC) operations and convolution), electro-optic architectures can be used to perform these operations at significantly higher frequencies than conventional electronics. Some of these architectures may successfully utilize novel neuroscience tools, such as a broadcast-weight architecture based on silicon photons. These architectures are potentially integrated with silicon photonics over traditional computing hardware. The following four electro-optic systems corresponding to fig. 1a, 1b, 2a and 2b are four neuromorphic architectures that may be improved by using improved photodetectors such as SPADs, particularly when used in arrays according to embodiments.

A silicon photonic modulator-based optical neuron design may consist of a balanced photodetector directly connected to a modulating microring resonator (modulating MRR). Such optical neurons have the necessary capabilities of network compatible neurons: fanin, high gain optical-optical nonlinearity, and variable cascading characteristics. For neuromorphic optical calculations, the modulated MRR may be considered an electronic-to-optical (E/O) converter. For modulating voltage or current dependent optical transmission, various effects can be considered, including thermo-optical, acousto-optical, electro-optical and other effects, but in all cases a modulator with electronic control consists of an optical input acting as a pump, typically with constant power and constant wavelength. In the case of a voltage mode power modulator, the optical transmission of the modulator is voltage dependent.

Fig. 1a shows a physical diagram 102 and an electrical diagram 104 of an electro-optic architecture for a balanced photodiode 106 directly connected to an MRR modulator 108. The balanced photodiode 106 is biased 110 and converts incident light into photocurrent. The photocurrent in combination 112 with the bias current 114, the sum of which affects the refractive index of the MRR modulator 108. Thus, the pump signal 116 transmitted through the MRR is modulated into an output optical signal 118.

Another configuration of optical neurons based on silicon photonic modulators is known as a dual waveguide configuration, or add-drop (MRR) configuration. In this case, the relation between the transfer functions of the light intensities of the pass-through port and the drop port with respect to the input light can be calculated by connecting the pass-through port and the drop port of the MRR into balanced photo detectors and amplifiers, typically transimpedance amplifiers (transimpedance amplifier, TIA). Due to the tunable gain of the TIA, a user-defined modulation may be achieved at the output. The main purpose of incorporating balanced photodetectors at the output of the add/drop MRR is to represent the positive and negative nuclei in the analog photons. The balanced photodetector may be used as an input port to allow for a push-pull current configuration. In the case of a spiking neural network (spiking neural network), the resulting difference in current from the two photodetectors may flow directly into the gain section of the distributed feedback (distributed feedback, DFB) laser.

FIG. 1b shows a dual waveguide configuration, also known as a add-drop MRR configuration, and how it can be used as a photonic neuron with an input optical signal that can be modulated. The input light 120 is split into two parts. A portion passes through a waveguide called a pass-through port 122 directly to a balanced photodetector 124. The other portion is transmitted to the MRR 126, and the MRR 126 modulates and drops (carries) the signal to another waveguide, referred to as a drop port 128, which is connected to the balanced photodetector 124. The electrical output signal of the balanced photodetector is then directed to TIA 130 for amplification.

The "broadcast-weight" protocol is a protocol that has been proposed as a standard protocol for implementing neuromorphic processors using integrated silicon photonics. It is based on a silicon photonic modulator, exhibiting the necessary functions of network compatible neurons. It can effectively simulate physical neurons and serve as a basic building block for neuromorphic processors. The broadcast-weight protocol can implement a generalized, fully programmable, and recursive neural network model. In the broadcast-weight protocol, the output of each neuron is assigned a unique wavelength carrier that is wavelength division multiplexed (wavelength division multiplexed, WDM) and broadcast. The incoming WDM signal is first weighted by a continuous value filter that acts as a reconfigurable photon weight set (weight bank). The outputs of the weights are then summed by detecting the total optical power of the weights. The architecture may be implemented using a set of tunable silicon MRRs that simulate physical neurons by recreating on-chip synaptic weights. In order to model the synapse-like connection of physical neurons, a Mach-Zehnder interferometer (Mach-Zehnder interferometer, MZI) may also be used instead of a similarly configured MRR. Neuromorphic photon processors incorporate a class of photon hardware accelerators designed to assist in the acquisition, feature extraction, and storage of broadband waveforms. These accelerators can manipulate the spectral-temporal distribution of a broadband signal, a task that is difficult to accomplish using analog electronics at wide bandwidths and low losses.

Fig. 2a is a diagram showing a broadcast-weight protocol. Which shows configurable analog weights in a neuromorphic photon broadcast-weight network. MRRs for different wavelengths are used together to make a tunable spectral filter 240. The tunable spectral filter 240 may input various signals 242, divide them according to their wavelengths, and modulate each signal independently according to an electrical modulation 244. The output signals are summed by optical power detector 246. Optical power detector 246 may generate an electrical signal 248 to power a laser source that serves as an E/O converter 250. With different wavelength laser sources for each of a series of tunable spectral filters, the laser outputs can be multiplexed 252 into a single beam 254 of new weights that can be sent to another neuron or returned to the same neuron. In some embodiments, the power detector 246 includes at least one SPAD light detector.

A fourth system that can be used for matrix multiplication is one such system: after each of the two matrices is converted to a vector, a tunable MRR may be used to load the vector components. Each component of the first vector may be encoded as the strength of the wavelength multiplexed signal and each component of the second vector may be encoded as the weight that modulates the signal in the MRR. Each weighted MRR may modulate the intensity of a component of the first vector, effectively effecting multiplication of the two components. The components of the two vectors may be linked by an optical waveguide. Once all the multiplications of the signals and weights have been performed, their summation (i.e. summation) can be performed by detecting the total power of all the wavelength channels. To represent positive and negative weights in the analog photons, a balanced photodetector architecture may be incorporated at the outputs of the drop and pass-through ports of the add/drop MRR, and may be followed by the TIA to provide variable gain.

Fig. 2b shows the architecture of a photonic computation block comprising a matrix loading block. After the input data 260 is processed by a time-division multiplexing (TDM) unit 262, it may be subjected to a photon product accumulation (MAC) operation in a photon MAC block 264. In the MAC block, each wavelength of the wavelength multiplexed signal 266 may be loaded into a separate MRR 268 through a silicon waveguide 270. Each component of the first vectoring matrix may be loaded onto MRR 268 by digital-to-analog (DAC) 272 and by tuning the resonant wavelength of the MRR to modulate the intensity of the corresponding wavelength of input signal 266. After loading the components of the first vectorized matrix, the components of the second matrix may be similarly loaded into the second set of DACs 274, the second set of DACs 274 tuning the second set of MRRs 276 accordingly. Multiplication is performed when the signal 278 weighted with the components of the first vector is modulated by the MRR weighted by the second component 276. The products of the components are accumulated (i.e., summed) by balanced photodetector 280 and the result may be amplified by TIA 282. The result may then be converted to a digital signal by ADC 284 and further processed using digital electronic hardware 286. Vector multiplications of at least 512 sizes can be calculated 288 with a sufficiently compact photon block 264. In some embodiments, the accumulation portion of the multiply-accumulate operation is performed using at least one SPAD photodetector.

The limitation of the neuron-simulated electro-optic architecture to perform vector dot product can be avoided by: their summed photo-detectors (PD) are biased above the breakdown voltage and operated in Geiger mode as Single Photon Avalanche Diode (SPAD) photo-detectors. When operating in geiger mode, a single input photon can trigger a self-sustaining avalanche event and thus be easily detected, making SPAD a superior sensor for low intensity light detection. SPAD-based systems can provide significantly improved single photon detection sensitivity compared to conventional photodiodes. Because of its simple structure, SPAD can be integrated into Application Specific Integrated Circuits (ASIC) for wide applications such as intra-chip communications, quantum key distribution, deep space laser communications, three-dimensional imaging, and charged particle detection.

SPAD is a semiconductor device capable of acquiring optical signals as low as a single photon level with high time resolution, very low noise, and extended Dynamic Range (DR). SPAD photodetectors are of interest because they have good photon detection efficiency (photon detection efficiency, PDE) and low timing jitter.

One of the main problems to be overcome in order to achieve an efficient physical implementation of neuromorphic computation is the error generated by inherent noise such as random shot noise, spectral noise, johnson-nyquist noise and flicker noise. The main noise contributions are quantization noise in the ADC and distortion of the radio-frequency (RF) signal applied to the modulator. The development of Radio Frequency (RF) complementary metal oxide semiconductor (complimentary metal-oxide semiconductor, CMOS) integrated microelectronic chips, including high speed drivers, control circuits, DACs, ADCs, synchronous Dynamic Random Access Memories (SDRAM), and 3D integration with silicon photonics platforms, can help minimize parasitic effects on the overall throughput of the system.

The conversion quality of a Photodetector (PD) of a system that generates an output electrical signal from an incoming optical signal can greatly impact the overall performance of the overall system. In general, an ideal PD should have high responsiveness, large bandwidth, high quantum efficiency (quantum efficiency, QE), low applied voltage bias requirements, low dark current, and CMOS compatibility. Unfortunately, PD can generate excessive noise sources related to gain, which limits the maximum gain to between 2 and 20. The disadvantage is that the PD must be connected to high bandwidth analog electronic circuits (e.g., TIA and ADC). These analog peripheral circuits consume a large amount of power, which has an adverse effect on the performance of an optical system including many PDs. Embodiments address these problems by using a time-gated single-photon avalanche diode (TG-SPAD) array architecture that can be easily integrated with CMOS processes and achieve good noise immunity, low power consumption, high packing density, and scalability.

In an embodiment, the basic building block of neuromorphic photons is a photonic neuron, which is a light-in light-out device. It may use an optical/electrical/optical (O/E/O) signal path with lumped intermediate electrical connections to convert multiple independently weighted inputs to a single output, apply a nonlinear transfer function to the weighted sum of the inputs, and produce an output capable of driving multiple other neurons, including itself. In an embodiment, the light detector for photoelectric conversion may be a reverse biased PN (p-n junction) photodiode. In the case of a spiking neural network, the current generated by the photodetector flows directly into the gain section of the DFB laser for optical conversion. In other methods, such as the "broadcast-weight" method, the electrically weighted sum may modulate a corresponding wavelength-division-multiplexed (WDM) carrier by a nonlinear or dynamic electro-optic process by means of an MRR or MZI. At the output of the photodiode, the current may be amplified by the TIA, which in the case of monolithic integration may be fabricated on the same chip. For heterogeneous integration, the TIA and other electronic control circuits may be fabricated in other standard CMOS processes and connected to the corresponding photonic chips by wire bonding or flip chip bonding. In some cases, a matrix multiplier, for example, coupled to the ADC, is also required to calculate a digital representation of the data.

Embodiments relate to and include neuromorphic electro-optic systems using arrays based on time-gated Single Photon Avalanche Diode (SPAD) photodetectors to speed up signal processing and reduce the use of analog design blocks. Since the SPAD output is already in the digital domain, no additional analog design blocks are needed for further processing. This may provide significant advantages in terms of lower power consumption, higher computational efficiency, higher noise margin, higher speed operation, and minimal capacitive loading.

In one embodiment, a time-gated SPAD (TG-SPAD) architecture is introduced to improve the dynamic range and count rate (i.e., throughput) of the photodetector. Typically, the count rate or operating frequency of a single photon detector is limited by its inherent dead time. However, in an embodiment, the count rate may be significantly increased and the effect of dead time of the photodetector may be mitigated.

A Single Photon Avalanche Diode (SPAD) is a semiconductor device capable of receiving and acquiring an optical signal as low as a single photon level with high time resolution, extremely low noise, and extended Dynamic Range (DR). As such, SPAD is a device that may be used to detect optical input signals. The fundamental difference between SPAD and Photodiode (PD) is that SPAD is specifically designed to be well above breakdown voltage (V _BD ) Is operated by the reverse bias voltage of (a). In contrast, the PD operates with a bias voltage less than the breakdown voltage. To detect incident radiation, SPAD utilization is reverse biased above V _BD Photons of the p-n junction of the so-called "over-bias" trigger the avalanche current. With such bias voltage signals, the electric field is sufficient to enable a single charge carrier injected into the depletion layer to trigger a self-sustaining avalanche. In some embodiments, the electric field is greater than 3E 5V/cm. The current rises rapidly (rise time is sub-nanosecond) to a macroscopically steady level, in the milliamp range. If the main carrier is photo-generated, the leading edge of the avalanche pulse marks the arrival time of the detected photon (time jitter is picoseconds). The current continues to flow until by decreasing the bias voltage to or below V _BD Quenching the avalanche. This reduces the electric field across the junction, thereby stopping the current flow by disabling the acceleration of the carriers and preventing them from ionizing by collisions with lattice atoms. In order to detect another photon, the bias voltage must rise again to V _BD The above. The initiation (ignition) due to carriers generated by thermal or tunneling processes represents the noise of the photodetector itself and causes a so-called Dark Count Rate (DCR). In addition, some carriers are also trapped during avalanche and ready to detect later in SPAD The photons are released causing a spurious trigger called an afterpulse. Appropriate circuitry, possibly tailored based on fine modeling of the electrical behavior of such photodetectors, may be used with SPADs to achieve optimal timing performance and reduce the effects of the residual pulses. In addition, SPAD can be biased (several volts) from V _BD Below to V _BD The above analog modulation is turned on and off. The on-state and off-state of the SPAD may be referred to as "active" state and "inactive" state, and the act of turning the SPAD on and off may include applying and removing a bias voltage to the SPAD. Applying and removing bias voltages to SPADs may also be referred to as "activating" and "deactivating" SPADs, and such bias voltages may be applied as voltage signals. When the photodetector is biased to V _BD Photons absorbed below do not trigger a self-sustaining avalanche; it is therefore not detected by the readout electronics. SPADs require suitable circuitry that must: 1. sensing a leading edge of the avalanche current; 2. generating a standard output pulse synchronized with avalanche accumulation; 3. by lowering the bias voltage to the breakdown voltage V _BD Quenching the avalanche current; 4. the SPAD is restored to the operating level. The associated circuitry may be referred to as quench and processing circuitry.

Fig. 3 is a block diagram of a SPAD photodetector count module according to an embodiment. When photons 310 are incident to operate bias voltage signal V _op 330 on the SPAD photodetector 320, an avalanche current process is initiated. Avalanche current flows through ballast resistor R340, initiating a passive quenching process that quickly senses the avalanche current. This in turn is achieved by making the switch S _Q 350 The (quench switch) is closed to begin the active quench process, which causes the capacitance C of the SPAD photodetector to be _d 360 with a time constant R (S) _Q )×C _d Rapidly discharge, wherein R (S _Q ) Indicating switch S _Q 350 nominal on-resistance, C _d Representing the termination capacitance 360 of SPAD. Using this technique, SPADs can be kept in a quenched state for a period of time (referred to as a hold-off time). To charge the SPAD and recover the bias voltage 330 of the SPAD, the switch can be turned onSwitch S _Q 350 and may be followed by a switch S _R 370 (charging switch) is closed. This can enable SPAD to be made up of R (S _R )×C _d The given time constant is fast charge, R (S _R ) Is a switch S _R 370 on-resistance. After a few nanoseconds, switch S _R 370 open again, ending the charging phase and readying SPAD for another detection event. The control logic block 380 may be used to cause the switch S _Q 350 and S _R 370 open and close, the counter 390 may keep track of the switch. The benefit of the SPAD architecture is the direct integration of SPAD photodetectors. This may replace the use of discrete devices and provide well-defined delays. It can also speed up the dead time of the voltage definition and provide a greatly reduced parasitic capacitance and smaller avalanche charge, thus enabling a reduction in intervening resets.

The maximum count rate and bandwidth of SPADs may be limited by the inherent resistance capacitance (resistance capacitance, RC) time constant, which may affect the SPAD's charging time. To address this problem, embodiments include an array of time-gated SPADs.

In an embodiment, the advantage of using SPAD is that by biasing its photodiode to breakdown voltage V in a very short time _BD Above, the bias voltage is then removed, which may turn SPAD on and off, or activate and deactivate. The act of activating and deactivating SPADs may be referred to as time gating, and activating SPADs within a specified time window may be referred to as the activation duration of SPADs. The time gate may also be adjustable in width (i.e., the terms "width" and "window," which are intended in the art to mean "duration") and frequency (i.e., repetition rate, or number of activations per unit time) because the time gate may be periodically repeated with respect to the trigger frequency (i.e., synchronization pulse), which may be provided by an integrated voltage controlled oscillator. One feature of these embodiments is that the SPAD photodetector is only sensitive during the time gate when it is activated, and does not detect any photons in the absence of a gate signal, i.e., when it is deactivated.

Fig. 4a shows an implementation of time-gated SPAD according to an embodiment, in which a periodic time-gated pulse train 410 is generated. The duration 420 of each pulse and the delay 430 between each pulse may be controlled with a bias voltage signal. For such a pulse train, SPAD is sensitive 440 to the detected photon when the bias voltage signal is applied, and SPAD is not sensitive to the detected photon even if the photon is incident 450 when the bias voltage signal is not present.

In an embodiment, when the avalanche process is triggered due to an input photon within the time gate, a pulse of adjustable width is generated at the output of the detection electronics and a user-tunable dead time may be initiated by the quenching circuit substantially simultaneously. Applying the appropriate dead time (when they occur completely or nearly simultaneously, they occur substantially simultaneously.) in combination with the time gating feature can be used to greatly reduce the effects of Dark Count Rate (DCR) and the afterpulses.

Fig. 4b shows how a time gating signal may be generated according to an embodiment. The synchronization pulse generated by voltage-controlled oscillator (VCO) 460 is delayed to turn SPAD on (i.e., activate) after a specified time window. Using variable delay block 470, the amount of delay may be user tunable with a step delay of 10 ps. To select the width of the delayed gating window, the pulse width modulator 480 may provide the SPAD photodetector with the appropriate on-time. The width of the time window may be selected to be 1 nanosecond (ns) to 2 ns, determining the time frame during which the SPAD photodetector should remain active and ready for photon detection.

In one embodiment, the SPAD array architecture can be composed of SPAD arrays each having 1/T _dead Is made of a plurality of SPAD's of maximum count rate, where T _dead Is the dead time of SPAD, also known as the "dead time" of SPAD, or the duration of its deactivation. Each Subarray (SA) may be composed of a plurality of time-gated SPADs (TG-SPADs), and any number ST of the plurality of SPADs may be activated during the same time window Δt. Activation of SPADs of the same SA may be performed substantially simultaneously, as may their deactivation. In one embodiment, each sub-array (SA) may be composed of 16 TG-SPAD fabricsSquare arranged in r=4 rows and r=4 columns; and in another embodiment, each SA may consist of 64 TG-SPADs arranged in squares of r=8 rows and r=8 columns. However, other array configurations and other numbers of rows and columns may also be different. Activating all SPADs of the SA substantially simultaneously within the same time window can increase the count rate of the SA to R ² /T _dead Wherein R is ² The number of pixels in the SA (i.e., the number of rows x the number of columns). Thus, dividing a large SPAD array into smaller groups of mxn subarray SAs allows each SA to function effectively as a single SPAD (M and N are the number of rows and columns, respectively, of SPAD subarrays), which can increase the effective count rate of the SPAD array architecture to mxn×r ² /T _dead 。

Fig. 5 illustrates a TG-SPAD array architecture according to an embodiment that allows for increased operating speed, dynamic range, and count rate. Each SPAD 510 may have a detection count 520 of 0 or 1 during a defined time window Δt. The count rate 530 of SPAD isAnd is controlled by the length of time (T) that the SPAD is unbiased _dead ) I.e. the expiration time or deactivation duration). Sub-array (SA) 540 of SPADs may include r=8 columns of SPADs multiplied by r=8 rows of SPADs, resulting in a square of r×r=64 SPADs. For such SA, count rate 550 is +.>If multiple sub-arrays are combined into a larger square with M rows of sub-arrays and N columns of sub-arrays, the count rate 570 of the entire array 560 may be +.>In the embodiment of fig. 5, the array includes m=4 row sub-arrays and n=4 column sub-arrays.

In an embodiment, the architecture of the SAs is such that each SA can be triggered at the same specified time and for the same time window, and it can have its own dedicated counter (i.e., the counter assigned for that particular SA) to register its photon count. All SPADs of the SA may be activated substantially simultaneously, and after the time window has elapsed they may also be deactivated substantially simultaneously.

Fig. 6 shows a sub-array (SA) architecture consisting of 16 SPADs, each of which may be referred to as a pixel, and front-end circuitry. The time gating buffer 610 may turn SPADs on and off independently according to a predefined off-time delay and on-time window. The time-gated SPADs 620 may be arranged in sub-arrays (SAs) with 4 columns and 4 rows to form 16-SPADs SAs. Each SPAD has a dedicated mixed quench circuit (mixed quenching circuit, MQC) 630. The counts for all SAs may then be summed in counter 640 and stored in memory 650, such as non-transitory memory.

Fig. 7a, 7b, 7c and 7d illustrate front-end circuitry of a TG-SPAD according to an embodiment, which is part of a SPAD sub-array.

In FIG. 7a, operation V _OP The voltage signal of 705 is applied to the photo detector 710. Operation V _OP 705 is greater than the breakdown voltage V of the photodetector _BD 715 and it may be applied for a short period of time. Applied V _OP 705 and breakdown voltage of photodetector V _BD 715 may be referred to as an excess bias voltage V _EX 720. The light detector 710 is sensitive only for this adjustable period of time, which may be referred to as a time gate, and is capable of detecting incoming photons during this adjustable period of time. In a first part of the circuit, the time gating operation is performed by a p-channel metal oxide (p-channel metal oxide, PMOS) transistor M _G 725, which can pull the SPAD anode voltage higher than the diode breakdown voltage V _BD Intermediate supply voltage V of (2) _OP Excess bias voltage V of substantially SPAD _EX ＝V _OP -V _BD . The time gating circuit may utilize a thick oxide transistor M _G 725 time gating, quenching and reset operation M _R 730。

In fig. 7b, a thick oxide transistor M _C 735 and thin oxide transistor M _B 740 are used to detect the voltage on the SPAD anode.

In FIG. 7c, the next part of the SPAD front end is formed by transistor M ₁ 745. Transistor M ₂ 750 and a set of inverters 755. Activation of M ₁ The latch can be flipped from its reset state, M ₂ May be used to reset the counter.

In FIG. 7d, the fourth part of the pixel front-end circuit is formed by the read transistor M _RD 760, which is used to address the pixel. According to pass transistor M _DOWN 760, column line is pulled down, M _UP 765 is used as a pull-up transistor.

In an embodiment, each SA may be activated within a specified time window such that two SAs are not triggered at the same time. When one SA is activated, the previous SA may be deactivated substantially simultaneously. Multiple SAs, each with a dedicated counter, may be triggered one after the other, and each photon count may be registered in the corresponding counter. The number of photons detected by the SA may give optical intensity information, so each counter may give intensity information for a specific time window. The method of recording the optical intensities of multiple consecutive time windows according to an embodiment may greatly improve the performance of a single photon detector array as a whole.

Fig. 8a is a diagram showing how the individual SAs are sequentially activated or triggered to be on in sequence within different time windows. In an embodiment, each SA 810 may be activated or on for 1 nanosecond (ns) 820, which may be followed by a dead/deactivation time or cut-off period 830 of 15ns, and each on-time may be immediately activated 840 when the previous SA is deactivated, such that activation of the subarray may occur substantially simultaneously with deactivation of the previously activated subarray, and the process may repeat indefinitely and until stopped, as deactivation may be repeated any number of times after activation, depending on the user's selection.

Fig. 8b schematically illustrates how the counter for each SA in the SA array can be read sequentially and can provide optical intensity data over a wide time scale, making the architecture of the embodiment suitable for high frequency applications. Each SA 810 may be associated with a dedicated counter 820, and the SAs may be sequentially turned on 830 during successive time windows.

Because deactivation or dead time can be applied to SPAD after each detection event, a disadvantage of SPAD may be a low count rate, which may limit its application in optical computing. However, using the techniques of the embodiments, the problem of low count rates can be solved. The time gate may be generated on-chip by a Voltage Controlled Oscillator (VCO). The output of the VCO may be connected to a variable delay generator to apply a user-tunable delay to select the time at which SPAD needs to be turned on. To provide a variable activation or on-time to the photodetector, the output of the variable delay generator can then pass through a pulse width modulator and then to a level shifter to provide the appropriate over-bias voltage to the SPAD.

In an embodiment, a TG-SPAD array may be used to collect outputs of pass-through ports and drop ports of a modulated MRR in an add-drop configuration. Such an architecture provides a significant improvement over conventional computing units used to process signals in optical computing systems. One feature of this architecture is that the inherent Dark Count Rate (DCR) of each SPAD photodetector can be eliminated at the output by a subtractor.

Figure 9 shows how two TG-SPAD arrays can be used with a modulated MRR in a add-drop configuration. The drop port output 910 and the pass-through port output 920 of the MRR are connected to two TG-SPAD arrays 930. Each of the two arrays collects an output from the MRR, which are combined by a subtractor to yield the final output of the system.

According to an embodiment, to perform dot-product with low-intensity signals, a TG-SPAD array system may be incorporated at the output of the drop and pass-through ports of a series of Micro Ring Resonator (MRR) weights. First input vector V ₁ May be encoded with signal strengths having different wavelengths, the strength of each signal corresponding to a vector component. Second input vector V ₂ May be encoded as a weighting factor to tune the resonant wavelength of the MRR. As such, when V by tuning the MRR ₂ Weighting factor pair V ₁ Weighting signalsTo modulate V ₁ At the component wavelength, V is performed ₁ And V is equal to ₂ Each multiplication of the dot product between. Such tuning may be performed by independently heating each MRR to a different temperature, but other mechanisms are possible, including thermo-optic, acousto-optic, electro-optic, and other mechanisms. Then, collecting all the products of the photodetectors may perform V ₁ ·V ₂ Sum of dot products. According to an embodiment, if the light detector is based on a TG-SPAD array, the signal strength may be very low.

Fig. 10 shows an electro-optic architecture in which dot-product can be performed. A pair of TG-SPAD arrays 1010 may be incorporated at the outputs of the drop and pass-through ports 1020 of a series of MRRs 1030, each MRR 1030 corresponding to a different vector component multiplication. A is that ₁ To A _k Is a component of the first vector, encoded into intensities 1040 of different wavelengths. They are multiplexed by a wavelength-division multiplexer (WDM) 1050 and an optical waveguide 1060, such as silicon, links them to MRR 1030, MRR 1030 being composed of a weight set F ₁ To F _k 1070 modulation. Weight group F ₁ To F _k 1070 is a filter value that modulates MRR 1030 according to the component of the second vector. In an embodiment, the weight set is implemented as a separate heater, modulating the MRR by tuning the temperature of the MRR and thus the resonant wavelength of the MRR. Tuning is effectively a multiplication between the component of the first vector (which is encoded as the signal strength in the MRR) and the component of the second vector (which is encoded as the temperature and resonant wavelength (i.e. "tuning frequency") of the MRR). Thus, each MRR is a point of product calculation between two vector components. Products each having a different wavelength are then summed in two TG-SPAD arrays 1010. The subtractors at the outputs of the two TG-SPAD arrays can cancel dark noise, and then the registers can provide electronic gain to the outputs.

In one embodiment, an optical computing system that performs multiple dot products may be implemented using TG-SPAD arrays, and this implementation achieves better performance in terms of computational efficiency, bandwidth, and power consumption.

FIG. 11 is a schematic diagram of a photonic neural network based on a TG-SPAD array in which the outputs of a number of dot products are used to modulate the outputs of as many laser diodes, having as many different wavelengths, the modulated laser diode signals being multiplexed into a single output waveguide, such as silicon. The independent weighting function of the input signal 1030 for each TG-SPAD array 1040 is implemented using a series of tunable spectral filters, such as MRR 1010, of a series of weighting sets 1020, which in some embodiments may be independent heaters. The total optical power of each spectral weighting signal 1030 is generated into the electronic sum 1050 of the input channels 1030 of the TG-SPAD array. The electronic sum 1050 is then converted to an optical signal 1080 using a laser diode source 1060 and an optical modulator 1070.

In an embodiment, the connection of the MRR to the electronic device may be facilitated by using a digital-to-analog converter (DAC), while the storage of the output and retrieval of the input may be implemented by at least one digital memory. A memory, which may also store photon counts accumulated by the integrated counter, may be connected to the computer, wherein the information is already in digital representation.

Fig. 12 is a simplified block diagram of a SPAD-based optical computing system in which the MRR 1210 connection to electronics is facilitated by a DAC 1220, and the storage of outputs and retrieval of inputs may be accomplished by a digital memory 1230, which digital memory 1230 may be non-transitory. A memory, which may also store photon counts accumulated by at least one integrated counter 1240, may be connected to the computer, wherein the information is already in a digital representation.

In embodiments of neuromorphic photonic networks, the laser power at the output of a modulator neuron may be sufficient to drive a subsequent neuron of the same network. In neuronal design, cascading of signals is a factor that should be considered so that a signal can evoke at least an equivalent small signal response after one round trip (if the signal is fed back to its original neuron). If the cascading condition is not met, the signal will eventually decay over time.

As shown in fig. 1c, the modulator-based broadcast-weight system may be partitioned into a modulator component 144 and a receiver component 146. Since the input optical power generates a photocurrent, the impedance R of the receiver _r Determining rotationChanging quality. The bandwidth f may be represented by the formula f= (2pi R _r C _mod ) ^–1 Determining, wherein C _mod Is the PN junction capacitance of the modulator. Thus, R is _r The increase in (a) results in a decrease in bandwidth f.

For reverse biased, voltage mode MRR depletion modulator, V _π Is the pi voltage of the modulator (i.e. the voltage required to convert the MRR resonance wavelength from one half wavelength), R _PD Is the responsivity of the photodetector. Pump power P of modulator _pump The calculation can be performed using the following formula:

by inserting f= (2 pi R) _r C _mod ) ^–1 For R _r Inversion, become:

P _pump (f)＝4(V _π C _mod )R _PD ^-1 f

the responsivity of a photodetector is defined as the average photocurrent produced per unit optical power, given by:

wherein I is _p Is the measured photocurrent, P _op Is the incident optical power at a particular wavelength on the sensor area.

For MRR depletion modulators fabricated in a typical silicon photonics casting platform, V _π ＝1.5V，C _mod =35 fF. Typical values for the response of photodetectors PD on the same platform are R _PD =0.97a/W. Thus, for a given signal bandwidth, the minimum pump power of the modulator can be calculated to be 2.16X10 ^–13 W/Hz. In contrast, SPAD has a significantly higher responsiveness than PD by the order of about 10e+5. This minimizes the minimum pump power required to about 2.2x10 ^–17 W/Hz。

Ring modulator systems such as micro-rings and micro-disk resonators can be quite complex and challenging to design due to their narrow-band nature, which makes them highly sensitive to manufacturing variations and environmental fluctuations (e.g., substrate temperature). Furthermore, the small size and high Q factor (quality factor) of these structures can lead to electric field enhancement and stronger light confinement. These properties may produce optical power densities that are high enough to generate nonlinear effects, including thermal and carrier-induced optical bistable states. Even though the input optical power is moderate (in the order of milliwatts), non-linear effects may lead to unwanted behavior.

Nonlinearities affecting performance mainly include: free carrier dispersion and free carrier absorption (free carrier absorption, FCA), both of which affect free carrier density, two-photon absorption (TPA), and thermal effects. These factors can affect the power handling limitations of the silicon micro-ring modulator. Currently, developments with longer link distances and improved link budgets require an increase in input optical power, which may further exacerbate the problems associated with handling high power, particularly in resonant modulators. Because SPADs have very high responsiveness and can detect very weak optical signals, even at the single photon level, implementation of SPADs can help mitigate nonlinear effects by minimizing the input optical power required by the system alone.

Fig. 13 is a time domain model of an externally modulated silicon resonator, showing the major nonlinearities that may affect the performance of a silicon ring modulator. Ideal control would include applying a modulation signal 1310 to cause a resonance shift 1320. However, the optical energy 1330 of the resonator may be sufficiently dense to cause two-photon absorption 1340, which in turn may cause an increase in free carrier density 1350 and self-heating 1360 in the resonator, both of which may further affect the resonance shift 1320. The two-photon absorption 1340 may affect not only the generation of free carriers 1350, but also their loss rate 1370. Essentially, the main nonlinearities affecting performance are: free carrier dispersion and Free Carrier Absorption (FCA), both of which affect free carrier density 1350, two-photon absorption (TPA) 1340, and thermal effects 1360.

In an embodiment, the time delay of the electro-optical conversion is the time delay between when the signal acquisition starts and when the data at the output of the converter is available. The time delay may also be referred to as "settling time". It cannot be zero and is generally considered to be the time delay required to converge the ideal step input to the final digital output value within the error margin. Time delay is critical in neuromorphic and optical computing applications.

Fig. 14a shows how a Photo Detector (PD) 1410 may be connected to other electronic circuits, first to TIA 1420, and then from TIA 1420 to ADC 1430. In one embodiment, the following is a typical delay Δt using typical values of the electronic circuit used _L And (5) calculating. First, the delay Δt of TIA 1420 _{L TIA} The delay of its sub-modules-gain stage and buffer-can be added to obtain:

Δt _{L TIA} ＝Δt _{L Gain Stage} +Δt _{L Buffer}

Δt _{L TIA} ＝78ps+73ps

Δt _{L TIA} ＝151ps

the delay Δt of the ADC 1430 can then be similarly obtained _{L ADC} The submodules are a comparator, an encoder and an amplifier:

Δt _{L ADC} ＝Δt _{L Comparator} +Δt _{L Encoder} +Δt _{L Amplifier}

Δt _{L ADC} ＝60ps+73ps+75ps

Δt _{L ADC} ＝208ps

in the case of PD systems, the total delay Deltat _{L total} The method comprises the following steps:

Δt _{L total} ＝Δt _{L TIA} +Δt _{L ADC}

Δt _{L total} ＝151ps+208ps

Δt _{L total} ＝359ps

fig. 14b shows the front-end circuitry of SPAD 1440, which may include a buffer 1450 and a counter 1460. In the case of SPAD systems, the typical value Δt of the buffer is used _{L Buffer} =73 ps and typical value Δt of counter _{L Counter} Time delay Δt of front-end circuit=73 ps _L The following can be calculated:

Δt _{L total} ＝Δt _{L Buffer} +Δt _{L Counter}

Δt _{L total} ＝73ps+73ps

Δt _{L total} ＝146ps

from the above comparison, using typical values, it is possible to infer the optically calculated time delay performance (Δt) based on TG-SPAD arrays _{L total} =146 ps) is generally better than PD-based systems (Δt _L _total =359 ps).

According to embodiments, implementation of time-gated SPAD arrays for photonic devices can help mitigate the limited count rate and bandwidth of other SPAD implementations, and also address bottlenecks inherent in other neuromorphic architectures, including I/O connection to digital systems through DACs and ADCs, modulator pump power, nonlinear effects, and latency. TG-SPAD array architectures with digital outputs can be used to perform basic convolution operations, including dot products of two vectorized matrices, and various nonlinear optical-optical transfer functions associated with various neural processing tasks. Can also be performed at significantly lower run times and increased computational efficiency compared to neuromorphic systems that do not use TG-SPAD.

Embodiments include a method that uses at least one single photon detector in an optical computing system for complex and high speed operation.

Embodiments include an architecture that can derive optical intensity from photon counts accumulated over multiple time bins and that does not use a complex analog light intensity measurement system.

Embodiments include a time-gated SPAD array architecture that is divided into several sub-arrays, and where each sub-array registers optical intensities for a particular sequence of on and off slots. This technique may improve performance compared to using a single photodetector because it may record the optical intensity for multiple consecutive time windows.

Embodiments include a system architecture that includes only a simplified digital block (e.g., counter) rather than using high bandwidth analog electronic circuitry.

Embodiments include a system architecture that includes both simplified digital blocks (e.g., counters) and high bandwidth analog electronic circuitry.

Embodiments using a photonic filter bank architecture may be implemented to compute inversion and multiplication operations of complex-valued matrices.

Embodiments may be used in photonic computing techniques to compute complex-valued matrix inversion and matrix multiplication for wireless communication applications.

Embodiments may achieve improvements in noise immunity, modulator pump power reduction, nonlinearity, and delay as compared to non-SPAD based architectures.

Embodiments may enable improvements in dynamic range, count rate, and reduced dark noise over architectures that are not SPAD-based.

Embodiments include employing single photon photodetectors in a photonic neural network.

Embodiments may be used to improve performance of an optical computing system in terms of power consumption and computing efficiency.

Embodiments may be used in conjunction with SPADs having improved performance, particularly where CMOS technology is involved, these may include silicon-based germanium SPADs, which may provide improved photon detection efficiency at larger wavelengths.

Embodiments may also be used in conjunction with a Superconducting Nanowire Single Photon Detector (SNSPD), which may provide a count rate of gigacounts per second.

An aspect of the present disclosure provides a method for detecting an optical input signal by: receiving an optical signal by an optical detector array, the optical detector array divided into a plurality of sub-arrays such that each sub-array comprises a plurality of optical detectors; activating the sub-arrays sequentially by applying a voltage signal to each of the photodetectors of the sub-arrays substantially simultaneously while deactivating and maintaining the photodetectors of the other sub-arrays substantially simultaneously until the sequence is further repeated; and charging the deactivated optical detectors of the array. In an embodiment, each sub-array may be connected to a dedicated counter, and the output of each activated sub-array may represent photon counts. In an embodiment, photon counts of each dedicated counter may be registered in non-transitory memory. In an embodiment, the time gating sequence of activating and deactivating sub-arrays of the array may be repeated indefinitely until stopped. In an embodiment, activating the subarray may include applying a bias voltage to its optical detector and deactivating the subarray may include removing the bias voltage from its optical detector. In one embodiment, activating and deactivating the subarray may be performed by a voltage controlled oscillator, a variable delay block, a pulse width modulator, and a buffer. In one embodiment, each optical detector of the array may be a Single Photon Avalanche Diode (SPAD). In an embodiment, each optical detector of the array may be a Superconducting Nanowire Single Photon Detector (SNSPD).

One aspect of the present disclosure provides a system for performing optical calculations, the system may include: at least one optical waveguide for propagating an optical input signal; at least one row of at least one optical element, each optical element modulated by an electrical input signal, each optical element for producing a corresponding modulated optical output signal from the optical input signal; and at least one Single Photon Avalanche Diode (SPAD) for receiving an optical output signal modulated by the at least one optical element. In an embodiment, a system may include a plurality of SPADs configured as an array of SPADs that receive an optical output signal; the SPAD array may be divided into a plurality of SPAD sub-arrays such that each SPAD sub-array includes at least one SPAD, and each SPAD sub-array may be connected to a time gating circuit for sequentially activating and deactivating the SPAD sub-arrays one at a time; each SPAD sub-array may be connected to a dedicated counter. In an embodiment, a system may include at least one SPAD that may be time gated according to parameters including SPAD activation duration, SPAD deactivation duration, and rate at which activation and deactivation may occur; SPAD activation allows its operation and deactivation allows its charging. In an embodiment, each optical element of the system for performing optical calculations may be a modulated Micro Ring Resonator (MRR) having a drop port for transmitting optical signals to a first SPAD array and a pass-through port for transmitting optical signals to a second SPAD array; the output of the first SPAD array and the output of the second SPAD array may be received by the same subtractor. In an embodiment, the optical elements of the system for performing optical calculations have drop ports and pass-through ports, and the output from each row of optical elements may be received by a respective subtractor through the first SPAD array and the second SPAD array. In an embodiment, the laser sources may be connected to each subtractor that collects the output of a row of optical elements through the SPAD array, such that each laser source may be modulated by the output of the subtractor. In one embodiment, at least one laser source is modulated by the output of a subtractor and a Wavelength Division Multiplexer (WDM) can receive an optical signal from each modulated laser source and multiplex the optical signal into a single output.

Embodiments have been described above in connection with aspects of the invention, which may be implemented according to these aspects. Those skilled in the art will appreciate that embodiments may be practiced in conjunction with aspects describing them, but may be practiced with other embodiments of the aspects. It will be apparent to those skilled in the art that embodiments are mutually exclusive or mutually incompatible. Some embodiments may be described in connection with one aspect, but may be adapted for use with other aspects, as will be apparent to those skilled in the art.

While the invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the invention. Accordingly, the specification and drawings are to be regarded only as illustrative of the invention as defined in the appended claims, and are intended to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention.

Claims

1. A method for detecting an optical input signal, comprising:

receiving the optical input signal by an optical detector array, the optical detector array divided into a plurality of sub-arrays, each sub-array comprising a plurality of optical detectors;

Activating each sub-array in sequence by applying a voltage signal to each light detector of each sub-array substantially simultaneously while deactivating and maintaining the light detectors of the other sub-arrays substantially simultaneously until further repetition of the sequence;

the deactivated optical detectors of the array are charged.

2. The method of claim 1, wherein each sub-array is connected to a dedicated counter, the output of each activated sub-array representing photon counts.

3. The method of claim 2, wherein the photon count of each dedicated counter is registered in a non-transitory memory.

4. A method according to any one of claims 1 to 3, wherein the time gating sequence of activating and deactivating sub-arrays of the array is repeated indefinitely until stopped.

5. The method of any one of claims 1 to 4, wherein activating the subarray comprises applying a bias voltage to its optical detector and deactivating the subarray comprises removing the bias voltage from its optical detector.

6. The method of any of claims 1 to 5, wherein activating and deactivating the subarray is performed by a voltage controlled oscillator, a variable delay block, a pulse width modulator, and a buffer.

7. The method of any one of claims 1 to 6, wherein each optical detector of the array is a Single Photon Avalanche Diode (SPAD).

8. The method of any one of claims 1 to 6, wherein each optical detector of the array is a Superconducting Nanowire Single Photon Detector (SNSPD).

9. A system for performing optical calculations, comprising:

at least one optical waveguide for propagating an optical input signal;

at least one row of at least one optical element, each optical element modulated by an electrical input signal, each optical element for producing a corresponding modulated optical output signal from the optical input signal;

at least one Single Photon Avalanche Diode (SPAD) for receiving the optical output signal modulated by the at least one optical element.

10. The system of claim 9, wherein:

the at least one SPAD includes a plurality of SPADs configured to receive a SPAD array of the optical output signal;

the SPAD array is divided into a plurality of SPAD sub-arrays, each SPAD sub-array comprising at least one SPAD;

each SPAD subarray is connected to a time gating circuit for sequentially activating and deactivating the SPAD subarrays one at a time;

Each SPAD sub-array is connected to a dedicated counter.

11. The system of any of claims 9 to 10, wherein the at least one SPAD is time gated according to parameters including SPAD activation duration, SPAD deactivation duration, and rate at which activation and deactivation occur; where SPAD activation allows its operation and deactivation allows its charging.

12. The system of any of claims 9 to 11, wherein each optical element is a modulated Micro Ring Resonator (MRR) having:

a drop port for transmitting an optical signal to the first SPAD array; and

a pass-through port for transmitting an optical signal to the second SPAD array;

the respective outputs of the first SPAD array and the second SPAD array are received by the same subtractor.

13. The system of claim 12, wherein the output from each row of at least one optical element is received by a respective subtractor through the first SPAD array and the second SPAD array.

14. The system of claim 13, further comprising a laser source for each subtractor, each laser source modulated by an output of the subtractor.

15. The system of claim 14, further comprising a Wavelength Division Multiplexer (WDM) that receives an optical signal from each modulated laser source and multiplexes the optical signals into a single output.

16. A system for performing optical calculations, comprising:

at least one optical waveguide for propagating an optical input signal;

at least one Superconducting Nanowire Single Photon Detector (SNSPD) for receiving the optical output signal modulated by the at least one optical element.