CN111538368B - Photon information processing chip - Google Patents

Photon information processing chip Download PDF

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CN111538368B
CN111538368B CN202010653113.7A CN202010653113A CN111538368B CN 111538368 B CN111538368 B CN 111538368B CN 202010653113 A CN202010653113 A CN 202010653113A CN 111538368 B CN111538368 B CN 111538368B
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周炆杰
刘晓海
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Otion Intelligent Technology Suzhou Co ltd
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Abstract

The invention discloses a photon information processing chip, which comprises a parallel beam expanding unit, a parallel beam expanding unit and a parallel beam expanding unit, wherein the parallel beam expanding unit is used for dividing an input photon signal into a plurality of beams of photon signals according to different wavelength intervals so as to realize parallel information processing; the weight setting unit is used for respectively setting the weight values of different levels of the intensity values or the phase values of each beam of photon beams with different wavelength intervals after the parallel beam expanding unit; the cross operation unit is used for redistributing the photon beams which are set to be different weight values after the weight setting unit according to different control voltage values; and the photoelectric receiving array is used for photoelectrically converting each photon beam with different wavelength intervals into a multi-path voltage signal array after the propagation channels are redistributed by the cross operation unit, and the four photon beams are manufactured on the same silicon-based material. Therefore, the photon information processing chip greatly improves the information processing capacity, greatly reduces the information processing time and greatly reduces the energy consumption of information processing.

Description

Photon information processing chip
Technical Field
The invention relates to the technical field of chips, in particular to a photon information processing chip.
Background
Information processing technology is a fundamental core technology of the current information age. The fields of artificial intelligence, big data, image recognition and the like need to process massive digital or analog information, so that an ultra-strong information processing technology is needed for supporting.
Information processing techniques used up to now are basically based on electronic information processing techniques, and among them, highly integrated digital electronic computers are the mainstream. However, whether in the fields of artificial intelligence, big data, or image recognition, it is increasingly appreciated that current electronic computer technology has become overwhelmed.
The requirements of the next generation information age can hardly be met based on the current electronic information processing technology, mainly because of two reasons: firstly, in the aspect of hardware, the Moore's law relied on by an electronic computer is reached to the end of the 3nm technology of today, and then the end is reduced to 1nm or less, which is almost contrary to quantum physics, and even then, high power consumption caused by leakage current becomes one of the bottlenecks of the electronic information processing technology; on the other hand, the physical characteristics of the electrons themselves determine the characteristics of a single bit number of an electronic information processing technology, and even if a distributed computing system is adopted, the problem of computing power cannot be fundamentally solved.
Quantum computers seem to be the technological direction to break through the bottlenecks of electronic computers. However, the current quantum computer requires an extremely expensive maintenance system, such as a liquid nitrogen ultra-low temperature cooling system, and the like, and cannot realize a very high computing power at a low cost.
Disclosure of Invention
In order to solve one or more of the above problems, the present application proposes a photonic information processing chip.
According to an aspect of the present application, a photonic information processing chip includes: the parallel beam expanding unit is used for dividing the input photon signals into a plurality of beams of photon signals according to different wavelength intervals so as to realize parallelized information processing; the weight setting unit is used for respectively setting the weight values of different levels of the intensity values or the phase values of each beam of photon beams with different wavelength intervals after the parallel beam expanding unit; the cross operation unit is used for redistributing the photon beams which are set to be different weight values after the weight setting unit according to different control voltage values; the photoelectric receiving array is used for respectively photoelectrically converting each photon beam with different wavelength intervals after the propagation channels are redistributed by the cross operation unit into a multi-path voltage signal array; the parallel beam expanding unit, the weight setting unit, the cross operation unit and the photoelectric receiving array are sequentially connected and manufactured on the same silicon-based material through a chip processing technology.
In some embodiments, the weight setting unit implements the different levels of weight value setting by different driving voltage values applied on optical paths of each of the photon beams of different wavelength intervals. The beneficial effects are as follows: the weight value setting of different levels is realized through the difference of the driving voltage values, and then the multi-order operation can be realized.
In some embodiments, the weight setting unit further implements the different levels of weight value setting by designing a specific structure of the photon beam optical path, the specific structure including one or more combinations of an electro-optical absorption structure, a multi-angle mirror structure, or a two-arm interferometer structure. The beneficial effects are as follows: because the weight setting unit has electro-optical conversion inside, the weight setting of different levels is realized through the difference of specific structures, and then the multi-order operation is realized.
In some embodiments, the parallel beam expanding unit divides the input photon signal into a plurality of photon signals at different wavelength intervals by a grating structure integrated on a silicon-based material. The beneficial effects are as follows: one incident light wave can be divided into a plurality of light waves through the parallel beam expanding unit, and then the parallel beam expanding unit can realize parallel operation.
In some embodiments, the crossing operation unit implements corresponding change of the propagation direction of each photon beam with different wavelength intervals by designing a specific structure of the photon beam optical path and different control voltage values, wherein the specific structure comprises one or more combinations of an electro-optical absorption structure, a multi-angle reflecting mirror structure or a double-arm interferometer structure. The beneficial effects are as follows: the function of the crossover operation which is difficult to be realized in the electronic circuit is realized by the crossover operation unit.
In some embodiments, the photoelectric conversion of the photoreceiving array includes converting the photon signal into a current signal by the photodetector, and converting the current signal into a voltage signal by the transimpedance amplifier. The beneficial effects are as follows: the photoelectric receiving array is processed by parallel circuits.
In some embodiments, the chip processing process comprises: lithography, etching, ion implantation or doping, wafer bonding processes, sputtering or deposition processes.
The beneficial effects are as follows: by utilizing the technical scheme of the application, the photon information processing chip has the advantages that the information processing capacity is greatly improved, the information processing time is greatly reduced, and the information processing energy consumption is greatly reduced.
The concrete description is as follows:
(1) the frequency of the photons can reach 800 GBPS (1 GBPS is equal to processing 1000 Mbits per second), and is improved by more than 30 times compared with the limit frequency of 25GHz of electrons;
(2) in the parallel beam expanding unit, the total number of photon beams with different wavelength intervals can reach more than 50, which means that the capacity of photon information processing can be increased by more than 50 times compared with electronic information processing within the same information processing time;
(3) in the photonic information processing chip of the present application, heat loss occurs only at the unit nodes, and the optical waveguide or the spatial optical transmission channel with almost zero heat loss is used to replace the circuit heat loss in the electronic information processing chip, so that even under the advantageous conditions described in (1) and (2), the heat loss of the photonic information processing chip is only one tenth or less of that of the electronic chip.
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FIG. 1 is a schematic structural diagram of an embodiment of a photonic information processing chip according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment of a photonic information processing chip according to the present application;
fig. 3 is a schematic structural diagram of an embodiment of a photonic information processing chip according to the present application.
In the figure, a parallel beam expanding unit 01; a weight setting unit 02; a crossover operation unit 03; a photoelectric receiving array 04; the feedback control circuit 05.
As shown in fig. 1 to 3, a photonic information processing chip includes: and the parallel beam expanding unit 01 is used for dividing the input photon signals into a plurality of beams of photon signals according to different wavelength intervals so as to realize parallelized information processing. Wherein the wavelength range of the incident photon beam is 1500-1600 nm. And the weight setting unit 02 is configured to perform weight value setting of different levels on the intensity value or the phase value of each photon beam with different wavelength intervals after the parallel beam expanding unit 01. And the intersection operation unit 03 is configured to redistribute the photon beams, which have been set to different weight values after the weight setting unit 02, to propagation channels according to different control voltage values. The photoelectric receiving array 04 is configured to photoelectrically convert each photon beam with different wavelength intervals after the propagation channels are redistributed by the crossover operation unit 03 into a multi-path voltage signal array; the parallel beam expanding unit 01, the weight setting unit 02, the cross operation unit 03 and the photoelectric receiving array 04 are sequentially connected and manufactured on the same silicon-based material through a chip processing technology. The parallel beam expanding unit 01 expands incident photons into n beams of photons, the weight setting unit 02 sets weight values of the n beams of photons, the n beams of photons enter the cross operation unit 03 and then form m beams of photons, and the m beams of photons enter the photoelectric receiving array 04, wherein n and m can be equal or unequal.
Therefore, by using the technical scheme of the application, the information processing capacity of the photon information processing chip is greatly improved, the information processing time is greatly reduced, and the energy consumption of information processing is greatly reduced. The concrete description is as follows: (1) the frequency of the photons can reach 800 GBPS (1 GBPS is equal to processing 1000 Mbits per second), and is improved by more than 30 times compared with the limit frequency of 25GHz of electrons; (2) in the parallel beam expanding unit 01, the total number of photon beams with different wavelength intervals can reach more than 50, which means that the capacity of photon information processing can be increased by more than 50 times compared with electronic information processing within the same information processing time; (3) in the photonic information processing chip shown in fig. 1, heat loss occurs only at the unit nodes, and the optical waveguide or the spatial optical transmission channel with almost zero heat loss is used instead of the circuit heat loss in the electronic information processing chip, so that the heat loss of the photonic information processing chip is only one tenth or less of that of the electronic chip even under the advantageous conditions of (1) and (2).
In some embodiments, the weight setting unit 02 implements the different levels of weight value setting by applying different driving voltage values on the optical path of each photon beam with different wavelength intervals. The weight setting unit 02 also realizes the setting of the weight values of the different levels by the design of the specific structure of the photon beam light path. Specifically, the weight setting unit 02 is configured to set intensity values or phase values of each of the photon beams with different wavelength intervals after the parallel beam expanding unit 01 at different levels respectively, which are achieved by different driving voltage values applied to optical paths of each of the photon beams with different wavelength intervals, and through design of a specific structure of the photon beam optical path, the different driving voltage values may cause corresponding changes to the intensity values or phase values of the photon beams on the optical path, where the intensity values or phase values at different levels are referred to as weight values. And the specific structure can be one or more combinations of electro-optical absorption structure, multi-angle reflecting mirror structure and double-arm interferometer structure. The electro-optical absorption structure and the multi-angle reflecting mirror surface influence the intensity value, the double-arm interferometer structure influences the phase value, and the structures can be combined and designed according to specific requirements, so that the specific multi-order operation purpose is realized.
In some embodiments, the parallel beam expanding unit 01 divides the input photon signal into a plurality of photon signals at different wavelength intervals by a grating structure integrated on a silicon-based material. Specifically, the incident light beams are diffracted by the grating structure and then separated from each other to realize beam expansion of the light, that is, the light beams are separated into a plurality of photon signals by the grating structure, and then the parallel beam expansion unit 01 can realize parallel operation.
In some embodiments, the intersection operation unit 03 implements corresponding change of the propagation direction of each photon beam with different wavelength intervals by designing a specific structure of the photon beam optical path and different control voltage values. The crossover operation unit 03 realizes a crossover operation function that is difficult to realize in an electronic circuit.
In some embodiments, the particular structure comprises one or more combinations of an electro-optical absorbing structure, a multi-angle mirror structure, and a dual-arm interferometer structure. Different specific structures are selected according to specific purposes, and further multi-order operation can be realized.
In some embodiments, the photoelectric conversion of the photoreceiving array 04 includes converting the photon signal into a current signal by a photodetector, and converting the current signal into a voltage signal by a transimpedance amplifier.
In some embodiments, the chip processing process comprises: lithography, etching, ion implantation or doping, wafer bonding processes, sputtering or deposition processes.
In order to explain the technical solution of the present application in more detail, the following is exemplified:
EXAMPLE 1 Photonic digital processor chip
As shown in fig. 1 and fig. 2, the parallel beam expanding unit 01 divides the incident optical wavelets into a plurality of specific channels according to different wavelengths, where the number of the specific channels is n, and then n beams of photons are formed, where n =50 specific channels in this embodiment may be implemented by a grating. In order to make the manufacturing process of the parallel beam expanding unit 01 compatible with the silicon-based chip processing process, nitrogen and oxygen can be doped on the silicon substrate by a magnetron sputtering method, so that the optical loss of the photon beam in the optical waveguide of the photon beam is less than 0.5dB/cm, and in order to realize that a specific wavelength propagates along a specific channel by the interference effect of light, the width interval between the optical waveguides of different adjacent channels, namely the photoetching precision d, must be accurately controlled. For example, if n =50, then d is about 10nm, a 10nm lithography process that is currently mature in the Integrated Circuit (IC) industry can be employed.
The weight setting unit 02 sets the level of the intensity or phase of the photon beam by applying a different magnitude of driving voltage to each photon beam. Since the scheme is applied by a digital processor, on one hand, only two-value characteristics of binary digits of 'on or off' are required to be realized; on the other hand, it is required that the switching speed is as fast as possible. Therefore, a germanium element with a certain concentration is doped through a typical vapor phase epitaxial growth process of silicon chip processing, so that a double-arm interferometer structure controlled by a germanium electrode is realized, namely in the embodiment, a specific structure of an optical path of an optical photon beam adopts a double-arm interferometer structure, namely a Mach-Zehnder interferometer, so that under the action of voltage, the electro-optic effect of metal germanium can rapidly change the refractive index of each switch waveguide, thereby changing the interference phase, finally realizing a rapid switching function and effectively improving the switching speed. The switching rate achievable by current germanium doping processes can reach 28 GBPS.
For photonic digital processor applications, the present embodiment simplifies the interleaving unit 03 directly for simplicity of design and reduced power consumption. Meanwhile, the photon beams with different wavelength intervals after passing through the weight setting unit 02 are directly introduced into the photoelectric receiving array 04 through the optical waveguide, at this time, a mach-zehnder interferometer is also selected as a specific structure of the cross operation unit 03, but the mach-zehnder interferometer does not need electricity here, as shown in fig. 2, the incident photons are expanded into n beams of photons by the parallel beam expanding unit 01, after the weight setting unit 02 sets the weight values of the n beams of photons, the n beams of photons enter the cross operation unit 03 to form m beams of photons, and then the m beams of photons enter the photoelectric receiving array 04, wherein n and m are equal.
It can be seen that, in the present embodiment, the specific configuration of the photon beam optical path in the weight setting unit 02 and the crossover operation unit 03 is a double-arm interferometer, that is, a mach-zehnder interferometer.
Example 2 Photonic Artificial Intelligence computing chip
As shown in fig. 1 and 3, the parallel beam expanding unit 01 divides incident optical wavelets into n specific channels with a wavelength range of 1500nm to 1600nm according to different wavelengths, and the number of the specific channels is n, so as to form n beams of photons, where n =50 specific channels in this embodiment, in order to make the manufacturing process of the parallel beam expanding unit 01 compatible with the processing process of a silicon-based chip, we dope nitrogen and oxygen on a silicon substrate by a magnetron sputtering method, so that the optical loss of the photon beams in the optical waveguide thereof is less than 0.5 dB/cm; in order to realize propagation of a specific wavelength along a specific channel by the interference effect of light, it is necessary to precisely control the width interval between the optical waveguides of adjacent different channels, i.e., the precision d of photolithography. For example, if n =50, then d is about 10nm, a 10nm lithography process that is currently mature in the Integrated Circuit (IC) industry can be employed.
The weight setting unit 02 sets the level of the intensity or phase of the photon beam by applying a different magnitude of driving voltage to each photon beam. For the artificial intelligence algorithm, it is necessary to set weighted values of as many levels as possible to implement more accurate "learning and memory" parameters, and for this reason, the specific structure of the photon beam optical path in this embodiment adopts an electro-optical absorption structure, which is specifically implemented as follows: the silicon substrate is doped with the mixed composition of indium and phosphorus first because the absorption edge curve of indium phosphide (InP) for light waves is exactly within the wavelength range, and the light absorption edge curve of the InP electrode is shifted in the wavelength direction by applying different driving voltage values to the InP electrode according to the physical principle, so that the absorption efficiency of each photon beam is different by applying different driving voltage values to the InP electrode of the optical waveguide of each photon beam with different wavelength intervals, and thus the beam intensity of the photon beam finally passing through is different, and the variation value of the beam intensity of the photon beam with different wavelength intervals can be sensitively recognized by the back-end photo-receiving array 04 (the light intensity discrimination accuracy of the photo-detector can be better than 0.2 dB). Thus, by the light intensity accurate characterization of the electro-optical absorption effect, we can achieve the calculation of a Hopfield neural network of n =50, i.e. equivalent to 50 neurons.
The crossover operation unit 03 serves as a neuron activation function of the Hopfield neural network, and the specific structure in the crossover operation unit 03 in this embodiment adopts a multi-angle mirror structure. To this end we can consider the most basic linear saturation activation function: that is, the relationship between the input value X and the output value Y of the neuron is:
Figure 702980DEST_PATH_IMAGE001
to achieve such large-scale matrix switching, an array of 1 × 50 micro mirrors is formed by a deep etching process of silicon processing, and a specific mirror is rotated by a specific angular range by applying an electrostatic voltage value satisfying a functional expression (×) to spatially redistribute photon beams of a specific channel to a designated different exit channel.
The working principle of the photon artificial intelligence operation chip of the embodiment is as follows: as shown in fig. 1 and fig. 3, on the basis of the frame diagram of the photon information processing chip shown in fig. 1, that is, the parallel beam expanding unit 01 expands incident photons into n beams of photons, and after the weight setting unit 02 sets the weight values of the n beams of photons, the n beams of photons enter the intersection operation unit 03 to form m beams of photons, and then the m beams of photons enter the photo-receiving array 04, where n and m are equal. The multi-path voltage signal array at the output end is processed by an external feedback control circuit 05 and then directly fed back to the weight setting unit 02. Assuming that the neuron weight matrix value of the weight setting unit 02 memorized and stored in the feedback control circuit 05 is W, the array-type multi-path voltage value at the output end corresponds to a vector Y of n × 1 after each learning, and the number of states memorized in the network is M, then after each learning, the neuron weight matrix value memorized by the Hopfield neural network is:
Figure 56600DEST_PATH_IMAGE002
wherein, I represents the unit matrix of n × n, and the superscript T represents the matrix transposition.
Compared with an electronic computing chip with equal computation amount, the photon information processing chip has the advantage that the computation speed can be improved by more than 30 times, but the electrical power consumption is only 1/10 of the latter, which is caused by adopting an optical path with almost zero heat loss to replace the heat loss of a circuit with huge number of intersections.
What has been described above are merely some embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the inventive concept thereof, and these changes and modifications can be made without departing from the spirit and scope of the invention.

Claims (6)

1. A photonic information processing chip, comprising:
the parallel beam expanding unit (01) is used for dividing the input photon signals into a plurality of beams of photon signals according to different wavelength intervals so as to realize parallelized information processing;
the weight setting unit (02) is used for respectively carrying out weight value setting of different levels on the intensity value or the phase value of each photon beam with different wavelength intervals after the parallel beam expanding unit (01);
the cross operation unit (03) is used for redistributing the photon beams which are set to different weight values after the weight setting unit (02) to propagation channels according to different control voltage values;
the photoelectric receiving array (04) is used for photoelectrically converting each photon beam with different wavelength intervals into a multi-path voltage signal array after the propagation channels are redistributed by the cross operation unit (03);
the parallel beam expanding unit (01), the weight setting unit (02), the cross operation unit (03) and the photoelectric receiving array (04) are sequentially connected and are manufactured on the same silicon-based material through a chip processing technology;
the weight setting unit (02) realizes the setting of the weight values of different levels by different driving voltage values applied to the optical path of each photon beam with different wavelength intervals.
2. A photonic information processing chip according to claim 1, wherein said weight setting unit (02) further implements said different levels of weight value setting by design of a specific structure of a photonic beam optical path, said specific structure including one or more combinations of an electro-optical absorption structure, a multi-angle mirror structure, or a two-arm interferometer structure.
3. A photonic information processing chip according to claim 1, wherein said parallel beam expanding unit (01) divides the input photonic signal into multiple photonic signals at different wavelength intervals by means of a grating structure integrated on a silicon based material.
4. The photonic information processing chip according to claim 1, wherein the crossover operation unit (03) implements a corresponding change in the propagation direction of each photon beam with different wavelength intervals by designing a specific structure of the photon beam path, wherein the specific structure comprises one or more combinations of an electro-optical absorption structure, a multi-angle mirror structure or a dual-arm interferometer structure.
5. A photonic information processing chip according to claim 1, wherein the photoelectric conversion of the photo-receiving array (04) comprises converting a photon signal into a current signal by a photodetector, and converting the current signal into a voltage signal by a transimpedance amplifier.
6. The photonic information processing chip of claim 1, wherein the chip processing process comprises: lithography, etching, ion implantation or doping, wafer bonding processes, sputtering or deposition processes.
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