CN116736088B - Chip testing method for assisting post-silicon test - Google Patents
Chip testing method for assisting post-silicon test Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 123
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 75
- 239000010703 silicon Substances 0.000 title claims abstract description 75
- 238000004088 simulation Methods 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000006243 chemical reaction Methods 0.000 claims abstract description 13
- 230000006870 function Effects 0.000 claims description 50
- 238000012795 verification Methods 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000005856 abnormality Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 6
- 238000012942 design verification Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
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- 101150098958 CMD1 gene Proteins 0.000 description 2
- 101100382321 Caenorhabditis elegans cal-1 gene Proteins 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The application relates to the field of integrated circuit testing, and discloses a chip testing method for assisting in post-silicon testing, which can greatly reduce the post-silicon testing difficulty. The method comprises the following steps: and acquiring the mode description text of the item. And calling a functional simulation template through a script generator to generate a functional simulation use case based on the mode description text. And carrying out the function simulation of the register conversion stage circuit by using the function simulation case, correcting the mode description text if the function simulation is not passed, and generating the register conversion stage circuit simulation case again to carry out the function simulation until the function simulation is passed. And calling the post-silicon test template by using the mode description text through the functional simulation through a script generator to generate a post-silicon test case which is homologous to the functional simulation case. And performing post-silicon testing by using the post-silicon test case.
Description
Technical Field
The application relates to the field of integrated circuit testing, in particular to a chip testing method for assisting in post-silicon testing.
Background
This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Because the silicon chip cannot directly observe the internal signals, the configuration information needs multiple iterations to succeed, DV (Design Verification, function verification, design front-end simulation) and the post-silicon test programming language difference, attention granularity and angle are different, which may cause that the test case of the design verification cannot be directly used for the post-silicon test, and the design verification can observe any internal signals in RTL (Register-transfer level) simulation, and timely find and correct the error configuration or error configuration flow.
Disclosure of Invention
The application aims to provide a chip testing method for assisting in testing after silicon, which can greatly reduce the difficulty of testing after silicon and save the cost of testing time.
The application discloses a chip testing method for assisting in post-silicon testing, which comprises the following steps:
acquiring a mode description text of an item;
based on the mode description text, a function simulation template is called by a script generator to generate a function simulation use case;
performing register conversion stage circuit function simulation by using the function simulation case, correcting the mode description text if the function simulation is not passed, generating the register conversion stage circuit simulation case again, and performing the function simulation until the function simulation is passed;
calling a post-silicon test template by using the mode description text through functional simulation through the script generator to generate a post-silicon test case which is homologous to the functional simulation case;
post-silicon testing was performed using the post-silicon test case.
In a preferred embodiment, the method further comprises:
acquiring a similar mode description text of a similar item;
based on the similar mode description text, calling the function simulation template through a script generator to generate the function simulation case;
using the function simulation case to perform register conversion stage circuit function simulation, if the function simulation does not pass, correcting the similar mode description text, and generating the register conversion stage circuit simulation case again to perform the function simulation until the function simulation passes;
using the similar mode description text through the function simulation to call a post-silicon test template through the script generator to generate a post-silicon test case which is homologous to the function simulation case;
post-silicon testing was performed using the post-silicon test case.
In a preferred embodiment, the method further comprises:
the script generator finds out a corresponding label and a corresponding library file according to the information provided by the mode description text, wherein the library file comprises atomic operation library files of each team;
and the script generator translates the corresponding instruction in the mode description text into corresponding operation and generates a corresponding application for each team to test.
In a preferred embodiment, the descriptive text includes an instruction set that is combined into a configuration flow for all chips.
In a preferred embodiment, the descriptive text is configured to describe the configuration flow in a base language and a text profile.
In a preferred embodiment, the post-silicon test team provides the pattern description text, and the functional verification team generates test cases according to the pattern description text and performs verification in a verification environment.
In a preferred embodiment, the functional verification team writes the mode description text according to the test scene provided by the post-silicon test team, generates a test case, and performs verification in a verification environment.
In a preferred embodiment, the functional simulation includes observing signals internal to the register transfer stage and correcting a misconfiguration or misconfiguration flow.
In a preferred embodiment, the items use separate text profiles.
In a preferred embodiment, the descriptive text includes item correspondence tags and directories, test case names, and tasks composed of atomic operations.
The application also discloses a computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the steps in the method as described hereinbefore.
In the embodiment of the application, the description text is used for generating the functional simulation case, the functional simulation is carried out by using the functional simulation case, if the verification fails, the description text is modified, the functional simulation case simulation is continuously generated until the simulation result accords with the expectation, the description text corresponding to the description text with successful simulation is used for generating the post-silicon test case, and compared with the post-silicon test, the functional simulation has more observation signals, and the debugging is easier.
Further, due to the homology of the functional simulation case and the post-silicon test case, the case for post-silicon test can be ensured to pass the functional simulation, and the probability of error configuration and error configuration flow is reduced;
further, for verification of the close item, a description text of the close item can be generated for functional simulation, and the description text of the close item can be multiplexed for the close item.
The silicon post-test difficulty is greatly higher than that of the functional simulation, because the functional simulation can observe any intermediate result at a small cost and is easy to debug, and when the silicon post-test is out of question, the problem can be the hardware problem or the problem of the test case, and the possibility of the problem of the test case can be greatly reduced by the method.
The technical features disclosed in the above summary, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various novel technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
FIG. 1 is a schematic flow diagram according to one embodiment of the application;
FIG. 2 is a schematic flow diagram according to one embodiment of the application;
FIG. 3 is a schematic flow diagram according to one embodiment of the application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
Description of the partial concepts:
functional verification, also known as functional verification test. In chip testing, the front-end design uses the hardware description language Verilog to describe and implement the module functions in codes, namely the functions required by the chip are described by a machine-understandable language, and RTL codes are formed. The function verification is mainly responsible for verifying whether the RTL code issued by the front-end design engineer really realizes the function required by the chip.
And (3) after silicon verification: after flow sheet, the sample is subjected to validation in a real environment, referred to as post-silicon validation. In post-silicon verification, the chip is configured using a software tool on a computer and test code is downloaded into the chip for various tests.
Atomic operation: refers to operations that are not interrupted by the thread scheduling mechanism; once this operation starts, it runs to the end without any intermediate operation of switching to another thread.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The application relates to a chip testing method for assisting in post-silicon testing, the flow of which is shown in figure 1, the method comprises the following steps:
in step 101, a pattern description text of an item is acquired.
In step 102, a functional simulation template is invoked by a script generator to generate a functional simulation use case based on the pattern description text.
In step 103, the script generator finds the corresponding tag and finds the corresponding library file according to the information provided by the pattern description text, the library file including the atomic operation library file of each team.
In step 104, the register conversion stage circuit function simulation is performed using the function simulation use case, and if the function simulation is not passed, the pattern description text is corrected until the function simulation is passed.
In step 105, the script generator translates the corresponding instructions in the pattern description text into corresponding operations and generates corresponding applications for testing by the various teams.
In step 106, the post-silicon test template is invoked by the script generator using the pattern description text through the functional simulation to generate a post-silicon test case that is homologous to the functional simulation case.
In step 107, a post-silicon test is performed using the post-silicon test case.
In an alternative embodiment, as shown in fig. 2, the method may further include:
in step 201, a similar mode description text of a similar item is acquired;
in step 202, based on the similar mode description text, a function simulation template is called by a script generator to generate a function simulation use case;
in step 203, performing register conversion stage circuit function simulation by using a function simulation case, and correcting the similar mode description text until the function simulation passes if the function simulation does not pass;
in step 204, using the similar mode description text through the functional simulation to call the post-silicon test template through the script generator to generate a post-silicon test case homologous to the functional simulation case;
in step 205, a post-silicon test is performed using the post-silicon test case.
In an alternative embodiment, the descriptive text may include a set of instructions that are combined into a configuration flow for all chips.
In an alternative embodiment, the descriptive text may be configured to describe the configuration flow in a base language and a text configuration file.
In an alternative embodiment, the functional simulation may include observing signals internal to the register conversion stage and correcting a misconfiguration or misconfiguration flow.
In an alternative embodiment, the items may use separate text profiles.
In an alternative embodiment, the descriptive text includes item correspondence tags and directories, test case names, and tasks consisting of atomic operations.
In an alternative embodiment, the post-silicon test team provides pattern description text, and the functional verification team generates test cases based on the pattern description text for verification in a verification environment. And modifying the mode description text, and generating a final post-silicon test case for a post-silicon test team through a script generator.
In an alternative embodiment, the functional verification team provides the pattern description text according to the test scenario provided by the post-silicon test team, generates test cases, and performs verification in the verification environment. And generating a final post-silicon test case for a post-silicon test team through a script generator.
In order to better understand the technical solution of the present application, the following description is given with reference to a specific example, in which details are listed mainly for the purpose of understanding, and are not to be construed as limiting the scope of protection of the present application.
And the script generator generates a post-silicon test case for the test team to use according to the mode description text and the basic operation (atomic operation template) of the bottommost layer provided by the design verification and test team, wherein the post-silicon test case is generated by correcting the mode description text until the functional simulation passes if the functional simulation does not pass.
The modes of operation may include the following two modes:
1) The post-silicon test team provides a mode description text, the verification team generates a verification case according to the mode description text, runs in a verification environment, modifies the mode description text, and generates a final post-silicon test case to the test team by using a script generator;
2) The functional verification team writes the mode description text according to the test scene provided by the test team, generates a verification case, runs in the verification environment, and generates a final post-silicon test case to the test team by utilizing a script generator.
In addition, as shown in fig. 3, the pattern description text is still reusable for different items. For the a-item, n pattern description texts may be generated: pattern description text 0-pattern description text n, for the B item, n pattern description texts corresponding to the a item may be generated: pattern description text 0-Pattern description text n-. The pattern description text of the A project and the B project can be input into the same script generator, so that the functional simulation case and the post-silicon test case are generated.
With respect to instruction sets, base instructions and extend instructions may be included.
The base instructions may include, but are not limited to, the following, which may be combined or varied as desired:
1. writing single reg single pen data:
WREG_ADDR_<addr>_DATA_<data>
2. reading a single reg returns a single pen of data
RREG_ADDR_<addr>
3. Write a single reg with mask:
WREG_ADDR_<addr>_DATA_<data>_MASK_<mask>
only changing mask bits to 1 corresponding bits
4. Reading a single reg and comparing (data & mask), which does not conform to the expected output specific character (report exception):
RREG_ADDR_<addr>_DATA_<data>_MASK_<mask>
5. the reg is circularly read until a specific state (data & mask) is read, and the next step is executed
POLLING_ADDR_<addr>_DATA_<data>_MASK_<mask>
6. Waiting for a specific delay
WAIT_<delay>
delay is a 10-ary integer + unit (s/ms/us/ns/ps)
7. Waiting for a signal rising edge in a specific time, and if not waiting for the signal rising edge to reach a specific character string (reporting abnormality)
1) Wait_pos_pad > (unlimited time until waiting)
2）WAIT_POS_<pad>_TIME_<time>
Pad corresponds to chip PAD, path corresponds to RTL signal path, and time is an integer of 10 system
8. Waiting for a signal falling edge in a specific time, and if not waiting for the signal falling edge to reach, outputting a specific character string (reporting abnormality)
1) Wait_neg_ < pad > (not limited time until waiting)
2）WAIT_NEG_<pad>_TIME_<time>
time is a number + unit, such as 20s,20ms,20us,20ns,20ps
9. Waiting for a signal to be at a specific level (0/1), and if the signal does not reach the specific level, outputting a specific character string (reporting abnormality)
1) Wait_lvl_ < pad > _ logic_ <0/1> (unlimited time until waiting until
2) Wait_lvl_ < pad > _ logic_ <0/1> _ time_ < TIME > (after TIME, check if the pad signal becomes value)
time is a number + unit, such as 20s,20ms,20us,20ns,20ps
10. Waiting for a signal to be equal to a specific value (floating point number), and if the signal does not reach the specific value, outputting a specific character string (reporting abnormality)
1) Wait_lvl_ < pad > _ value_eq_ < VALUE > _ abs_ < ABS > (without time limitation until waiting until
2）WAIT_LVL_<pad>_VALUE_EQ_<value>_ABS_<abs>_TIME_<time>
After a time (time is a number + unit, such as 20s,20ms,20us,20ns,20 ps), it is queried whether the pad signal becomes a value, and the allowable error is abs
11. Waiting for a signal to be larger than a specific value (floating point number), and if the signal does not reach the specific value, outputting a specific character string (reporting abnormality)
1) Wait_lvl_ < pad > _ value_lg_ < VALUE > _ abs_ < ABS > (without time limitation until waiting until
2）WAIT_LVL_<pad>_VALUE_LG_<value>_ABS_<abs>_TIME_<time>
After a time (time is a number + unit, such as 20s,20ms,20us,20ns,20 ps), it is queried whether the pad signal is greater than a value
12. Waiting for a signal to be larger than a specific value (floating point number), and if the signal does not reach the specific value, outputting a specific character string (reporting abnormality)
1) Wait_lvl_ < pad > _ value_sm_ < VALUE > _ abs_ < ABS > (without time limitation until waiting until
2）WAIT_LVL_<pad>_VALUE_SM_<value>_ABS_<abs>_TIME_<time>
After a time (time is a number + unit, such as 20s,20ms,20us,20ns,20 ps), it is queried whether the pad signal is greater than a value
13. Writing a single cmd
WCMD_<cmd>
The expansion instructions may include, but are not limited to, the following, which may be combined or varied as desired:
1. writing a single reg of data: (same reg multiple configuration)
WREG_ADDR_<addr>_DATA_<data0>_<data1>_<data2>…<datan>:
Note that: can be decomposed into instruction 1:
WREG_ADDR_<addr>_DATA_<data0>
WREG_ADDR_<addr>_DATA_<data1>
WREG_ADDR_<addr>_DATA_<data2>
WREG_ADDR_<addr>_DATA_<data3>
…
WREG_ADDR_<addr>_DATA_<datan>
2. writing a plurality of reg single strokes of data: (same data for multiple reg configurations)
WREG_ADDR_<addr0>_<addr1>…<addrn>_DATA_<data>：
Note that: can be decomposed into instruction 1:
WREG_ADDR_<addr0>_DATA_<data>
WREG_ADDR_<addr1>_DATA_<data>
WREG_ADDR_<addr2>_DATA_<data>
WREG_ADDR_<addr3>_DATA_<data>
…
WREG_ADDR_<addrn>_DATA_<data>
3. writing a plurality of reg multi-pen data: (multiple reg configuration with different data)
WREG_ADDR_<addr0>_<addr1>…<addrn>_DATA_<data0>_<data1>…<addrn>
Note that: can be decomposed into instruction 1:
WREG_ADDR_<addr0>_DATA_<data0>
WREG_ADDR_<addr1>_DATA_<data1>
WREG_ADDR_<addr2>_DATA_<data2>
WREG_ADDR_<addr3>_DATA_<data3>
…
WREG_ADDR_<addrn>_DATA_<datan>
4. writing multiple cmd
WCMD_<cmd0>_<cmd1>_<cmd2>…<cmdn>
Note that: can be broken down into instruction 8:
WCMD_<cmd0>
WCMD_<cmd1>
WCMD_<cmd2>
…
WCMD_<cmdn>
5. writing multiple reg multi-pen data, BURST operation: (multiple reg configuration with different data)
BWREG_ADDR_<addr0>_DATA_<data0>_<data1>…<addrn>
Note that: it can be equivalently:
WREG_ADDR_<addr0>_DATA_<data0>
WREG_ADDR_<addr0+1*offset>_DATA_<data1>
WREG_ADDR_<addr2+2*offset>_DATA_<data2>
WREG_ADDR_<addr3+3*offset>_DATA_<data3>
…
WREG_ADDR_<addrn+n*offset>_DATA_<datan>
offset is the Offset of 2 adjacent regs
6. Multiple regs are read and compared (data & mask), BURST operation, not conforming to expected output specific characters (exception reporting):
BRREG_ADDR_<addr>_DATA_<data0>_<data1>…<datan>…MASK_<mask0>_<mask1>…<maskn>
note that can be equivalently:
RREG_ADDR_<addr>_DATA_<data0>_MASK_<mask0>
RREG_ADDR_<addr+1*offset>_DATA_<data1>_MASK_<mask1>
RREG_ADDR_<addr+2*offset>_DATA_<data2>_MASK_<mask2>
…
RREG_ADDR_<addr+n*offset>_DATA_<datan>_MASK_<maskn>
offset is the Offset of 2 adjacent regs
Alternatively, the pattern description text may be composed of 3 parts:
1) Verifying/testing team project corresponding labels and catalogs;
2) Test case name;
3) Atomic operations constitute tasks.
Specifically, the pattern description text may include, but is not limited to, the following:
DV_TAG= < project0_v3.0 >// verify atomic operation library signature, which contains instances of verify platform basic instructions and extended instructions
DV_PATH=/project/dac_xxx/xxxxx/dv
Test_tag= < project0_v2.1 >// TEST atomic operation library label, which contains TEST platform basic instruction and extension instruction examples
test_path=/project/dac_xxx/xxxxx/TEST// correspondence
Case= < dac ch1_output_test >// use CASE name
MAIN={
WAIT 200us chip power-up/WAIT 200us
The polling_addr_8' h01_data_16' h0001_mask_16' hfff;/cycle reads the 8' h01 status register reg until 32' h0001 is read, if this status is read, indicating that the chip has been status in line with expectations
WREG_ADDR_8'h02_DATA_16' h5a5a;// configure 8'h02 reg (ch 1 data register) to be 16' h5a5a
RREG_ADDR_8' h02_DATA_16' h5a5a_MASK_16' hfff;// configure 8' h02 reg (ch 1 data register) to be 16' h5a5a
Wait_lvl_dac_out1_value_eq_2.5v_abs_0.1v_time_20us;// 20us checks if the output voltage of dac_out1pad is 2.5v and the error enable is 0.1v
WAIT 100 us;// WAIT 100us
}
In an alternative embodiment, the script generator may find the corresponding tag according to the information provided by the pattern description text, so as to find the library file, and verify the atomic operation task function of each team after functional verification/silicon is included in the library file, and the script generator translates and assembles the corresponding instruction in the main function corresponding to the test case according to the library file to generate the corresponding test case, and each team takes the test case, compiles and runs, so that the homologous operation can be obtained.
In an alternative embodiment, the functional simulation use cases generated from the pattern description text may include, but are not limited to, the following:
`ifndef DAC_CH1_OUTPUT_TEST__SV
`define DAC_CH1_OUTPUT_TEST__SV
class dac_ch1_output_test extends base_test;
`uvm_component_utils(dac_ch1_output_test)
extern function new(string name = "dac_ch1_output_test", uvm_component parent = null);
extern task do_test();
endclass
function dac_ch1_output_test::new(string name = "dac_ch1_output_test", uvm_component parent = null);
super.new(name, parent);
endfunction
task dac_ch1_output_test::do_test();
// WAIT_200_us
begin
#200us;
end
// POLLING_ADDR_8’h01_DATA_16’h0001_MASK_16’hffff
begin
bit [15:0] wdata;
bit [15:0] rdata;
bit [15:0] exp_data;
bit [15:0] mask;
bit [7:0] addr;
addr = 8'h01;
mask = 16'hffff;
exp_data = 16'h00001;
while((rdata&mask)!=exp_data)begin
read_reg(addr,rdata);
end
end
// WREG_ADDR_8’h02_DATA_16’h5a5a;
begin
bit [15:0] wdata;
bit [7:0] addr;
wdata=16'h5a5a;
addr=8'h02;
write_reg(addr,wdata);
end
// RREG_ADDR_8’h02_DATA_16’h5a5a_MASK_16’hffff
begin
bit [15:0] wdata;
bit [15:0] rdata;
bit [15:0] exp_data;
bit [15:0] mask;
bit [7:0] addr;
addr = 8’h02;
wdata=16'h5a5a;
read_reg (addr,rdata);
if((rdata&mask)!=wdata)
`uvm_error("",$psprintf("exp_data=0x%h while rdata=0x%h",exp_data,rdata))
end
// WAIT_LVL_DAC_OUT1 _VALUE_EQ_2.5v_ABS_0.1v_TIME_20us
begin
real act = 0.0;
real exp = 2.5;
real toller=0.1;
#20us;
act = hdl_top.DAC_OUT1；
if(abs(act,exp)>toller)
`uvm_error("",$psprintf("exp =%.8f act=%.8f toller=%.8f",exp,act,toller))
end
// WAIT_100_us
begin
#100us;
end
endtask
`endif
in an alternative embodiment, the post-silicon test cases generated from the pattern description text may include, but are not limited to, the following:
main(){
uint16_t rdata;
float out1;
HARD_Init();
// WAIT_200_us
Delayus(200);
// POLLING_ADDR_8’h01_DATA_16’h0001_MASK_16’hffff
rdata= DAC_RREG(0x01);
while(rdata&0xffff != 0x5a5a){
rdata= DAC_RREG(0x01);
Delayus(1);
}
// WREG_ADDR_8’h02_DATA_16’h5a5a;
DAC_WREG(0x02,0x5a5a);
// RREG_ADDR_8’h02_DATA_16’h5a5a_MASK_16’hffff
rdata= DAC_RREG(0x02);
if(rdata&0xffff != 0x5a5a){
print_log(“Errror rdata is not match wdata”);//print to teriminal
}
// WAIT_LVL_DAC_OUT1 _VALUE_EQ_2.5v_ABS_0.1v_TIME_20us
Delayus(20);
out1 = OUT_measure(1);// run ADC to cature OUT, and convert to float data
if(out1<(2.5-0.1) ){
print_log(“Errror! OUT=%.8f not as expected!”,out1);//print to teriminal
}
// WAIT_100_us
Delayus(100);
…
}
…
accordingly, embodiments of the present application also provide a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the method embodiments of the present application. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium which can be used to store information that can be accessed by a computing device. Computer-readable storage media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It is noted that in the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
The sequence numbers used in describing the steps of the method do not themselves constitute any limitation on the order of the steps. For example, the step with the larger sequence number is not necessarily performed after the step with the smaller sequence number, but the step with the larger sequence number may be performed first and then the step with the smaller sequence number may be performed in parallel, as long as the order of execution is reasonable for those skilled in the art. As another example, steps having consecutive numbered numbers (e.g., step 101, step 102, step 103, etc.) are not limiting as other steps may be performed therebetween, e.g., there may be other steps between step 101 and step 102.
This specification includes combinations of the various embodiments described herein. Reference to an embodiment alone (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All references mentioned in this specification are to be considered as being included in the disclosure of the application in its entirety so as to be applicable as a basis for modification when necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims (7)
1. A method for facilitating post-silicon testing of a chip, comprising:
acquiring a mode description text of an item, wherein the mode description text comprises a label and a catalog corresponding to the item, a test case name and a task consisting of atomic operation;
based on the mode description text, a functional simulation template is called by a script generator to generate a functional simulation use case, wherein the script generator finds a corresponding tag and a corresponding library file according to information provided by the mode description text, the library file comprises atomic operation library files of each team, and the script generator translates a corresponding instruction in the mode description text into a corresponding operation according to the library file and generates the corresponding functional simulation use case;
performing register conversion stage circuit function simulation by using the function simulation case, correcting the mode description text if the function simulation is not passed, generating the register conversion stage circuit simulation case again, and performing the function simulation until the function simulation is passed;
calling a post-silicon test template by using the mode description text through functional simulation through the script generator to generate a post-silicon test case which is homologous to the functional simulation case;
post-silicon testing was performed using the post-silicon test case.
2. The method for facilitating post-silicon testing of claim 1, further comprising:
acquiring a similar mode description text of a similar item;
based on the similar mode description text, calling the function simulation template through a script generator to generate the function simulation case;
using the function simulation case to perform register conversion stage circuit function simulation, if the function simulation does not pass, correcting the similar mode description text, and generating the register conversion stage circuit simulation case again to perform the function simulation until the function simulation passes;
using the similar mode description text through the function simulation to call a post-silicon test template through the script generator to generate a post-silicon test case which is homologous to the function simulation case;
post-silicon testing was performed using the post-silicon test case.
3. The method for assisting post-silicon testing according to claim 1, wherein a post-silicon testing team provides the pattern description text, and a functional verification team generates test cases according to the pattern description text, and performs verification in a verification environment;
and modifying the mode description text until the functional simulation passes, and calling a post-silicon test template through the script generator by using the mode description text passing the functional simulation to generate a post-silicon test case homologous to the functional simulation case for the post-silicon test team to use.
4. The method for facilitating post-silicon testing of claim 1, wherein the descriptive text includes a set of instructions combined into a configuration flow for all chips.
5. The method for facilitating post-silicon testing of claim 1, wherein the descriptive text is configured to describe a configuration flow in a base language and a text configuration file.
6. The method for facilitating post-silicon testing as recited in claim 1, wherein the items use separate text profiles.
7. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the steps in the method of any one of claims 1 to 6.
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