CN116705906A - Silicon wafer texturing process - Google Patents

Silicon wafer texturing process Download PDF

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Publication number
CN116705906A
CN116705906A CN202310681920.3A CN202310681920A CN116705906A CN 116705906 A CN116705906 A CN 116705906A CN 202310681920 A CN202310681920 A CN 202310681920A CN 116705906 A CN116705906 A CN 116705906A
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China
Prior art keywords
silicon wafer
texturing
mask
etching
silicon
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Pending
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CN202310681920.3A
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Chinese (zh)
Inventor
赵彩霞
张波
赵军龙
梁玲
杨旭彪
吕涛
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Shanxi Luan Solar Energy Technology Co Ltd
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Shanxi Luan Solar Energy Technology Co Ltd
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Priority to CN202310681920.3A priority Critical patent/CN116705906A/en
Publication of CN116705906A publication Critical patent/CN116705906A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)

Abstract

The invention relates to the field of solar cell generation, in particular to a silicon wafer texturing process, which comprises the following steps: firstly, masking and oxidizing a pre-cleaned silicon wafer to form a compact oxide layer region in an unmasked region; step two, removing the mask, etching the silicon wafer by using etching liquid, and forming an etching groove in a compact oxide layer area of the silicon wafer; and thirdly, texturing the silicon wafer with the etching groove. On one hand, the reflection of the illumination is smaller, and on the other hand, more and deeper PN junctions can be obtained, so that the power generation efficiency of the solar cell is improved.

Description

Silicon wafer texturing process
Technical Field
The invention relates to the field of solar cell generation, in particular to the field of solar cell silicon wafer texturing.
Background
Solar cells are devices that directly convert light energy into electrical energy through a photoelectric effect or a photochemical effect. Crystalline silicon solar cells currently operating with the photovoltaic effect are the main stream. Taking a monocrystalline silicon solar cell as an example, the solar cell generation process comprises a solar grade monocrystalline silicon rod manufactured by a crucible Czochralski method, cutting into rectangular silicon wafers, removing surface defects of the silicon wafers generated in the cutting process by alkali or acid corrosion, texturing the silicon wafers, forming a loose silicon layer on the surfaces of the silicon wafers, performing diffusion and knot manufacturing on the silicon wafers, polishing the surfaces of the silicon wafers, removing phosphorosilicate glass, plating an antireflection layer, screen printing and sintering.
Solar light irradiates on PN junction of semiconductor silicon to form hole-electron pair, photo-generated hole flows to p region, photo-generated electron flows to n region, and current is generated after circuit is completed. Therefore, for the solar cell, the efficiency depends on the conditions of 1, the illumination condition of the position of the silicon wafer, 2, the reflection condition of the silicon wafer, 3 and PN junction. Because the illumination condition of the position of the silicon wafer cannot be changed, the efficiency of the solar cell is generally improved through the optimization of the two.
The PN junction state is related to the quality of the silicon wafer, the texturing, the diffusion and other processes, and the invention further improves the power generation efficiency of solar energy mainly from the aspect of texturing.
Disclosure of Invention
The purpose of solar silicon wafer texturing is to generate a plurality of tiny pyramid-shaped appearances on the surface of the silicon wafer, the prior art considers that the texturing is to reduce the reflection of light, and the inventor considers that a loose silicon layer (pyramid-shaped appearance) formed in the texturing process is beneficial to the penetration depth of phosphorus or boron in the subsequent diffusion process, and further beneficial to the penetration of PN junctions. Under the condition that the thickness of the silicon wafer meets the requirement, the deeper PN junction can generate higher battery power generation efficiency.
In a silicon single crystal, four electrons are present beside a silicon atom, when other impurities such as boron and phosphorus are doped in the silicon crystal, a hole is present in the silicon crystal when boron is doped, the hole becomes unstable because no electron is present, the electron is easy to be absorbed and neutralized, a P-type semiconductor is formed, and after a phosphorus atom is doped, because five electrons are present in the phosphorus atom, one electron becomes very active, an N-type semiconductor is formed, more holes are contained in the P-type semiconductor, and more electrons are contained in the N-type semiconductor, so that when the P-type and N-type semiconductors are combined together, a potential difference is formed at a contact surface, that is, a PN junction.
When P-type and N-type semiconductors are bonded together, a special thin layer is formed in the interface region of the two semiconductors, the P-type side of the interface is negatively charged, and the N-type side is positively charged. This is because the P-type semiconductor has multiple holes and the N-type semiconductor has multiple free electrons, and a concentration difference occurs. Holes in the P region spontaneously diffuse into the N region, electrons in the N region spontaneously diffuse into the P region, and due to the opposite directions of the electrons and the holes, the original neutral P-type semiconductor enriches negative charges near the interface (due to the fact that a part of holes diffuse into the N region), and similarly, the original neutral N-type semiconductor enriches positive charges near the interface (due to the fact that a part of electrons diffuse into the P region), so that an 'inner electric field' with N pointing to P is formed, and the diffusion of electrons and holes is prevented. After equilibrium is reached, a special thin layer is formed to form a potential difference, thereby forming a PN junction. When the wafer receives light, holes of the N-type semiconductor move to the P-type region in the PN junction, and electrons in the P-type region move to the N-type region, so that a current is formed from the N-type region to the P-type region. A potential difference is then formed in the PN junction, which forms a power supply.
It can be seen that the PN junction depth and number have a great effect on the cell efficiency. In the prior art, the PN junction depth is often increased by laser scanning.
How to further improve the PN junction depth and the PN junction quantity under the condition that the thickness of the silicon wafer meets the requirement, thereby improving the efficiency of the solar cell.
The technical scheme adopted by the invention is as follows: a silicon wafer texturing process comprises the following steps:
firstly, masking and oxidizing a pre-cleaned silicon wafer to form a compact oxide layer region in an unmasked region;
step two, removing the mask, etching the silicon wafer by using etching liquid, and forming an etching groove in a compact oxide layer area of the silicon wafer;
and thirdly, texturing the silicon wafer with the etching groove.
The pre-cleaned silicon wafer is a dried silicon wafer which is cleaned by deionized water after the surface of the silicon wafer is polished by alkali liquor.
The silicon wafer mask in the first step comprises a single-sided mask and a double-sided mask.
The mask is a physical mask, namely, a physical mask plate is stuck on the silicon wafer.
The etching liquid is an acidic or alkaline etching liquid and comprises hydrofluoric acid solution and sodium hydroxide solution.
The depth of the etching groove is 100-200 mu m.
The beneficial effects of the invention are as follows: according to the invention, after the mask is covered, the etching solution of acid or alkali is adopted to form the etching groove with the depth of 100-200 mu m on the surface of the silicon wafer, and then the etching is carried out to form the pyramid structure on the surface of the silicon wafer with the etching groove, so that on one hand, the reflection of illumination is smaller, and on the other hand, more and deeper PN junctions can be obtained, thereby improving the power generation efficiency of the solar cell.
Detailed Description
Cutting a silicon ingot into silicon wafers, pre-cleaning and drying;
and cleaning the cut and formed silicon wafer subjected to pre-cleaning by using a potassium hydroxide solution containing hydrogen peroxide, cleaning by using deionized water, and drying. In the used potassium hydroxide solution containing hydrogen peroxide, the mass concentration of potassium hydroxide is 1.2%, the mass concentration of hydrogen peroxide is 5%, the temperature of the liquid medicine is 65 ℃, and the reaction time is 60s.
When the surface of the silicon wafer is polished by adopting potassium hydroxide, alkali liquor is adopted for polishing, the temperature is 80 ℃ for 10min, the mass concentration of potassium hydroxide in the alkali liquor is 10%, the mass percentage of chemical auxiliary agent for polishing is 1.5%, the balance is water, and the mass concentration of sodium polyepoxysuccinate in the chemical auxiliary agent for polishing is 0.3%, the mass concentration of sodium chloride is 0.2%, the mass concentration of hydroxyethylidene diphosphate is 0.6%, and the mass concentration of sodium citrate is 0.6%. And then cleaning with deionized water and drying.
Adhering a metal mask plate mask on the front surface, oxidizing, and oxidizing by ozone in an unmasked area to form a compact oxide layer;
removing the metal mask, etching the silicon wafer by using etching liquid, and forming an etching groove on the front surface of the silicon wafer; the etching liquid is sodium hydroxide solution with the mass percentage concentration of 2%, and the depth of the etching groove is 152 mu m. The depth of the etching groove is related to the thickness of the compact oxide layer, so that the etching is stopped when the compact oxide layer is exactly etched by the etching liquid, and the compact oxide layer has the function of preventing silicon under the compact oxide layer from being etched.
And texturing the silicon wafer with the etching groove. In the used texturing solution, the mass percent concentration of KOH is 2.5%, the mass percent concentration of sodium carboxymethylcellulose is 0.8%, the mass percent concentration of sodium chloride is 1.0%, the mass percent concentration of hydroxyethylidene diphosphate is 1.5%, the mass percent concentration of sodium acetate is 0.4%, the mass percent concentration of sodium citrate is 1.5%, the rest is water, the temperature is 80-90 ℃, and the weight reduction of the silicon wafer is kept at 0.4g.
When the PN junction is prepared by a diffusion process, the PN junction is divided into 2-4 steps, each step is firstly oxidized and then deposited, the process conditions during oxidation are that nitrogen is 1500-2000sccm, oxygen is 800-1000sccm, the temperature is 750 ℃, the oxidation time is 100-200s, the process conditions during deposition are that the time is 100-300s, nitrogen is 1000-2000sccm, phosphorus oxychloride is 500-700sccm, and the temperature is 800-820 ℃.
And silicon oxide is formed on the surface of the silicon wafer in the oxidation process, and the silicon oxide reacts with phosphorus oxychloride in the deposition process to complete phosphorus diffusion. The reaction formula is shown below, and x is the number of oxygen atoms bonded with silicon in the oxide layer.
POCl 3 +SiO X →P+ Cl 2 ↑+ SiO 2
Polishing the back surface of the silicon wafer by adopting KOH solution containing an additive; the volume concentration of KOH solution is 5-10%. The weight of the silicon wafer is reduced to 0.1-0.3g in the polishing process; the reflectivity of the back surface of the polished silicon wafer is 35-55%.
The oxidation temperature is controlled between 650 and 750 ℃. The high-temperature oxygen-introducing process can effectively oxidize the silicon wafer to play a passivation role, so that the junction area recombination can be reduced, the open-circuit voltage can be improved, and the product yield can be improved.
The passivation film is a SixNyOz/SixNy laminated film; PECVD can be used to deposit the passivation film; preparing SixNyOz/SixNy laminated film on the back surface of the silicon wafer by using a tubular PECVD method; sixNyOz film is prepared by uniformly mixing SiH4, NH3 and N2O in different proportions, and the total thickness is as follows: 100-150nm, refractive index: 1.5 to 4.0, 3 layers of silicon oxynitride films were prepared in this example; siH uniformly mixed by different proportions 4 And NH 3 SixNy film was prepared, thickness: 50-80nm, refractive index: 1.0-1.5, a multilayer silicon nitride layer is prepared in this example; refractive index of the last silicon nitride layer and silicon oxynitride layer in this embodiment: 4.0-5.0.
And (5) screen printing.
The laser is adopted to open holes on the passivation film on the back, and the parameters of the laser pattern on the back are as follows: number of lines: 50-200 roots; spot diameter: 5-100 μm, spacing of laser lines: 100-10000 mu m; laser power: 5-100W; so that the aluminum silicon forms good ohmic contact.
And printing back electrode silver paste on the back surface of the silicon wafer, back electric field aluminum paste and positive electrode silver paste on the front surface of the silicon wafer.
Sintering at high temperature to form a silicon-based battery; wherein the firing temperature was 750 ℃.
Other non-illustrated matters employ prior art.
。
The test comparison is carried out by adopting 20 silicon wafers with the same specification, wherein 10 silicon wafers completely adopt the process, and the other 10 silicon wafers do not have the steps of preparing masks and forming etching grooves, so that the result shows that the solar power generation efficiency of the silicon wafers with the steps of masking and unmasking is improved by about 5 percent on average compared with the silicon wafers with the steps of unmasking and unmasking.

Claims (6)

1. The silicon wafer texturing process is characterized by comprising the following steps of:
firstly, masking and oxidizing a pre-cleaned silicon wafer to form a compact oxide layer region in an unmasked region;
step two, removing the mask, etching the silicon wafer by using etching liquid, and forming an etching groove in a compact oxide layer area of the silicon wafer;
and thirdly, texturing the silicon wafer with the etching groove.
2. The process for texturing a silicon wafer according to claim 1, wherein: the pre-cleaned silicon wafer is a dried silicon wafer which is cleaned by deionized water after the surface of the silicon wafer is polished by alkali liquor.
3. The process for texturing a silicon wafer according to claim 1, wherein: the silicon wafer mask in the first step comprises a single-sided mask and a double-sided mask.
4. The process for texturing a silicon wafer according to claim 1, wherein: the mask is a physical mask, namely, a physical mask plate is stuck on the silicon wafer.
5. The process for texturing a silicon wafer according to claim 1, wherein: the etching liquid is an acidic or alkaline etching liquid and comprises hydrofluoric acid solution and sodium hydroxide solution.
6. The process for texturing a silicon wafer according to claim 1, wherein: the depth of the etching groove is 100-200 mu m.
CN202310681920.3A 2023-06-09 2023-06-09 Silicon wafer texturing process Pending CN116705906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310681920.3A CN116705906A (en) 2023-06-09 2023-06-09 Silicon wafer texturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310681920.3A CN116705906A (en) 2023-06-09 2023-06-09 Silicon wafer texturing process

Publications (1)

Publication Number Publication Date
CN116705906A true CN116705906A (en) 2023-09-05

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Country Status (1)

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