CN116682734A - Trench MOS device and preparation method thereof - Google Patents
Trench MOS device and preparation method thereof Download PDFInfo
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- CN116682734A CN116682734A CN202310934320.3A CN202310934320A CN116682734A CN 116682734 A CN116682734 A CN 116682734A CN 202310934320 A CN202310934320 A CN 202310934320A CN 116682734 A CN116682734 A CN 116682734A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000005468 ion implantation Methods 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000227 grinding Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 7
- -1 boron ions Chemical class 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
The invention discloses a Trench MOS device and a preparation method thereof, and relates to the technical field of semiconductor electronic devices, wherein the preparation method comprises the steps of providing a P-type epitaxial substrate, etching to form a groove, and depositing a first dielectric layer on the surface of the P-type epitaxial substrate and the groove; growing polysilicon on the first dielectric layer in the groove to fill the groove, and grinding back to etch; n-type doping and P-type doping are sequentially carried out on the P-type epitaxial layer, and a well region and a source electrode are obtained; depositing a second dielectric layer on the surface of the P-type epitaxial layer, and etching the well region to form a groove; p-type ion implantation is carried out in the groove at a first preset temperature and a first preset concentration, and then N-type ion implantation is carried out; the metal is deposited in the groove, and the invention can solve the technical problems that doping ions injected into the well region before metal deposition are of the same type, the doping of the well region is wide due to the depth change of the through hole caused by process fluctuation, a PN junction forms a bulge with smaller curvature radius, and BV is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor electronic devices, in particular to a Trench MOS device and a preparation method thereof.
Background
The Trench MOS device is a novel vertical structure device, is developed on the basis of a VDMOS (vertical double-diffusion metal oxide semiconductor field effect transistor), and has lower on-resistance and gate leakage charge density compared with the VDMOS, so that the Trench MOS device has lower on-state and switching loss and faster switching speed. Meanwhile, as the channel of the Trench MOS device is vertical, the channel density of the Trench MOS device can be further improved, and the chip size is reduced.
The source electrode of the conventional Trench MOS device is etched by etching a through hole in a metal region of an epitaxial substrate, depositing metal to connect the source electrode, and connecting the source electrode out, but in order to avoid parasitic triode effect, the through hole is usually etched to a well region, and ion implantation is performed before depositing metal, so that the contact resistance between the metal and the source electrode is reduced.
However, when the ion implantation is performed before the metal deposition, the doping of the well region is widened due to the deepening of the through hole, a bulge is formed, the thickness of the compressive epitaxial substrate is reduced, the radius of curvature of the junction is reduced, and the BV (breakdown voltage) is reduced.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a Trench MOS device and a preparation method thereof, and aims to solve the technical problems that doping ions injected into a well region before metal deposition are of the same type, the doping of the well region is widened due to the depth change of a through hole caused by process fluctuation, a PN junction forms a bulge with smaller curvature radius, and BV is reduced.
An aspect of the present invention provides a method for manufacturing a Trench MOS device, where the method for manufacturing a Trench MOS device includes:
providing a P-type epitaxial substrate, etching the P-type epitaxial substrate to form a groove, and depositing a first dielectric layer with preset thickness on the surface of the P-type epitaxial substrate and the groove;
growing polysilicon on the first dielectric layer in the groove to fill the groove, and grinding and back-etching the polysilicon;
n-type doping and P-type doping are sequentially carried out on one side, close to the side wall of the groove, of the P-type epitaxial substrate to obtain a well region and a source electrode, and the source electrode is arranged on the well region;
depositing a second dielectric layer on the surface of the P-type epitaxial substrate, and etching the second dielectric layer to the well region on one side close to the groove to form a groove;
p-type ion implantation is carried out in the groove at a first preset temperature and a first preset concentration, and N-type ion implantation is carried out at a second preset temperature and a second preset concentration after the P-type ion implantation is completed;
and after the N-type ion implantation is completed, depositing metal in the groove.
Compared with the prior art, the invention has the beneficial effects that: the preparation method of the Trench MOS device can effectively improve BV of the Trench MOS device, specifically, N-type ions are implanted into the groove to reduce contact resistance between metal and a source electrode, P-type ions are implanted before N-type ion implantation to inhibit diffusion of N-type ions, and the problem that the well region is widened due to diffusion of N-type ions to form protrusions to cause BV to be lowered is solved, so that the technical problem that doped ions implanted before metal deposition and the well region are doped in the same type, the well region is widened due to doping due to depth change of a through hole caused by process fluctuation, PN junctions form protrusions with smaller curvature radius to cause BV to be lowered is solved.
According to an aspect of the above technical solution, the P-type ion is boron ion, the first preset temperature is 800 ℃ to 1100 ℃, and the first preset concentration is 1×10 12 cm -3 -1×10 15 cm -3 。
According to an aspect of the above technical solution, under the preset times, the N-type ions are arsenic ions, the second preset temperature is 700 ℃ to 1100 ℃, and the second preset concentration is 1×10 13 cm -3 -1×10 16 cm -3 。
According to an aspect of the above technical solution, the N-type ions and the P-type ions are implanted through bottom edges of the grooves.
According to an aspect of the above technical solution, the depth of the groove is 0.3 μm-0.6 μm.
According to an aspect of the foregoing technical solution, the preset thickness is 400 a-700 a.
According to an aspect of the above technical solution, the dopant of the well region is phosphorus, the temperature of the N-type doping is 700 ℃ to 1000 ℃, and the concentration of the N-type doping is 1×10 10 cm -3 -1×10 14 cm -3 。
According to an aspect of the above technical solution, the dopant of the source is boron, the temperature of the P-type doping is 800-1100 ℃, and the concentration of the P-type doping is 1×10 13 cm -3 -1×10 17 cm -3 。
According to an aspect of the foregoing technical solution, the depth of the trench is 1 μm-1.5 μm.
Another aspect of the present invention provides a Trench MOS device, where the Trench MOS device is prepared by the method for preparing a Trench MOS device described in any one of the above, and the Trench MOS device includes:
a P-type epitaxial substrate;
the P-type epitaxial substrate is provided with a groove, a first dielectric layer and polysilicon are sequentially arranged in the groove, second dielectric layers are respectively arranged on the groove and the P-type epitaxial substrate, grooves are formed in the second dielectric layers, P-type ions and N-type ions are sequentially injected into the bottom edges of the grooves, and metal is filled in the grooves;
and a source electrode and a well region are arranged between the groove and the groove, and the source electrode is arranged on the well region.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a flowchart of a method for manufacturing a Trench MOS device of the present invention;
fig. 2 is a schematic diagram of a method for manufacturing a Trench MOS device of the present invention;
description of the drawings element symbols:
the semiconductor device comprises a P-type epitaxial substrate 10, a first dielectric layer 20, a second dielectric layer 21, polysilicon 30, a well region 40, a source electrode 50 and metal 60.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," "upper," "lower," and the like are used herein for descriptive purposes only and not to indicate or imply that the apparatus or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
In the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1-2, a method for manufacturing a Trench MOS device according to the present invention includes steps S10-S15:
step S10, providing a P-type epitaxial substrate, etching the P-type epitaxial substrate to form a groove, and depositing a first dielectric layer with preset thickness on the surface of the P-type epitaxial substrate and the groove;
wherein the depth of the trench is 1 μm-1.5 μm, and the trench is used for filling the polysilicon 30 to form the gate.
In addition, the first dielectric layer 20 is used to isolate the P-type epitaxial substrate 10 with the preset thickness of 400 a-700 a, and when the preset thickness is too thin, the substrate and the gate cannot be effectively isolated, resulting in short circuit.
The growth temperature of the first dielectric layer 20 is 800-1100 ℃, and the compactness and the flatness of the first dielectric layer 20 can be improved by means of hot oxygen and high temperature.
Step S11, growing polysilicon on the first dielectric layer in the groove to fill the groove, and grinding and back-etching the polysilicon;
after the polysilicon 30 is polished back and etched, a gate is formed, so as to avoid the polysilicon 30 remaining on the surface of the P-type epitaxial substrate 10 to cause a short circuit.
Step S12, N-type doping and P-type doping are sequentially carried out on one side, close to the side wall of the groove, of the P-type epitaxial substrate, so that a well region and a source electrode are obtained, and the source electrode is arranged on the well region;
specifically, the P-type epitaxial substrate 10 is doped with phosphorus in the N-type doping temperature of 700-1000 ℃ to obtain a well region 40; wherein the N-type doping concentration is 1×10 10 cm -3 -1×10 14 cm -3 。
P type doping is carried out on the P type epitaxial substrate 10, the doping agent is boron, the temperature of the P type doping is 800-1100 ℃, and the source electrode 50 is obtained. Wherein the concentration of the P-type doping is 1×10 13 cm -3 -1×10 17 cm -3 。
Step S13, depositing a second dielectric layer on the surface of the P-type epitaxial substrate, and etching the second dielectric layer to the well region on one side close to the groove to form a groove;
the second dielectric layer 21 is etched into the well region 40 to form a recess with a depth of 0.3 μm to 0.6 μm for depositing the metal 60 to turn on the source 50, but the recess is typically etched into the well region 40 to avoid parasitic triode effect.
S14, P-type ion implantation is carried out in the groove at a first preset temperature and a first preset concentration, and N-type ion implantation is carried out at a second preset temperature and a second preset concentration after the P-type ion implantation is completed;
in order to reduce the contact resistance between the metal 60 and the source 50, N-type ion implantation is required to implant the same type of doping as the doping ions of the well region 40 before depositing the metal 60. However, the N-type ions are the same as the doping ions in the well region 40, which will lead to a wide doping in the well region 40, form protrusions, reduce the thickness of the compressive epitaxial substrate, reduce the radius of curvature of the junction, and lower the BV (breakdown voltage).
Therefore, P-type ions are implanted before N-type ion implantation to suppress diffusion of N-type ions, to smooth the well region 40, to improve formation of protrusions, and to suppress lowering of BV.
Specifically, the P-type ion is boron ion, the first preset temperature is 800-1100 ℃, and the first preset concentration is 1 multiplied by 10 12 cm -3 -1×10 15 cm -3 . By setting the first preset temperature and the first preset concentration, the diffusion area of the P-type ions is controlled, the threshold voltage is affected by too wide diffusion area, and the short circuit of the source electrode 50 area is caused by too deep diffusion area.
When the first preset concentration is too low, the diffusion of the N-type ions is limited, and the protrusion is formed under the well region 40, so that BV is reduced; when the first preset concentration is too high, the diffusion region of the P-type ions is widened and deepened, affecting the threshold voltage or shorting the source 50.
Similarly, when the first preset temperature is too low, the diffusion area of the P-type ions is limited, the diffusion of the N-type ions is limited, and the protrusion is formed under the well region 40, so that the BV is reduced; when the first preset temperature is too high, the diffusion region of the P-type ions is widened and deepened, affecting the threshold voltage or shorting the source 50.
The N-type ion is arsenic ion, the second preset temperature is 700-1100 ℃, and the second preset concentration is 1 multiplied by 10 13 cm -3 -1×10 16 cm -3 。
Wherein, N-type ions and P-type ions are injected through the bottom edge of the groove.
And S15, depositing metal in the groove after the N-type ion implantation is completed.
In addition, the invention also provides a Trench MOS device, which is prepared by the preparation method of the Trench MOS device, and comprises the following steps:
a P-type epitaxial substrate;
the P-type epitaxial substrate is provided with a groove, a first dielectric layer and polysilicon are sequentially arranged in the groove, second dielectric layers are respectively arranged on the groove and the P-type epitaxial substrate, grooves are formed in the second dielectric layers, P-type ions and N-type ions are sequentially injected into the bottom edges of the grooves, and metal is filled in the grooves;
wherein the depth of the trench is 1 μm-1.5 μm. The first dielectric layer is used for isolating the P-type epitaxial substrate, and the polysilicon forms a grid electrode. The groove is used for depositing metal, conducting the source electrode and connecting the source electrode out.
In addition, in order to reduce the contact resistance between the metal and the source, the N-type ion implantation is required to implant the same type of doping as the doping ions of the well region before depositing the metal. However, the N-type ions and the doping ions of the well region have the same type, which can lead to the wide doping of the well region, form protrusions, reduce the thickness of the compressive epitaxial substrate, reduce the radius of curvature of the junction, and reduce the BV (breakdown voltage). Therefore, P-type ions are implanted before N-type ion implantation to suppress diffusion of N-type ions, to smooth the well region, to improve formation of protrusions, and to suppress lowering of BV.
Specifically, P-type ion implantation is performed in the groove at a first preset temperature and a first preset concentration, and after the P-type ion implantation is completed, N-type ion implantation is performed at a second preset temperature and a second preset concentration.
And a source electrode and a well region are arranged between the groove and the groove, and the source electrode is arranged on the well region.
And performing N-type doping on the P-type epitaxial layer to obtain a well region, and performing P-type doping on the P-type epitaxial layer to obtain a source electrode.
The invention is further illustrated by the following examples:
example 1
The first embodiment of the invention provides a method for preparing a Trench MOS device, which comprises the following steps of S10-S15:
step S10, providing a P-type epitaxial substrate, etching the P-type epitaxial substrate to form a groove, and depositing a first dielectric layer with preset thickness on the surface of the P-type epitaxial substrate and the groove;
the depth of the groove is 1-1.5 mu m, and the groove is used for filling polycrystalline silicon to form a grid electrode.
In addition, the preset thickness is 400A-700A, and the first dielectric layer is used for isolating the P-type epitaxial substrate.
The growth temperature of the first dielectric layer is 800-1100 ℃.
Step S11, growing polysilicon on the first dielectric layer in the groove to fill the groove, and grinding and back-etching the polysilicon;
and after the polysilicon is ground and etched back, forming a grid electrode, and avoiding short circuit caused by the fact that the polysilicon remains on the surface of the P-type epitaxial substrate.
Step S12, N-type doping and P-type doping are sequentially carried out on one side, close to the side wall of the groove, of the P-type epitaxial substrate, so that a well region and a source electrode are obtained, and the source electrode is arranged on the well region;
specifically, N-type doping is carried out on the P-type epitaxial layer, the doping agent is phosphorus, the temperature of the N-type doping is 700-1000 ℃, and a well region is obtained; wherein the N-type doping concentration is 1×10 10 cm -3 -1×10 14 cm -3 。
And P-type doping is carried out on the P-type epitaxial layer, the doping agent is boron, the temperature of the P-type doping is 800-1100 ℃, and the source electrode is obtained. Wherein the concentration of the P-type doping is 1×10 13 cm -3 -1×10 17 cm -3 。
Step S13, depositing a second dielectric layer on the surface of the P-type epitaxial substrate, and etching the second dielectric layer to the well region on one side close to the groove to form a groove;
the depth of the groove is 0.3 μm, which is used for depositing metal and connecting the source electrode.
S14, P-type ion implantation is carried out in the groove at a first preset temperature and a first preset concentration, and N-type ion implantation is carried out at a second preset temperature and a second preset concentration after the P-type ion implantation is completed;
specifically, the P-type ion is boron ion, the first preset temperature is 800-1100 ℃, and the first preset concentration is 1 multiplied by 10 12 cm -3 -1×10 15 cm -3 。
The N-type ion is arsenic ion, the second preset temperature is 700-1100 ℃, and the second preset concentration is 1 multiplied by 10 13 cm -3 -1×10 16 cm -3 。
Wherein, N-type ions and P-type ions are injected through the bottom edge of the groove.
And S15, depositing metal in the groove after the N-type ion implantation is completed.
Example 2
The method for manufacturing the Trench MOS device provided by the second embodiment of the present invention is different from the method for manufacturing the Trench MOS device in the first embodiment in that:
the depth of the groove was 0.4. Mu.m.
Example 3
The third embodiment of the present invention provides a method for manufacturing a Trench MOS device, which is different from the method for manufacturing a Trench MOS device in the first embodiment in that:
the depth of the groove was 0.5. Mu.m.
Example 4
The method for manufacturing a Trench MOS device provided by the fourth embodiment of the present invention is different from the method for manufacturing a Trench MOS device in the first embodiment in that:
the depth of the groove was 0.6. Mu.m.
Comparative example 1
The method for manufacturing the Trench MOS device provided by the first comparative example of the present invention is different from the method for manufacturing the Trench MOS device in the first embodiment in that:
the grooves have no P-type ion implantation, and the depth of the grooves is 0.3 mu m.
Comparative example 2
The method for manufacturing the Trench MOS device provided by the second comparative example of the present invention is different from the method for manufacturing the Trench MOS device in the first embodiment in that:
the grooves have no P-type ion implantation, and the depth of the grooves is 0.4 mu m.
Comparative example 3
The method for manufacturing the Trench MOS device provided by the third comparative example of the present invention is different from the method for manufacturing the Trench MOS device in the first embodiment in that:
the grooves have no P-type ion implantation, and the depth of the grooves is 0.5 mu m.
Comparative example 4
The method for manufacturing the Trench MOS device provided by the fourth comparative example of the present invention is different from the method for manufacturing the Trench MOS device in the first embodiment in that:
the grooves have no P-type ion implantation, and the depth of the grooves is 0.6 mu m.
Referring to table 1 below, the results of the performance test of the Trench MOS devices prepared in the different examples and comparative examples are shown.
TABLE 1
According to table 1, it can be seen from the depth test data of the different grooves of examples 1 to 4 and comparative examples 1 to 4 that the deeper the groove is, the deeper the depth of the well region is etched, the more easily the implanted N-type ions cause the well region to be widened, the larger the protrusion is, the more the BV is lowered, and when P-type ions are implanted before the N-type ions, the widening of the well region can be effectively suppressed, the generation of the protrusion is suppressed, and the BV is raised. In addition, the deeper the groove, the more pronounced the inhibition of P-type ions.
In summary, P-type ions are implanted before N-type ion implantation to inhibit diffusion of N-type ions, so that the well region is smooth, the formation of protrusions is improved, and BV is promoted.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention, and are described in detail, but are not to be construed as limiting the scope of the invention. It should be noted that it is possible for those skilled in the art to make several variations and modifications without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. The preparation method of the Trench MOS device is characterized by comprising the following steps of:
providing a P-type epitaxial substrate, etching the P-type epitaxial substrate to form a groove, and depositing a first dielectric layer with preset thickness on the surface of the P-type epitaxial substrate and the groove;
growing polysilicon on the first dielectric layer in the groove to fill the groove, and grinding and back-etching the polysilicon;
n-type doping and P-type doping are sequentially carried out on one side, close to the side wall of the groove, of the P-type epitaxial substrate to obtain a well region and a source electrode, and the source electrode is arranged on the well region;
depositing a second dielectric layer on the surface of the P-type epitaxial substrate, and etching the second dielectric layer to the well region on one side close to the groove to form a groove;
p-type ion implantation is carried out in the groove at a first preset temperature and a first preset concentration, and N-type ion implantation is carried out at a second preset temperature and a second preset concentration after the P-type ion implantation is completed;
and after the N-type ion implantation is completed, depositing metal in the groove.
2. The method for manufacturing a Trench MOS device according to claim 1, wherein the P-type ions are boron ions, the first preset temperature is 800-1100 ℃, and the first preset concentration is 1×10 12 cm -3 -1×10 15 cm -3 。
3. The method for manufacturing a Trench MOS device according to claim 1, wherein the N-type ions are arsenic ions, the second preset temperature is 700-1100 ℃, and the second preset concentration is 1×10 13 cm -3 -1×10 16 cm -3 。
4. The method for manufacturing a Trench MOS device according to claim 1, wherein the N-type ions and the P-type ions are implanted through bottom edges of the recess.
5. The method for manufacturing the Trench MOS device according to claim 1, wherein the depth of the groove is 0.3 μm-0.6 μm.
6. The method for manufacturing a Trench MOS device according to claim 1, wherein the predetermined thickness is 400-700A.
7. The method for manufacturing a Trench MOS device according to claim 1, wherein the dopant of the well region is phosphorus, the temperature of the N-type doping is 700-1000deg.C, and the concentration of the N-type doping is 1×10 10 cm -3 -1×10 14 cm -3 。
8. The method for manufacturing a Trench MOS device according to claim 1, wherein the dopant of the source is boron, the temperature of the P-type doping is 800-1100 ℃, and the concentration of the P-type doping is 1×10 13 cm -3 -1×10 17 cm -3 。
9. The method for manufacturing the Trench MOS device according to claim 1, wherein the depth of the Trench is 1 μm-1.5 μm.
10. A Trench MOS device, wherein the Trench MOS device is prepared by the method for preparing a Trench MOS device according to any one of claims 1-9, the Trench MOS device comprising:
a P-type epitaxial substrate;
the P-type epitaxial substrate is provided with a groove, a first dielectric layer and polysilicon are sequentially arranged in the groove, second dielectric layers are respectively arranged on the groove and the P-type epitaxial substrate, grooves are formed in the second dielectric layers, P-type ions and N-type ions are sequentially injected into the bottom edges of the grooves, and metal is filled in the grooves;
and a source electrode and a well region are arranged between the groove and the groove, and the source electrode is arranged on the well region.
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