CN215578580U

CN215578580U - Novel groove IGBT semiconductor device

Info

Publication number: CN215578580U
Application number: CN202121121004.7U
Authority: CN
Inventors: 戚丽娜; 张景超; 井亚会; 俞义长; 赵善麒
Original assignee: Macmic Science & Technology Holding Co ltd
Current assignee: Macmic Science & Technology Holding Co ltd
Priority date: 2021-05-24
Filing date: 2021-05-24
Publication date: 2022-01-18
Anticipated expiration: 2031-05-24

Abstract

The utility model provides a novel trench IGBT semiconductor device, which comprises a substrate, and a base region, a well region and a source region which are formed on the substrate in an epitaxial manner in sequence, wherein a plurality of true trench gate units and a false trench gate unit arranged between the adjacent true trench gate units are arranged in the base region and the well region, the source region is respectively arranged on two sides of each true trench gate unit, and a bottom doped region is arranged at the bottom of each true trench gate unit and the bottom of each false trench gate unit. The utility model can realize a local super junction structure to improve breakdown voltage, and can realize the reduction of the structure thickness to reduce voltage drop, thereby reducing the capacitance area and the Miller capacitance and ensuring the performance of the device.

Description

Novel groove IGBT semiconductor device

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a novel trench IGBT semiconductor device.

Background

At present, the power devices have a large trend of high power density and continuous miniaturization, and for example, the IGBT chips also need to be further increased in power density. Generally, in order to increase the power density of an IGBT chip, a fine cell design is generally adopted to increase the density of trenches, so as to achieve the purpose of increasing the current density, but due to the increase of the trench density, the capacitance area and the miller capacitance are often increased, thereby affecting the chip performance.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to solving, at least to some extent, one of the technical problems in the art described above. Therefore, the utility model aims to provide a novel trench IGBT semiconductor device, which can realize a local super junction structure to improve breakdown voltage, and can realize reduction of the structure thickness to reduce voltage drop, thereby reducing the capacitance area and the Miller capacitance and ensuring the performance of the device.

In order to achieve the above object, an embodiment of the present invention provides a novel trench IGBT semiconductor device, including a substrate, and a base region, a well region, and a source region which are sequentially formed on the substrate by epitaxy, and a plurality of true trench gate units and a dummy trench gate unit which is disposed between adjacent true trench gate units are further disposed in the base region and the well region, wherein two sides of each true trench gate unit are respectively provided with the source region, and a bottom doped region is further disposed at the bottom of each true trench gate unit and each dummy trench gate unit.

According to the novel trench IGBT semiconductor device provided by the embodiment of the utility model, the substrate, the base region, the well region and the source region are sequentially formed on the substrate in an epitaxial manner, the base region and the well region are also provided with the plurality of true trench gate units, and the false trench gate units are arranged between the adjacent true trench gate units, wherein the bottom doping regions are also arranged at the bottoms of each true trench gate unit and each false trench gate unit, so that a local super junction structure can be realized to improve the breakdown voltage, the reduction of the structure thickness can be realized to reduce the voltage drop, the capacitance area and the Miller capacitance can be reduced, and the performance of the device can be ensured.

In addition, the novel trench IGBT semiconductor device proposed according to the above embodiment of the present invention may also have the following additional technical features:

according to an embodiment of the present invention, the width of the bottom doped region is the same as the width of the corresponding true trench gate cell or the dummy trench gate cell.

According to one embodiment of the utility model, the bottom doped region is located within the base region.

According to an embodiment of the present invention, the bottom doped region is a P + type doped region.

According to one embodiment of the utility model, the substrate is an N-type substrate.

According to one embodiment of the utility model, the base region is N⁺And a base region.

According to one embodiment of the present invention, the well region is a P-type well region.

According to one embodiment of the present invention, the source region is N⁺A source region.

Drawings

Fig. 1 is a schematic structural diagram of a novel trench IGBT semiconductor device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a novel trench IGBT semiconductor device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the longitudinal electric field distribution of a prior art IGBT semiconductor device;

fig. 4 is a schematic diagram of the longitudinal electric field distribution of the novel trench IGBT semiconductor device according to an embodiment of the present invention;

fig. 5 is a PW large angle implant schematic diagram of a novel trench IGBT semiconductor device according to an embodiment of the utility model.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a novel trench IGBT semiconductor device according to an embodiment of the present invention.

As shown in fig. 1, the novel trench IGBT semiconductor device according to the embodiment of the utility model includes a substrate 10, and a base region 20, a well region 30, and a source region 40 epitaxially formed on the substrate 10 in sequence, and a plurality of true trench gate units 50 and dummy trench gate units 60 disposed between adjacent true trench gate units 50 are further disposed in the base region 20 and the well region 30, wherein the source region 40 is disposed on two sides of each true trench gate unit 50, and a bottom doped region 70 is further disposed at the bottom of each true trench gate unit 50 and each dummy trench gate unit 60.

Specifically, as shown in fig. 1, each true trench gate cell 50 and each dummy trench gate cell 60 may be connected to the bottom of the base region 20 through a bottom doped region 70 provided at the bottom, whereby a local super junction structure can be realized to improve the breakdown voltage, and a reduction in the thickness of the structure can be realized to reduce the voltage drop, so that the capacitance area and the miller capacitance can be reduced.

Further, as shown in fig. 2, the novel trench IGBT semiconductor device according to the embodiment of the present invention may further include a buffer region 80 and a collector region 90, i.e., N shown in fig. 2⁺ Buffer 80 and P⁺Collector region 90, wherein buffer region 80 may be used to reduce saturation voltage drop and shorten switching time. Specifically, the buffer 80 may be an N-type SIC buffer, and in other embodiments of the present invention, the buffer 80 may be configured as another type, for example, the buffer 80 may be a P-type SIC buffer, which is not limited herein.

In one embodiment of the present invention, the substrate 10 may be an N-type substrate, and in particular, the N-type substrate 10 may be an N-type single crystal silicon substrate. In addition, in other embodiments of the present invention, the substrate 10 may also be other semiconductor materials, such as polysilicon or amorphous silicon, and may also include mixed semiconductor structures, such as silicon carbide, alloy semiconductors, or combinations thereof, which are not limited herein.

In one embodiment of the present invention, base region 20 may be N, as shown in FIGS. 1 and 2⁺The base region may be epitaxially formed on the substrate 10, further, a well region 30, such as a P-type well region, i.e., a PW well region, may be epitaxially formed on the base region 20, and a source region 40, such as an N + source region, may be epitaxially formed on the well region 30.

In one embodiment of the present invention, as shown in fig. 1 and fig. 2, the bottom doped region 70 may be a P + type doped region, and the width of the bottom doped region 70 is the same as that of the corresponding true trench gate cell 50 or dummy trench gate cell 60, and furthermore, the bottom of the bottom doped region 70 may maximally extend to the bottom of the base region 20, so as to ensure that the bottom doped region 70 is located in the base region 20. The doping concentration and the depth of the base region 20 can be increased as required, so that the bottom doping region can have the characteristics of longitudinal extension and transverse folding, and the slope of a longitudinal electric field can be reduced through matching between the doping concentration of the base region and the doping concentration of the bottom doping region.

Specifically, as shown in fig. 3 and fig. 4, the novel trench IGBT semiconductor device proposed based on the embodiment of the present invention can reduce the slope of the longitudinal electric field, thereby improving the breakdown voltage of the structure, providing a possibility for reducing the thickness of the structure, and further realizing the miniaturization of the structure.

Based on the structure, the novel trench IGBT semiconductor device according to the embodiment of the present invention can be formed, and the following describes a manufacturing process of the novel trench IGBT semiconductor device according to the embodiment of the present invention with reference to the structure.

The preparation method of the novel groove IGBT semiconductor device provided by the embodiment of the utility model comprises the following specific steps: 1, GR, field-limiting ring injection and push-knot; 2, base region injectionThe junction is implanted and pushed, and N can be formed by implanting ions into N-type substrate⁺Base region, and N⁺The concentration and the junction depth of the base region can be adjusted according to actual requirements; 3, etching the groove, specifically in N⁺Etching the true trench gate unit and the false trench gate unit on the base region; 4, well region large angle injection, specifically injecting P on the side wall of the groove to form a P-type well region; 5, a gate oxide layer; 6, injecting a bottom doped region, specifically injecting P + type doping at an angle of 0 DEG to form a P type bottom doped region; 7, depositing and etching polycrystalline silicon; 8, injecting and activating a source region, specifically injecting and forming N outside the true trench gate unit⁺A source region; 9, a hole; 10, a metal; 11, a passivation layer; and 12, thinning the back, injecting and metalizing the BGBM. The steps 9-12 are conventional IGBT preparation steps and are not described in detail.

The well region large angle implantation, that is, the angle of PW large angle implantation needs to be determined by combining the widths and the intervals of the true trench gate unit and the dummy trench gate unit, and the well region junction depth requirement and implantation energy, for example, the well region large angle implantation can be performed through the angle shown in fig. 5, and the implantation angle Φ is between 20 ° and 45 °, if the influence of the implantation energy is neglected, the implantation depth H of the trench sidewall is approximately equal to the PW junction depth, the implantation angle Φ is calculated from the trench width W and the sidewall implantation region depth H, that is, tan Φ is W/H, so that the implantation angle Φ can be calculated; if the influence of the implantation energy is considered, the same design and the same implantation angle phi are adopted, and the larger the implantation energy is, the deeper the PW junction is.

The deep well region can be formed by utilizing the side wall of the groove through large-angle injection, and the step of well region junction pushing in the prior art can be omitted, so that the stress influence caused by a refined groove can be reduced, and in addition, a precise doping foundation can be provided for the subsequent injection of the bottom doped region; moreover, well region large-angle injection is carried out before the gate oxide layer is carried out, and the influence of the well region large-angle injection, namely the PW large-angle injection on the quality of gate oxide can be avoided; in addition, the bottom doped region is implanted after the gate oxide layer is formed, so that the thermal process of the subsequent step of bottom implantation can be reduced to the maximum extent, and the lateral expansion of the bottom doped region can be reduced.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The meaning of "plurality" is two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Claims

1. The utility model provides a novel slot IGBT semiconductor device, its characterized in that, includes the substrate, and base region, well region, the source region that epitaxial formation in proper order on the substrate, and the base region with still be equipped with a plurality of true trench gate units in the well region, and set up in adjacent false trench gate unit between the true trench gate unit, wherein, every true trench gate unit both sides are equipped with the source region respectively, and at every true trench gate unit and every false trench gate unit bottom still is equipped with the bottom and mixes the district.

2. The novel trench IGBT semiconductor device of claim 1, wherein the bottom doped region has a width that is the same as a width of the corresponding true trench gate cell or the dummy trench gate cell.

3. The novel trench IGBT semiconductor device of claim 2, wherein the bottom doped region is located within the base region.

4. The novel trench IGBT semiconductor device of claim 3, wherein the bottom doped region is a P + type doped region.

5. The novel trench IGBT semiconductor device of claim 4, wherein the substrate is an N-type substrate.

6. The novel trench IGBT semiconductor device of claim 5, characterized in that the base region is N⁺And a base region.

7. The novel trench IGBT semiconductor device of claim 6, wherein the well region is a P-type well region.

8. The novel trench IGBT semiconductor device of claim 3, wherein the source region is N⁺A source region.