CN116666428A - 一种氮化镓肖特基二极管及其制备方法 - Google Patents
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 155
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 238000002161 passivation Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000011148 porous material Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 36
- 229910001020 Au alloy Inorganic materials 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 238000009616 inductively coupled plasma Methods 0.000 claims description 21
- 238000001704 evaporation Methods 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 16
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 15
- 238000005566 electron beam evaporation Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 238000002207 thermal evaporation Methods 0.000 claims description 2
- 238000004377 microelectronic Methods 0.000 abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 18
- 229910010271 silicon carbide Inorganic materials 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
本发明涉及一种氮化镓肖特基二极管及其制备方法,属于微电子二极管技术领域。二极管包括由下到上依次设置的阴极金属、n+型SiC衬底、n+型GaN层、无掺杂GaN层和p型GaN层,p型GaN层上设置有阳极金属,阳极金属、p型GaN层和无掺杂GaN层上方覆盖有开孔的SiO2钝化层,SiO2钝化层开孔处设有阳极金属场版。本发明在SiC衬底上进行GaN垂直器件的制备,可实现垂直器件的三维电子通道,从而有效提高输出电流密度,降低器件导通阻值,降低器件尺寸,实现器件高功率小型化的使用。
Description
技术领域
本发明涉及一种氮化镓肖特基二极管及其制备方法,属于微电子二极管技术领域。
背景技术
随着科技的不断进步,能源成为限制科技发展速度的重要因素,电力电子技术中的功率器件作为能源转换的核心元件,成为微电子学研究的重点。目前市场上主流的功率器件仍然是硅基器件,但是随着电力电子技术的发展,硅基材料由于本身材料特性参数的制约,无法继续满足功率器件的进一步需求。以氮化镓和碳化硅为代表的第三代半导体由于耐高压、耐高温、高频率、高功率以及抗辐射等优异的性能得到了广泛的关注和研究。
肖特基二极管(SBD)是功率转换系统中的核心元件之一,具有高开关速度、低开启电压、低导通电阻、以多数载流子为主导的的特点。一般来说,氮化镓基肖特基二极管主要包括三种结构:水平结构,准垂直结构和垂直结构。水平结构和准垂直结构大多是在异质外延层上来制备的,但异质外延层中较大的位错密度和晶格失配导致器件存在较大的反向漏电。另外,从结构上来看,水平结构和准垂直结构无法充分利用氮化镓材料宽禁带的特点,电学特性难以达到其材料极限。除此之外,相比于水平结构和准垂直结构,垂直结构可以实现更小的尺寸,可以在很大程度上缓解电场阻塞效应,有利于制备出性能更高的肖特基二极管。
在衬底选择上,无论是水平器件、准垂直器件还是垂直器件,可以实现同质外延的氮化镓衬底是最理想的材料,但是氮化镓衬底极高的成本和极难的大尺寸生长工艺限制了其广泛应用。
在氮化镓肖特基二极管中,结边缘的电场聚集往往会导致器件的过早击穿,因此,利用终端结构来平衡结边缘的电场分布是提高反向击穿电压的有效手段。其中,通过离子注入的方法在结边缘引入PN结从而改变器件的空间电荷区是平衡电场的常用方法,但是这种方法工艺复杂,价格昂贵。为此,提出本发明。
发明内容
针对现有技术的不足,本发明提供一种氮化镓肖特基二极管,在SiC衬底上进行GaN垂直器件的制备,可实现垂直器件的三维电子通道,从而有效提高输出电流密度,降低器件导通阻值,降低器件尺寸,实现器件高功率小型化的使用。
本发明还提供上述氮化镓肖特基二极管的制备方法。
本发明的技术方案如下:
一种氮化镓肖特基二极管,包括由下到上依次设置的阴极金属、n+型SiC衬底、n+型GaN层、无掺杂GaN层和p型GaN层,p型GaN层上设置有阳极金属,阳极金属、p型GaN层和无掺杂GaN层上方覆盖有开孔的SiO2钝化层,SiO2钝化层开孔处设有阳极金属场版。
根据本发明优选的,所述氮化镓肖特基二极管包括下列条件之一或多种:
(1)所述n+型GaN层的厚度为10~2000nm,掺杂元素为Si,掺杂浓度为1×1018~1×1020cm-3;
(2)所述无掺杂GaN层的厚度为1~100μm;
(3)所述p型GaN层的厚度为1~5000nm,掺杂元素为Mg,掺杂浓度为1×1017~1×1019cm-3;
(4)所述阴极金属的材料为Ni、Ni/Au合金或Ti/Au合金;
(5)所述阳极金属的材料为Ni/Au合金、Pd/Au合金或Al/Au合金;
(6)所述阳极金属场版的材料为Ni/Au合金或Ti/Au合金。
根据本发明进一步优选的,n+型GaN层的厚度为1000nm,掺杂元素Si的掺杂浓度为1×1019cm-3,无掺杂GaN层的厚度为5μm,p型GaN层的厚度为500nm,掺杂元素Mg的掺杂浓度为1×1018cm-3,阴极金属的材料为Ni,阳极金属的材料为Ni/Au合金,阳极金属场版的材料为Ni/Au合金。
上述氮化镓肖特基二极管的制备方法,步骤如下:
S1、在n+型SiC衬底上依次外延生长n+型GaN层、无掺杂GaN层和p型GaN层;
S2、通过干法刻蚀对p型GaN层进行台面刻蚀,刻蚀终点位于无掺杂GaN层;
S3、通过干法刻蚀对p型GaN层进行中间部分刻蚀,刻蚀终点位于无掺杂GaN层;
S4、在n+型SiC衬底下方蒸镀阴极金属,退火形成欧姆接触;
S5、在p型GaN层和无掺杂GaN层上方蒸镀阳极金属,形成肖特基接触;
S6、在无掺杂GaN层、p型GaN层和阳极金属的上方生长SiO2钝化层;
S7、在SiO2钝化层需要蒸镀阳极金属场版的区域通过光刻显影和干法刻蚀的方法开孔;
S8、在SiO2钝化层开孔区域蒸镀阳极金属场版(FP)。
根据本发明优选的,步骤S1中的n+型GaN层、无掺杂GaN层、p型GaN层和步骤S6中的SiO2钝化层的生长方法为金属有机化学气相沉积法(MOCVD)或分子束外延法(MBE)等高质量成膜方法,步骤S2中的台面刻蚀、步骤S3中的p型GaN层刻蚀和步骤S7中的SiO2刻蚀的方法为电感耦合等离子体刻蚀(ICP)或反应离子刻蚀(RIE),步骤S4中阴极金属、步骤S5中阳极金属和步骤S8中阳极金属场版的蒸镀方法为电子束蒸发(EBE)、磁控溅射(MS)或热蒸发(VTE)。
根据本发明进一步优选的,步骤S1中的n+型GaN层、无掺杂GaN层、p型GaN层和步骤S6中的SiO2钝化层的生长方法均为金属有机化学气相沉积法(MOCVD),步骤S2中的台面刻蚀和步骤S3中的p型GaN层刻蚀方法为电感耦合等离子体刻蚀(ICP),步骤S7中的SiO2刻蚀的方法为反应离子刻蚀(RIE),步骤S4中阴极金属、步骤S5中阳极金属和步骤S8中阳极金属场版的蒸镀方法均为电子束蒸发(EBE)。
根据本发明优选的,步骤S2中,采用电感耦合等离子体刻蚀(ICP)进行台面刻蚀的具体过程为:
A、提供需要进行ICP刻蚀的n+型SiC衬底及其外延材料;
B、在p型GaN层上涂覆光刻胶;
C、利用光刻显影技术,在光刻胶上显露出需要刻蚀的p型GaN层区域;
D、使用电感耦合等离子体装置刻蚀p型GaN层、无掺杂GaN层,刻蚀深度延伸到无掺杂GaN层;
E、使用化学溶液去除涂覆的光刻胶,实现台面隔离的效果。
根据本发明优选的,步骤S3中,采用电感耦合等离子体刻蚀(ICP)对p型GaN层进行中间部分区域刻蚀的具体过程为:
Ⅰ、在p型GaN层和无掺杂GaN层上涂覆光刻胶;
Ⅱ、利用光刻显影技术,在光刻胶上显露出需要刻蚀的p型GaN层区域;
Ⅲ、使用电感耦合等离子体装置刻蚀p型GaN层,直至无掺杂GaN层露出;
Ⅳ、使用化学溶液去除涂覆的光刻胶。
根据本发明优选的,步骤S7及步骤S8中,阳极金属场版制备的具体过程为:
①、在步骤S6中生长的SiO2钝化层上涂覆光刻胶;
②、利用光刻显影技术,在光刻胶上显露出需要刻蚀开孔的SiO2钝化层区域;
③、使用反应离子刻蚀刻蚀SiO2钝化层,直至阳极金属露出;
④、使用电子束蒸发设备蒸镀阳极场版金属Ti/Au合金;
⑤、采用lift-off技术对金属进行剥离。
根据本发明优选的,步骤S4中,形成阴极欧姆接触的退火处理方式为在N2中900℃退火1min。
本发明的有益效果在于:
1.低成本大尺寸特性
GaN肖特基二极管常采用导电性GaN衬底,GaN衬底目前尺寸较小,成本较高。本发明采用导电性SiC衬底,SiC目前尺寸可达到8英寸,具有相对较小的晶格失配度,更好的导热性等优点,价格也远低于GaN衬底,因此,相较于目前的GaN衬底的小尺寸高成本,本发明基于SiC衬底实现GaN垂直器件,具有低成本大尺寸的明显优势。
2.工艺简单,成本更低
本发明通过外延p型GaN层结合刻蚀工艺来形成区域PN结,相比于复杂且昂贵的选区离子注入工艺,该方法工艺简单,成本更低。
3.击穿电压更大
本发明的氮化镓肖特基二极管通过增加漂移区厚度来提升击穿电压,其耐压程度大大提高。另外,本发明在阳极金属和n型GaN层的边缘区域通过形成PN结的方法增加了空间电荷区的宽度,进一步提高了器件的反向击穿电压。
4.高输出电流和低导通阻值
本发明在SiC衬底上实现GaN垂直器件的制备,可实现垂直器件的三维电子通道,从而有效提高输出电流密度,降低器件导通阻值,降低器件尺寸,实现器件高功率小型化的使用。
5.散热能力更好
本发明制备的GaN垂直器件中,电场和电流分布更加均匀,且由于SiC衬底优异于GaN衬底的热导率,器件可更好的将热量传递到热沉,从而实现器件更高的散热特性,提高器件输出功率和可靠性。
附图说明
图1为本发明n+型SiC衬底层示意图;
图2为本发明制备方法步骤S1之后形成的器件结构示意图;
图3为本发明制备方法步骤S2刻蚀之后形成的器件结构示意图;
图4为本发明制备方法步骤S3刻蚀之后形成的器件结构示意图;
图5为本发明制备方法步骤S4蒸镀阴极金属之后形成的器件结构示意图;
图6为本发明制备方法步骤S5蒸镀阳极金属之后形成的器件结构示意图;
图7为本发明制备方法步骤S6生长SiO2钝化层之后形成的器件结构示意图;
图8为本发明制备方法步骤S7 SiO2钝化层开孔之后形成的器件结构示意图;
图9为本发明制备方法步骤S8蒸镀阳极金属场版之后形成的器件结构示意图;
其中,1、n+型SiC衬底,2、n+型GaN层,3、无掺杂GaN层,4、p型GaN层,5、阳极金属,6、阴极金属,7、SiO2钝化层,8、阳极金属场版;
具体实施方式
下面通过实施例并结合附图对本发明做进一步说明,但不限于此。
实施例1:
如图9所示,本实施例提供一种氮化镓肖特基二极管,包括由下到上依次设置的阴极金属6、n+型SiC衬底1、n+型GaN层2、无掺杂GaN层3和p型GaN层4,p型GaN层4上设置有阳极金属5,阳极金属5、p型GaN层4和无掺杂GaN层3上方覆盖有开孔的SiO2钝化层7,SiO2钝化层7开孔处设有阳极金属场版8。
n+型GaN层的厚度为1000nm,掺杂元素Si的掺杂浓度为1×1019cm-3,无掺杂GaN层的厚度为5μm,p型GaN层的厚度为500nm,掺杂元素Mg的掺杂浓度为1×1018cm-3,阴极金属的材料为Ni,阳极金属的材料为Ni/Au合金,阳极金属场版的材料为Ni/Au合金。
实施例2:
一种氮化镓肖特基二极管,结构如实施例1所示,不同之处在于,n+型GaN层的厚度为10nm,掺杂元素Si的掺杂浓度为1×1018cm-3,无掺杂GaN层的厚度为1μm,p型GaN层的厚度为1nm,掺杂元素Mg的掺杂浓度为1×1017cm-3,阴极金属的材料为Ni/Au合金,阳极金属的材料为Pd/Au合金,阳极金属场版的材料为Ti/Au合金。
实施例3:
一种氮化镓肖特基二极管,结构如实施例1所示,不同之处在于,n+型GaN层的厚度为2000nm,掺杂元素Si的掺杂浓度为1×1020cm-3,无掺杂GaN层的厚度为100μm,p型GaN层的厚度为5000nm,掺杂元素Mg的掺杂浓度为1×1019cm-3,阴极金属的材料为Ti/Au合金,阳极金属的材料为Al/Au合金。
实施例4:
一种制备如实施例1所述氮化镓肖特基二极管的制备方法,步骤如下:
S1、在n+型SiC衬底上采用金属有机化学气相沉积法(MOCVD)依次外延生长n+型GaN层、无掺杂GaN层和p型GaN层;
S2、通过电感耦合等离子体刻蚀(ICP)对p型GaN层进行台面刻蚀,刻蚀终点位于无掺杂GaN层,具体过程为:
A、提供需要进行ICP刻蚀的n+型SiC衬底及其外延材料;
B、在p型GaN层上涂覆光刻胶;
C、利用光刻显影技术,在光刻胶上显露出需要刻蚀的p型GaN层区域;
D、使用电感耦合等离子体装置刻蚀p型GaN层、无掺杂GaN层,刻蚀深度延伸到无掺杂GaN层;
E、使用化学溶液去除涂覆的光刻胶,实现台面隔离的效果;
S3、通过电感耦合等离子体刻蚀(ICP)对p型GaN层进行中间部分刻蚀,刻蚀终点位于无掺杂GaN层,具体过程为:
Ⅰ、在p型GaN层和无掺杂GaN层上涂覆光刻胶;
Ⅱ、利用光刻显影技术,在光刻胶上显露出需要刻蚀的p型GaN层区域;
Ⅲ、使用电感耦合等离子体装置刻蚀p型GaN层,直至无掺杂GaN层露出;
Ⅳ、使用化学溶液去除涂覆的光刻胶;
S4、在n+型SiC衬底下方通过电子束蒸发(EBE)蒸镀阴极金属,退火形成欧姆接触,退火处理方式为在N2中900℃退火1min;
S5、在p型GaN层和无掺杂GaN层上方通过电子束蒸发(EBE)蒸镀阳极金属,形成肖特基接触;
S6、在无掺杂GaN层、p型GaN层和阳极金属的上方生长SiO2钝化层;
S7、在SiO2钝化层需要蒸镀阳极金属场版的区域通过光刻显影和反应离子刻蚀(RIE)的方法开孔,然后在SiO2钝化层开孔区域通过电子束蒸发(EBE)蒸镀阳极金属场版(FP),具体方法为:
①、在步骤S6中生长的SiO2钝化层上涂覆光刻胶;
②、利用光刻显影技术,在光刻胶上显露出需要刻蚀开孔的SiO2钝化层区域;
③、使用反应离子刻蚀刻蚀SiO2钝化层,直至阳极金属露出;
④、使用电子束蒸发设备蒸镀阳极场版金属Ti/Au合金;
⑤、采用lift-off技术对金属进行剥离。
以上所述仅为本发明的优选实施例,并非因此限制本发明的专利范围,凡是在本发明的构思下,利用本发明说明书及附图内容所作的等效结构变换,或直接/间接运用在其他相关的技术领域均包括在本发明的专利保护范围内。
Claims (10)
1.一种氮化镓肖特基二极管,其特征在于,包括由下到上依次设置的阴极金属、n+型SiC衬底、n+型GaN层、无掺杂GaN层和p型GaN层,p型GaN层上设置有阳极金属,阳极金属、p型GaN层和无掺杂GaN层上方覆盖有开孔的SiO2钝化层,SiO2钝化层开孔处设有阳极金属场版。
2.如权利要求1所述的氮化镓肖特基二极管,其特征在于,所述氮化镓肖特基二极管包括下列条件之一或多种:
(1)所述n+型GaN层的厚度为10~2000nm,掺杂元素为Si,掺杂浓度为1×1018~1×1020cm-3;
(2)所述无掺杂GaN层的厚度为1~100μm;
(3)所述p型GaN层的厚度为1~5000nm,掺杂元素为Mg,掺杂浓度为1×1017~1×1019cm-3;
(4)所述阴极金属的材料为Ni、Ni/Au合金或Ti/Au合金;
(5)所述阳极金属的材料为Ni/Au合金、Pd/Au合金或Al/Au合金;
(6)所述阳极金属场版的材料为Ni/Au合金或Ti/Au合金。
3.如权利要求2所述的氮化镓肖特基二极管,其特征在于,n+型GaN层的厚度为1000nm,掺杂元素Si的掺杂浓度为1×1019cm-3,无掺杂GaN层的厚度为5μm,p型GaN层的厚度为500nm,掺杂元素Mg的掺杂浓度为1×1018cm-3,阴极金属的材料为Ni,阳极金属的材料为Ni/Au合金,阳极金属场版的材料为Ni/Au合金。
4.如权利要求1所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤如下:
S1、在n+型SiC衬底上依次外延生长n+型GaN层、无掺杂GaN层和p型GaN层;
S2、通过干法刻蚀对p型GaN层进行台面刻蚀,刻蚀终点位于无掺杂GaN层;
S3、通过干法刻蚀对p型GaN层进行中间部分刻蚀,刻蚀终点位于无掺杂GaN层;
S4、在n+型SiC衬底下方蒸镀阴极金属,退火形成欧姆接触;
S5、在p型GaN层和无掺杂GaN层上方蒸镀阳极金属,形成肖特基接触;
S6、在无掺杂GaN层、p型GaN层和阳极金属的上方生长SiO2钝化层;
S7、在SiO2钝化层需要蒸镀阳极金属场版的区域通过光刻显影和干法刻蚀的方法开孔;
S8、在SiO2钝化层开孔区域蒸镀阳极金属场版。
5.如权利要求4所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤S1中的n+型GaN层、无掺杂GaN层、p型GaN层和步骤S6中的SiO2钝化层的生长方法为金属有机化学气相沉积法或分子束外延法,步骤S2中的台面刻蚀、步骤S3中的p型GaN层刻蚀和步骤S7中的SiO2刻蚀的方法为电感耦合等离子体刻蚀或反应离子刻蚀,步骤S4中阴极金属、步骤S5中阳极金属和步骤S8中阳极金属场版的蒸镀方法为电子束蒸发、磁控溅射或热蒸发。
6.如权利要求5所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤S1中的n+型GaN层、无掺杂GaN层、p型GaN层和步骤S6中的SiO2钝化层的生长方法均为金属有机化学气相沉积法,步骤S2中的台面刻蚀和步骤S3中的p型GaN层刻蚀方法为电感耦合等离子体刻蚀,步骤S7中的SiO2刻蚀的方法为反应离子刻蚀,步骤S4中阴极金属、步骤S5中阳极金属和步骤S8中阳极金属场版的蒸镀方法均为电子束蒸发。
7.如权利要求6所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤S2中,采用电感耦合等离子体刻蚀进行台面刻蚀的具体过程为:
A、提供需要进行ICP刻蚀的n+型SiC衬底及其外延材料;
B、在p型GaN层上涂覆光刻胶;
C、利用光刻显影技术,在光刻胶上显露出需要刻蚀的p型GaN层区域;
D、使用电感耦合等离子体装置刻蚀p型GaN层、无掺杂GaN层,刻蚀深度延伸到无掺杂GaN层;
E、使用化学溶液去除涂覆的光刻胶,实现台面隔离的效果。
8.如权利要求7所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤S3中,采用电感耦合等离子体刻蚀对p型GaN层进行中间部分区域刻蚀的具体过程为:
Ⅰ、在p型GaN层和无掺杂GaN层上涂覆光刻胶;
Ⅱ、利用光刻显影技术,在光刻胶上显露出需要刻蚀的p型GaN层区域;
Ⅲ、使用电感耦合等离子体装置刻蚀p型GaN层,直至无掺杂GaN层露出;
Ⅳ、使用化学溶液去除涂覆的光刻胶。
9.如权利要求8所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤S7及步骤S8中,阳极金属场版制备的具体过程为:
①、在步骤S6中生长的SiO2钝化层上涂覆光刻胶;
②、利用光刻显影技术,在光刻胶上显露出需要刻蚀开孔的SiO2钝化层区域;
③、使用反应离子刻蚀刻蚀SiO2钝化层,直至阳极金属露出;
④、使用电子束蒸发设备蒸镀阳极场版金属Ti/Au合金;
⑤、采用lift-off技术对金属进行剥离。
10.如权利要求4所述的氮化镓肖特基二极管的制备方法,其特征在于,步骤S4中,形成阴极欧姆接触的退火处理方式为在N2中900℃退火1min。
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