CN116647187A - Class C voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop - Google Patents
Class C voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop Download PDFInfo
- Publication number
- CN116647187A CN116647187A CN202310464403.0A CN202310464403A CN116647187A CN 116647187 A CN116647187 A CN 116647187A CN 202310464403 A CN202310464403 A CN 202310464403A CN 116647187 A CN116647187 A CN 116647187A
- Authority
- CN
- China
- Prior art keywords
- circuit
- complementary
- nmos
- pmos
- differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 24
- 230000000295 complement effect Effects 0.000 claims abstract description 143
- 230000010355 oscillation Effects 0.000 claims abstract description 52
- 239000003990 capacitor Substances 0.000 claims abstract description 36
- 238000004146 energy storage Methods 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
The invention discloses a C-type voltage-controlled oscillator applied to a low-jitter sub-sampling phase-locked loop, which relates to the technical field of integrated circuits and comprises a power supply circuit, a tank circuit, a PMOS bias circuit, an NMOS bias circuit, a first RC network, a second RC network, a complementary PMOS circuit, a complementary NMOS circuit, a switch capacitor array and a differential oscillation groove; the NMOS bias circuit is used for providing a common mode bias level for the complementary NMOS circuit, the first RC network is used for providing a differential mode bias level for the complementary NMOS circuit, and the complementary NMOS circuit is used for transmitting current pulses to the differential oscillation tank; the PMOS bias circuit is used for providing a common-mode bias level for the complementary PMOS circuit, the second RC network is used for providing a differential-mode bias level for the complementary PMOS circuit, and the complementary PMOS circuit is used for transmitting current pulses to the differential oscillation tank; the switch capacitor array is used for adjusting the capacitor connected into the differential oscillation groove so as to control the output signal of the differential oscillation groove. The invention has the advantages of low power consumption, low phase noise, large output swing, wide tuning range and the like.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a class-C voltage-controlled oscillator applied to a low-jitter sub-sampling phase-locked loop.
Background
With the continuous development and progress of communication technology, in high performance systems and applications such as wireless communication, wired communication, high-speed data conversion, etc., efficient synthesis of low-jitter reference frequencies and clocks is required. Phase-Locked Loop (PLL) has been widely used in the field of integrated circuits as an integrated circuit device capable of generating a high-precision clock signal, in which a sub-sampling PLL obtains a higher Loop gain and lower power consumption by removing a frequency divider structure due to the sub-sampling Phase discriminator, and shows a better compromise between power consumption and jitter, which becomes a new front edge in the current Phase-Locked Loop research field.
The Voltage-controlled oscillator (Voltage-Controlled Oscillator VCO) is used as a core module in the phase-locked loop, and has the main function of providing an output oscillating signal after frequency multiplication of a reference clock for the phase-locked loop, so as to say, the performance of the Voltage-controlled oscillator directly determines the overall performance of the phase-locked loop; the power consumption of the voltage-controlled oscillator generally occupies 80% of the phase-locked loop, determines the power consumption level of the whole chip, and the phase noise of the voltage-controlled oscillator is used as the main noise contribution of the whole circuit after passing through the phase-locked loop, the lower the phase noise of the voltage-controlled oscillator directly causes lower clock jitter, and for the sub-sampling phase-locked loop, the suppression effect is more obvious due to the high loop gain of the sub-sampling phase-locked loop, which is often required to be matched with the lower phase noise of the voltage-controlled oscillator.
Therefore, in order to obtain a phase locked loop with low power consumption and low jitter, it is necessary to design a voltage controlled oscillator with lower power consumption and lower phase noise.
Disclosure of Invention
The invention aims to solve the technical problem of providing a class-C voltage-controlled oscillator which has low power consumption, low phase noise, large output swing and wide tuning range and is applied to a low-jitter sub-sampling phase-locked loop.
In order to solve the technical problems, the invention provides a C-type voltage-controlled oscillator applied to a low-jitter sub-sampling phase-locked loop, which comprises a power supply circuit, a tank circuit, a PMOS bias circuit, an NMOS bias circuit, a first RC network, a second RC network, a complementary PMOS circuit, a complementary NMOS circuit, a switched capacitor array and a differential oscillation groove; the power supply circuit is connected with the complementary NMOS circuit and is used for providing working current; the energy storage circuit is connected with the complementary NMOS circuit and is used for keeping the voltage of a source node of the complementary NMOS circuit constant; the complementary NMOS circuit is respectively connected with the NMOS bias circuit, a first RC network and the differential oscillation tank, the NMOS bias circuit is used for providing a common mode bias level for the complementary NMOS circuit, the first RC network is used for providing a differential mode bias level for the complementary NMOS circuit, and the complementary NMOS circuit is used for transmitting current pulses to the differential oscillation tank; the complementary PMOS circuit is respectively connected with the PMOS bias circuit, a second RC network and the differential oscillation tank, the PMOS bias circuit is used for providing a common-mode bias level for the complementary PMOS circuit, the second RC network is used for providing a differential-mode bias level for the complementary PMOS circuit, and the complementary PMOS circuit is used for transmitting current pulses to the differential oscillation tank; the switch capacitor array is connected with the differential oscillation groove and is used for adjusting the capacitance connected into the differential oscillation groove so as to control the output signal of the differential oscillation groove.
As an improvement of the above scheme, the gate node of the complementary NMOS circuit is connected to the NMOS bias circuit and the first RC network, respectively, and the drain node of the complementary NMOS circuit is connected to the differential oscillating tank and the drain node of the complementary PMOS circuit, respectively; and a grid node of the complementary PMOS circuit is respectively connected with the PMOS bias circuit and the second RC network, and a drain node of the complementary PMOS circuit is connected with the differential oscillation groove.
As an improvement of the above scheme, the common mode bias level provided by the NMOS bias circuit to the complementary NMOS circuit is lower than the common mode voltage of the differential oscillation tank; the PMOS bias circuit provides a common mode bias level to the complementary PMOS circuit that is higher than a common mode voltage of the differential tank.
As an improvement of the scheme, the zero peak differential voltage swing at the two ends of the differential oscillating tank is smaller than or equal to the voltage threshold value of the complementary NMOS circuit and the complementary PMOS circuit.
As an improvement of the scheme, when the grid voltage of the NMOS tube in the complementary NMOS circuit is equal to the threshold voltage of the NMOS tube in the complementary NMOS circuit, the NMOS tube is conducted.
As an improvement of the above scheme, under steady-state conditions, both ends of the differential oscillation tank output constant sine waves.
As an improvement of the above scheme, under the steady-state condition, the current conduction angle and the current pulse shape of the complementary NMOS circuit are the same as those of the complementary PMOS circuit.
As an improvement of the scheme, the output voltage, the current conduction angle and the current pulse shape of the complementary NMOS circuit are related to the ratio of the width to the length of the NMOS tube in the complementary NMOS circuit; the output voltage, current conduction angle and current pulse shape of the complementary PMOS circuit are related to the ratio of the width to the length of the PMOS tube in the complementary PMOS circuit.
As an improvement of the above scheme, the capacitance value of the input differential oscillation tank is inversely proportional to the oscillation frequency of the output signal of the differential oscillation tank.
As an improvement of the above scheme, the tank circuit is arranged between the source node and the ground node of the complementary NMOS circuit to make the voltage of the source node of the complementary NMOS circuit constant
Aiming at the compromise relation among various performance parameters such as phase noise, output swing, tuning range, power consumption and the like of a low-jitter sub-sampling phase-locked loop voltage-controlled oscillator, the invention designs the class-C voltage-controlled oscillator with push-pull bias, and the implementation of the invention has the following beneficial effects:
the invention adopts a C-type structure, modulates the current conduction angle through the tail end heavy load capacitor, and provides lower phase noise performance under the same power consumption;
according to the invention, the bias voltages of the complementary NMOS circuit and the complementary PMOS circuit are adaptively adjusted through the push-pull structure, so that a larger output swing is provided;
the invention adopts the switched capacitor array to obtain a wider tuning range, and can effectively improve the precision, swing and output frequency range of an output clock when being applied to a sub-sampling phase-locked loop.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a class C voltage controlled oscillator of the present invention applied to a low jitter sub-sampling phase locked loop;
FIG. 2 is a waveform diagram of node voltage and node current of a complementary PMOS circuit of the present invention;
fig. 3 is a schematic structural diagram of an embodiment of a switched capacitor array according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1, fig. 1 shows a specific structure of a class C voltage controlled oscillator applied to a low-jitter sub-sampling phase-locked loop according to the present invention, which includes a power supply circuit 1, an energy storage circuit 2, a PMOS bias circuit 3, an NMOS bias circuit 4, a first RC network 5, a second RC network 6, a complementary PMOS circuit 7, a complementary NMOS circuit 8, a switched capacitor array 9, and a differential oscillating tank 10, specifically:
the power supply circuit 1 is connected with the complementary NMOS circuit 8 and is used for providing working current;
the tank circuit 2 is connected with the complementary NMOS circuit 8 and is used for keeping the voltage of the source node of the complementary NMOS circuit 8 constant;
the complementary NMOS circuit 8 is respectively connected with the NMOS bias circuit 4, the first RC network 5 and the differential oscillation tank 10, the NMOS bias circuit 4 is used for providing a common mode bias level for the complementary NMOS circuit 8, the first RC network 5 is used for providing a differential mode bias level for the complementary NMOS circuit 8, and the complementary NMOS circuit 8 is used for transmitting current pulses to the differential oscillation tank 10;
the complementary PMOS circuit 7 is respectively connected with the PMOS bias circuit 3, the second RC network 6 and the differential oscillation tank 10, the PMOS bias circuit 3 is used for providing a common-mode bias level for the complementary PMOS circuit 7, the second RC network 6 is used for providing a differential-mode bias level for the complementary PMOS circuit 7, and the complementary PMOS circuit 7 is used for transmitting current pulses to the differential oscillation tank 10;
the switched capacitor array 9 is connected to the differential oscillating tank 10, and the switched capacitor array 9 is used for adjusting the capacitance connected to the differential oscillating tank 10 to control the output signal of the differential oscillating tank 10.
As can be seen from the above, the class-C voltage-controlled oscillator of the present invention adopts a class-C structure, and provides a differential mode bias level for the complementary MOS transistor pair (i.e., the complementary NMOS circuit 8 and the complementary PMOS circuit 7) acting as a negative resistance by adding the RC network (i.e., the first RC network 5 and the second RC network 6) based on the existing LC voltage-controlled oscillator.
Correspondingly, the grid node of the complementary NMOS circuit 8 is respectively connected with the NMOS bias circuit 4 and the first RC network 5, and the drain node of the complementary NMOS circuit 8 is respectively connected with the differential oscillating tank 10 and the drain node of the complementary PMOS circuit 7; the grid node of the complementary PMOS circuit 7 is respectively connected with the PMOS bias circuit 3 and the second RC network 6, and the drain node of the complementary PMOS circuit 7 is connected with the differential oscillation groove 10.
When the circuit works normally, when the gate voltage of the NMOS tube in the complementary NMOS circuit 8 is equal to the threshold voltage of the NMOS tube in the complementary NMOS circuit 8, the NMOS tube is conducted; this takes only a small fraction of the time during the whole oscillation period, so the tank current essentially consists of current pulses with a narrow pulse width and a high peak value. In order to maintain the pulse current shape, it is important that the NMOS transistor not enter the triode region. Thus, to maximize the output swing, a blocking RC network needs to be introduced to provide a differential mode bias level to the gate nodes of the complementary MOS transistor pairs.
Therefore, the main purpose of the invention is to provide a relatively constant bias voltage which varies with the class-C voltage-controlled oscillator for the complementary MOS transistor pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7), i.e., to use the dc level generated by the bias circuit portion (i.e., PMOS bias circuit 3, NMOS bias circuit 4) as the common-mode bias level; meanwhile, a differential mode bias level which continuously changes along with the output of the C-type voltage-controlled oscillator is also needed, and because the voltage swing of the grid node of the complementary MOS tube pair is directly equal to the output swing of the C-type voltage-controlled oscillator when the C-type voltage-controlled oscillator is directly connected by adopting a lead, and the differential range is overlarge, the invention adopts an RC network (namely a first RC network 5 and a second RC network 6) to filter the output of the C-type voltage-controlled oscillator, and the differential mode bias level is added to the common mode level generated by a bias circuit as a differential mode component after the swing is reduced, and the differential mode bias level and the common mode bias voltage are used as a whole to bias the complementary MOS tube pair.
The current change condition of the C-type voltage-controlled oscillator circuit during operation is as follows: after the class C voltage controlled oscillator is started, the complementary NMOS circuit 8 delivers a current pulse to the differential tank 10 and causes the same pulse to flow through the cross-coupled complementary PMOS circuit 7.
As shown in fig. 2, line a represents the gate node voltage of NMOS transistor MN1, line b represents the gate node voltage of NMOS transistor MN2, line c represents the drain node current of NMOS transistor MN1, line d represents the drain node current of NMOS transistor MN2, and line e represents the source node voltages of NMOS transistors MN1, MN 2. Under steady state conditions, the voltage waveforms at the two ends of the differential oscillating tank 10 (i.e. the gate nodes of the complementary NMOS circuit 8 and the complementary PMOS circuit 7) remain stable, and a constant sine wave is output. At this time, the tail current source (i.e. the source node of the complementary NMOS circuit 8) has a narrow and high peak current conduction angle and current pulse shape due to the large load capacitance C0, so that the current utilization efficiency is improved, and the opposite complementary NMOS circuit 8 and complementary PMOS circuit 7 have identical current conduction angle and current pulse shape, i.e. the current conduction angle and current pulse shape of the complementary NMOS circuit 8 are identical to the current conduction angle and current pulse shape of the complementary PMOS circuit 7.
The following describes the power supply circuit 1, the energy storage circuit 2, the PMOS bias circuit 3, the NMOS bias circuit 4, the first RC network 5, the second RC network 6, the complementary PMOS circuit 7, the complementary NMOS circuit 8, the switched capacitor array 9, and the differential oscillation tank 10 in further detail:
1. power supply circuit
In the invention, the NMOS tube MN0 is used as a power supply circuit, and can provide working current for the main circuit of the whole C-type voltage-controlled oscillator.
2. Energy storage circuit
The tank circuit is disposed between the source node of the complementary NMOS circuit 8 and the ground node so as to make the voltage of the source node of the complementary NMOS circuit 8 constant. Wherein, the energy storage circuit is preferably an energy storage capacitor C0.
Thus, by providing a relatively large storage capacitor C0 between the source node of the complementary NMOS circuit 8 and the ground node, the voltage at the source node can be made nearly constant.
3. PMOS bias circuit
The PMOS bias circuit includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4, and a current branch formed by the third PMOS transistor MP3 and the fourth PMOS transistor MP4 can provide a common mode bias level higher than the common mode voltage of the differential oscillating tank 10. That is, the PMOS bias circuit 3 supplies the complementary PMOS circuit 7 with a common mode bias level higher than the common mode voltage of the differential oscillation tank 10.
4. NMOS bias circuit
The NMOS bias circuit includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4, where the current branch formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4 can provide a common mode bias level lower than the common mode voltage of the differential oscillating tank 10. That is, the common-mode bias level provided by the NMOS bias circuit 4 to the complementary NMOS circuit 8 is lower than the common-mode voltage of the differential oscillation tank 10.
For example, if the output level of the class C voltage controlled oscillator is 0 to 1.2V, the center level is 0.6V; the bias of the NMOS bias circuit 4 should be less than 0.6V (e.g. 0.5V), so as to ensure that the common-mode bias level provided by the NMOS bias circuit 4 to the complementary NMOS circuit 8 is lower than the common-mode voltage of the differential oscillation tank 10; and the bias of the PMOS bias circuit 3 should be greater than 0.6V (e.g. 0.7V), so as to ensure that the common-mode bias level provided by the PMOS bias circuit 3 to the complementary PMOS circuit 7 is higher than the common-mode voltage of the differential oscillating tank 10.
5. First RC network
The first RC network 5 includes a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2, where the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 together play roles in blocking direct current and conducting alternating current, so that the output direct current component is suppressed, and no common mode bias level is provided for the complementary NMOS circuit 8.
6. Second RC network
The second RC network 6 includes a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4, where the third capacitor C3, the fourth capacitor C4, the third resistor R3, and the fourth resistor R4 together play roles in blocking direct current and conducting alternating current, so that the output direct current component is suppressed, and no common mode bias level is provided for the complementary PMOS circuit 7.
7. Complementary PMOS circuit
The PMOS circuit 7 comprises a first PMOS tube MP1 and a second PMOS tube MP2; the first PMOS transistor MP1 and the second PMOS transistor MP2 are complementary PMOS pairs, and can provide negative resistance for the differential oscillating tank 10, so as to maintain the oscillation continuously without attenuation, and play a role in output limiting.
It should be noted that the output voltage, the current conduction angle, and the current pulse shape of the complementary PMOS circuit 7 are related to the ratio of the width to the length of the PMOS transistor in the complementary PMOS circuit 7.
8. Complementary NMOS circuit
The NMOS circuit 8 comprises a first NMOS tube MN1 and a second NMOS tube MN2; the first NMOS transistor MN1 and the second NMOS transistor MN2 are complementary NMOS pairs, and can also provide negative resistance for the differential oscillation tank 10, so as to maintain the oscillation continuously without attenuation, and play a role in output clipping.
The output voltage, the current conduction angle, and the current pulse shape of the complementary NMOS circuit 8 are related to the ratio of the width to the length of the NMOS transistor in the complementary NMOS circuit 8.
9. Switched capacitor array (Switch Capacitor Array SCA)
As shown in fig. 3, since it is difficult to adjust inductance in an integrated circuit, tuning of the class C voltage controlled oscillator frequency can be achieved by adjusting the capacitance of the variable capacitor and the number of switched capacitor arrays. In order to widen the tuning range of the class C voltage controlled oscillator, outputting more different frequencies, the invention uses a switched capacitor array for tuning 9.
10. Differential oscillating tank
The inductor L, the first voltage-controlled capacitor Cv1 and the second voltage-controlled capacitor Cv2 together form a differential oscillation tank 10 (i.e., LC resonance tank), where the first voltage-controlled capacitor Cv1 and the second voltage-controlled capacitor Cv2 are used as adjustable capacitors, so as to effectively control the time constant of the resonance of the class-C voltage-controlled oscillator, thereby controlling the oscillation frequency of the output signal.
As shown in fig. 3, the capacitance value of the access differential oscillation tank 10 can be controlled by giving different control bits, so as to change the time constant of resonance; wherein the capacitance value of the switched-in differential oscillation tank 10 is inversely proportional to the oscillation frequency of the output signal of the differential oscillation tank 10, i.e. the more switched-in capacitances, the lower the oscillation frequency.
More preferably, the zero peak differential voltage swing across the differential tank 10 is less than or equal to the voltage thresholds of the complementary NMOS circuit 8 and the complementary PMOS circuit 7.
To minimize the effect of phase noise, the zero peak differential voltage swing across the differential tank 10 must be at or below the voltage threshold of the complementary CMOS pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7). Therefore, the invention adopts an improved push-pull structure to generate bias voltage for the circuit, and has the advantages of adapting to larger voltage swing; by introducing additional RC networks (first RC network 5, second RC network 6), differential mode bias levels are provided for the gate nodes of the CMOS pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7), allowing for a larger oscillator output swing before the complementary CMOS pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7) is pushed into the triode region. In the NMOS bias circuit 4 and the PMOS bias circuit 3, both NMOS tubes and PMOS tubes are used as level shifters, and the common mode part of the output voltage is used for realizing self-adaptive adjustment of the bias voltage, so that the impedance of the oscillating tank under the lower common mode bias level can be well kept, and a more stable common mode voltage is obtained.
In summary, aiming at the trade-off relation among various performance parameters such as phase noise, output swing, tuning range, power consumption and the like of a pressure-controlled oscillator in a low-jitter sub-sampling phase-locked loop, the invention designs a class-C pressure-controlled oscillator with push-pull bias; the invention can provide lower phase noise than other types of oscillators under the condition of meeting low power consumption; the bias voltages of the complementary NMOS circuit and the complementary PMOS circuit are adaptively adjusted through the push-pull structure, and a larger output swing is provided; and a wider tuning range is obtained by adopting a switched capacitor array, so that the precision, the swing and the output frequency range of an output clock can be effectively improved when the switched capacitor array is applied to a sub-sampling phase-locked loop.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (10)
1. The class-C voltage-controlled oscillator is characterized by comprising a power supply circuit, a tank circuit, a PMOS bias circuit, an NMOS bias circuit, a first RC network, a second RC network, a complementary PMOS circuit, a complementary NMOS circuit, a switched capacitor array and a differential oscillation tank;
the power supply circuit is connected with the complementary NMOS circuit and is used for providing working current;
the energy storage circuit is connected with the complementary NMOS circuit and is used for keeping the voltage of a source node of the complementary NMOS circuit constant;
the complementary NMOS circuit is respectively connected with the NMOS bias circuit, a first RC network and the differential oscillation tank, the NMOS bias circuit is used for providing a common mode bias level for the complementary NMOS circuit, the first RC network is used for providing a differential mode bias level for the complementary NMOS circuit, and the complementary NMOS circuit is used for transmitting current pulses to the differential oscillation tank;
the complementary PMOS circuit is respectively connected with the PMOS bias circuit, a second RC network and the differential oscillation tank, the PMOS bias circuit is used for providing a common-mode bias level for the complementary PMOS circuit, the second RC network is used for providing a differential-mode bias level for the complementary PMOS circuit, and the complementary PMOS circuit is used for transmitting current pulses to the differential oscillation tank;
the switch capacitor array is connected with the differential oscillation groove and is used for adjusting the capacitance connected into the differential oscillation groove so as to control the output signal of the differential oscillation groove.
2. A class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop as claimed in claim 1,
the grid node of the complementary NMOS circuit is respectively connected with the NMOS bias circuit and the first RC network, and the drain node of the complementary NMOS circuit is respectively connected with the differential oscillating tank and the drain node of the complementary PMOS circuit;
and a grid node of the complementary PMOS circuit is respectively connected with the PMOS bias circuit and the second RC network, and a drain node of the complementary PMOS circuit is connected with the differential oscillation groove.
3. A class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop as claimed in claim 1 or 2,
the common mode bias level provided by the NMOS bias circuit to the complementary NMOS circuit is lower than the common mode voltage of the differential oscillation tank;
the PMOS bias circuit provides a common mode bias level to the complementary PMOS circuit that is higher than a common mode voltage of the differential tank.
4. The class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop of claim 1 or 2, wherein zero peak differential voltage swing across the differential tank is less than or equal to the voltage thresholds of the complementary NMOS and complementary PMOS circuits.
5. The class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop of claim 1 or 2, wherein the NMOS transistors in the complementary NMOS circuit are turned on when their gate voltages are equal to their threshold voltages.
6. A class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop as claimed in claim 1 or 2 wherein under steady state conditions a constant sine wave is output across the differential tank.
7. The class-C voltage controlled oscillator for a low jitter sub-sampling phase locked loop of claim 1 or 2, wherein the current conduction angle and current pulse shape of the complementary NMOS circuit is the same as the current conduction angle and current pulse shape of the complementary PMOS circuit under steady state conditions.
8. A class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop as claimed in claim 1 or 2,
the output voltage, the current conduction angle and the current pulse shape of the complementary NMOS circuit are related to the ratio of the width to the length of the NMOS tube in the complementary NMOS circuit;
the output voltage, current conduction angle and current pulse shape of the complementary PMOS circuit are related to the ratio of the width to the length of the PMOS tube in the complementary PMOS circuit.
9. The class C voltage controlled oscillator for a low jitter sub-sampling phase locked loop of claim 1, wherein a capacitance value of an access to the differential oscillation tank is inversely proportional to an oscillation frequency of an output signal of the differential oscillation tank.
10. The class C voltage controlled oscillator of claim 1, wherein the tank circuit is disposed between a source node of the complementary NMOS circuit and a ground node to maintain a constant voltage at the source node of the complementary NMOS circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310464403.0A CN116647187A (en) | 2023-04-26 | 2023-04-26 | Class C voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310464403.0A CN116647187A (en) | 2023-04-26 | 2023-04-26 | Class C voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116647187A true CN116647187A (en) | 2023-08-25 |
Family
ID=87642499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310464403.0A Pending CN116647187A (en) | 2023-04-26 | 2023-04-26 | Class C voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116647187A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117277968A (en) * | 2023-11-20 | 2023-12-22 | 深圳市华普微电子股份有限公司 | Differential complementary variable capacitor for voltage-controlled oscillator |
-
2023
- 2023-04-26 CN CN202310464403.0A patent/CN116647187A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117277968A (en) * | 2023-11-20 | 2023-12-22 | 深圳市华普微电子股份有限公司 | Differential complementary variable capacitor for voltage-controlled oscillator |
| CN117277968B (en) * | 2023-11-20 | 2024-03-26 | 深圳市华普微电子股份有限公司 | Differential complementary variable capacitor for voltage-controlled oscillator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7348818B2 (en) | Tunable high-speed frequency divider | |
| KR19990025790A (en) | Multiple Feedback Loop Ring Oscillator and its Delay Cells | |
| CN108199687B (en) | Transconductance linearization broadband LC type voltage-controlled oscillator and adjustable capacitor array circuit | |
| KR100691369B1 (en) | Voltage controlled oscillator with body bias controlling | |
| US7683681B2 (en) | Injection-locked frequency divider embedded an active inductor | |
| TWI323565B (en) | Voltage-controlled oscillator | |
| CN116647187A (en) | Class C voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop | |
| US10355643B2 (en) | Differential Colpitts voltage-controlled oscillator | |
| CN108494397B (en) | Voltage-controlled oscillator circuit and phase-locked loop | |
| JP2010010864A (en) | Voltage-controlled oscillator | |
| CN101572539A (en) | Bias-voltage generating circuit for high-speed narrow-band voltage-controlled oscillators (VCO) | |
| US6067336A (en) | Charge pump circuit | |
| CN112242841A (en) | Phase-locked loop circuit with high power supply noise rejection ratio | |
| EP1831988A2 (en) | Differential oscillator device with pulsed power supply, and related driving method | |
| KR101750450B1 (en) | Voltage-controlled oscillator | |
| CN111628725B (en) | LC voltage-controlled oscillator circuit with noise circulation | |
| KR100431999B1 (en) | A Self-Regulating Voltage Controlled Oscillator | |
| CN108599762B (en) | Dual-mode low-power-consumption wide-locking-range injection locking frequency divider | |
| CN213426145U (en) | Phase-locked loop circuit with high power supply noise rejection ratio | |
| CN111162736B (en) | Voltage controlled oscillator | |
| CN117978093A (en) | Class C voltage-controlled oscillator with low phase noise | |
| Xu et al. | Fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and 35 ps jitter | |
| Stoopman et al. | A sub-GHz UWB pulse generator for wireless implantable medical devices | |
| CN110504956A (en) | A kind of broadband pre-divider that power consumption is adaptive | |
| CN116961585B (en) | Self-biased voltage-controlled oscillator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |