CN116646825A - VCSEL array based on nano-wire axial heterojunction and preparation method thereof - Google Patents
VCSEL array based on nano-wire axial heterojunction and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a VCSEL array based on a nanowire axial heterojunction and a preparation method thereof, belonging to the technical field of semiconductor photoelectrons. The characteristic temperature is improved by utilizing the quantum effect of the nano disc; the diameter of the nanowire is smaller than 1 mu m, so that the nanowire has the advantage of single transverse mode emission naturally; the nanowires can release stress in two dimensions perpendicular to the growth direction, have higher tolerance to strain, and can realize larger-range material composition and wavelength regulation; the nanowire is of an epitaxial growth single crystal structure, and the problem of side wall damage is avoided.
Description
Technical Field
The invention relates to a VCSEL array based on a nanowire axial heterojunction and a preparation method thereof, belonging to the technical field of semiconductor photoelectrons.
Background
The Vertical-cavity surface-emitting laser (VCSEL) is a novel semiconductor laser, and has the advantages of being capable of performing on-chip test in the light emitting direction perpendicular to a substrate, low in threshold current, high in modulation rate, capable of working in a single longitudinal mode, easy to couple with an optical fiber in a circular light spot and the like, and is widely applied to the fields of optical communication, optical interconnection, intelligent sensing, quantum precision measurement and the like.
In recent years, the importance of quantum precision measurement technology and high-speed optical communication is increasingly highlighted, quantum precision measurement is an important direction of world-wide layout, and high-speed optical communication is a necessary development trend in the big data era. These two directions present significant challenges to the performance of VCSEL high temperature operation, single mode, spectral linewidth, etc. Facing these challenges, researchers have done a great deal of research effort, mainly in the following areas: (1) By regulating the epitaxial structure, the temperature characteristics of the VCSEL are improved: for the regulation of an epitaxial structure, the most successful scheme is a gain-cavity mode mismatch technology proposed by a catharanthus roseus optical machine. In GaAs-based VCSELs, the temperature drift coefficient of the cavity mode is much smaller than that of the gain spectrum, which can red shift faster at high temperatures. By accurately measuring the two temperature drift coefficients, the gain spectrum peak is positioned at the short wavelength on the left side of the cavity mode at room temperature, and when the VCSEL works at high temperature, the gain spectrum peak is red shifted to match with the cavity mode, so that the temperature characteristic of the device is improved. (2) The single-mode characteristic and the spectral linewidth of the VCSEL are regulated and controlled by changing the size of the oxidation hole: by reducing the diameter of the oxidation hole, the occurrence of a higher-order transverse mode can be effectively inhibited, and a higher side mode inhibition ratio is achieved. For example, sandia laboratories in the United states have achieved side mode rejection ratios of 35dB and line widths of less than 50MHz through oxide holes less than 5 μm in diameter. (3) Thirdly, dielectric film DBR or multi-resonant cavity coupling is adopted, so that the limitation on photons is enhanced, and narrow linewidth emission is realized.
Through the efforts in the aspects, the single-mode characteristics, the spectral linewidth and other performance indexes of the VCSEL are obviously improved. But limited by the physical properties of the material itself and the state of the art, existing VCSELs also suffer from several disadvantages: (1) The high-temperature working characteristic of the VCSEL is not stable enough, and the temperature interval with optimal VCSEL performance is smaller due to the huge difference between the cavity mode temperature drift coefficient and the gain spectrum, so that a VCSEL device insensitive to temperature is difficult to realize; (2) In order to realize single transverse mode operation, the oxidation holes need to be less than 3 mu m, so that the difficulty of a wet oxidation process is greatly increased, and the yield of chips is reduced; (3) Existing commercial VCSELs are GaAs-based VCSELs, and an active region is generally InGaAs, inGaAlAs or InGaAlP quantum well. Due to the limitation of a material system, the light emitting wavelength of the GaAs-based VCSEL is often limited to 620-1064 nm, and beyond the range, a large number of defects can be generated in a quantum well active region due to high strain, so that the threshold current, the light emitting power, the service life and the like of the device are seriously influenced. (4) The preparation of the GaAs-based VCSEL needs to adopt a dry etching technology to etch a table surface with the thickness of more than 3 mu m, and the dry etching can leave a large amount of etching damage on the side wall of the table surface, thereby being unfavorable for improving the performance of the device and possibly influencing the wet oxidation process. Aiming at the problems in the prior art, a VCSEL array based on a nano-wire axial heterojunction and a preparation method are designed, the temperature stability and single-mode characteristics of the VCSEL are improved through the characteristics of quantum effect, high strain tolerance and the like of the nano-wire, the light-emitting wavelength range is enlarged, and meanwhile, the problem of dry etching damage is solved to be an urgent need at present.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a VCSEL array based on a nano-wire axial heterojunction and a preparation method thereof, and solves the problems in the prior art.
The VCSEL array based on the nanowire axial heterojunction comprises a first electrode, an insulating buried layer, a mask layer, a substrate and a second electrode which are sequentially arranged, wherein nanowires are grown in the insulating buried layer and the mask layer, each nanowire is vertically arranged to form a nanowire array, and each nanowire in the nanowire array independently forms a VCSEL structure.
Further, the nanowire is formed by an axial heterostructure, comprising, in order from bottom to top: an N-GaAs segment, an N-DBR segment, a lower confinement segment, an active region, an upper confinement segment, a P-DBR segment, and a P+ GaAs contact segment.
Further, the first electrode is located above the insulating buried layer and forms ohmic contact with the P+ GaAs contact section of the nanowire, and the second electrode is located below the substrate and forms ohmic contact with the substrate.
Further, the N-GaAs section, the N-DBR section, the lower confinement section, the active region, the upper confinement section, the P-DBR section and a part of the P+ GaAs contact section of the nanowire are buried by the insulating buried layer, and the rest part of the P+ GaAs contact section is exposed on the insulating buried layer and used for forming ohmic contact with the first electrode.
Further, the first electrode comprises two layers, one layer is an ITO transparent electrode, ohmic contact is formed between the ITO transparent electrode and the P+GaAs contact section, the other layer is a metal electrode positioned on the ITO transparent electrode, and electrode openings are formed in the metal electrode at the position of the array point corresponding to the nanowire so as to ensure that laser energy can exit through the electrode openings.
Further, the mask layer is provided with holes which are arranged periodically, the diameters of the holes are the same as those of the nanowires, the nanowires grow out of the holes, and the minimum period of the hole arrangement is square, rectangle, diamond or parallelogram.
Further, the N-DBR section and the P-DBR section are made of Al x Ga 1-x As and Al y Ga 1-y The As nano-discs are formed by periodical overlapping, wherein x and y are Al components of AlGaAs respectively, and x is not equal to y, so that Al x Ga 1-x As and Al y Ga 1-y As has different refractive indexes, the diameter of the disk is equal to that of the nanowire, and the N-DBR section and the P-DBR section of the nanowire are formed by periodical overlapping.
Further, the active region is a single-layer nano-disc or two kinds of periodically overlapped nano-discs, and the diameter of the discs is the diameter of the nano-wires.
Further, the mask layer is made of SiO 2 Or SiNx materialThe insulating buried layer is SiO 2 One or more combinations of SiNx insulating dielectric materials.
The invention relates to a preparation method of a VCSEL array based on a nano-axis axial heterojunction, which comprises the following steps:
s1: firstly, selecting a substrate, and depositing a mask layer on the surface of the substrate by adopting a magnetron sputtering or plasma-assisted chemical vapor deposition method;
s2: forming an open hole pattern on the mask layer, and forming an open hole on the mask layer to the surface of the substrate to serve as a mask for the growth of the nanowire array;
s3: the nanowire array is grown segment by segment in an autocatalysis mode, and the length of each segment is accurately controlled by regulating and controlling the growth rate and the growth time;
s4: after the growth of the nanowire array is completed, depositing an insulating buried layer, and controlling the thickness of the insulating buried layer by controlling the deposition rate and time to cover the nanowire array;
s5: etching the top of the insulating buried layer to expose part of the P+ GaAs contact section, and cleaning the surface of the P+ GaAs contact section to remove impurities remained on the surface in the etching process;
s6: depositing an ITO transparent electrode on the insulating buried layer and forming ohmic contact with the P+ GaAs contact section;
s7: forming a metal electrode pattern on the surface of the ITO transparent electrode, depositing a metal electrode on the surface of the ITO, and forming an opening at a lattice point of the nanowire array for laser emission;
s8: thinning, polishing and cleaning a substrate, and then preparing a metal electrode on the back of the substrate, wherein the metal electrode is used as a negative electrode of the nano array;
s9: scribing and splitting according to the requirement to form a nanowire array chip, and completing the preparation.
Compared with the prior art, the invention has the following beneficial effects:
according to the VCSEL array based on the axial heterojunction of the nanometer tube and the preparation method thereof, the active region formed by the nanometer disc has quantum effects in three dimensions, and compared with a traditional VCSEL structure, the VCSEL array based on the axial heterojunction of the nanometer tube has lower threshold current and higher characteristic temperature, the temperature characteristic of the device is effectively improved, and the device can work at high temperature.
The diameter of the nanowire is smaller than 1 mu m, single transverse mode emission can be realized naturally, and the high-order transverse mode is not required to be restrained by reducing the diameter of an oxidation hole, so that the nanowire VCSEL provided by the invention omits the step of preparing the oxidation hole, simplifies the preparation process of a device and reduces the preparation difficulty of the device.
The nanowire can release stress in XY two directions through elastic deformation, and the active region can achieve high strain without strain relaxation, so that the material composition of the nano disk forming the active region can be changed in a larger range, and accordingly, the luminescence wavelength of the VCSEL can be adjusted in a larger range;
the nanowire is a natural waveguide structure, the refractive index of the nanowire is far greater than that of the buried dielectric film, and photons can be limited in the nanowire and can propagate along the axial direction. The nanowire is an epitaxially grown monocrystal, the side wall is free from etching damage and the like, photons can be better limited, and the problems that in the prior art, the VCSEL characteristic temperature is low, a single transverse mode is difficult to realize, the wavelength range which can be realized is narrow, and the side wall is damaged by etching are solved. Simultaneously, the selectable VCSEL emission wavelength range is expanded, and etching damage generated in the traditional VCSEL preparation process is avoided.
Drawings
FIG. 1 is a schematic diagram of a nanowire axial heterojunction-based VCSEL array and a fabrication method thereof;
FIG. 2 is a schematic diagram of a nanowire VCSEL array based on nanowire axial heterojunction and a method for fabricating the same according to the present invention;
FIG. 3 is a nanowire VCSEL structure of embodiment 1 of the present invention;
FIG. 4 is a periodic opening arrangement of the mask layer and the upper electrode in embodiment 1 of the present invention;
FIG. 5 is an N-DBR reflection spectrum in example 1 of the present invention;
FIG. 6 is a cavity mode of nanowire VCSELs in embodiment 1 of the present invention;
in the figure: 1. electrode opening; 2. a first electrode; 3. an ITO transparent electrode; 4. a nanowire; 5. an insulating buried layer; 6. a mask layer; 7. a substrate; 8. a second electrode; 41. p+ GaAs contact section; 42. a P-DBR section; 43. an upper limiting section; 44. an active region; 45. a lower limiting section; 46. an N-DBR section; 47. N-GaAs segment.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
as shown in fig. 1, the VCSEL array based on a nanowire axial heterojunction according to the present invention includes a first electrode 2, an insulating buried layer 5, a mask layer 6, a substrate 7, and a second electrode 8, which are sequentially disposed, wherein nanowires 4 are grown in the insulating buried layer 5 and the mask layer 6, each nanowire 4 is vertically arranged to form a nanowire array, and each nanowire 4 in the nanowire array forms a VCSEL structure individually.
The substrate 7 is an N-type GaAs substrate to facilitate the growth of the nanowires 4.
The mask layer 6 is SiO 2 Or SiNx material, is perforated by photolithography and dry etching techniques to expose the substrate 7. The mask layer 6 is about 20-30 nm thick, and is not too thick to affect the growth of the nanowires 4. The opening diameter is the same as the nanowire 4 diameter. The openings are arranged periodically, and the minimum period can be square, rectangle, diamond or parallelogram.
As shown in fig. 2, the nanowire 4 is formed of an axial heterostructure comprising, in order from bottom to top: an N-GaAs segment 47, an N-DBR segment 46, a lower confinement segment 45, an active region 44, an upper confinement segment 43, a P-DBR segment 42, and a P+ GaAs contact segment 41. The diameter of the nanowire 4 can be any value between 100nm and 1000nm according to the requirement;
the N-GaAs segment 47 serves to mask etching damage to the surface of the substrate 7 caused by the opening of the mask layer 6.
The first electrode 2 is located above the insulating buried layer 5 and forms an ohmic contact with the p+ GaAs contact section 41 of the nanowire 4, and the second electrode 8 is located below the substrate 7 and forms an ohmic contact with the substrate 7.
The second electrode 8 is located on the back of the N-GaAs substrate and is the negative electrode of this VCSEL array. The first electrode 2 is located above the insulating buried layer 5 and is the positive electrode of this VCSEL array. The first electrode 2 comprises two layers, the first layer is an ITO transparent electrode 3 positioned above an insulating buried layer 5, ohmic contact is formed with a P+ GaAs contact section 41, and the second layer is a metal electrode positioned above the ITO transparent electrode 3. The second layer is perforated at a lattice point of the nanowire VCSEL array, the perforation diameter being larger than the nanowire diameter to ensure that laser energy is emitted from the perforation.
The insulating buried layer 5 buries the N-GaAs section 47, the N-DBR section 46, the lower confinement section 45, the active region 44, the upper confinement section 43, the P-DBR section 42, and a portion of the p+ GaAs contact section 41 of the nanowire 4, and the remaining portion of the p+ GaAs contact section 41 is exposed above the insulating buried layer 5 for ohmic contact with the first electrode 2.
The first electrode 2 comprises two layers, one layer is an ITO transparent electrode 3, the ITO transparent electrode 3 and the P+ GaAs contact section 41 form ohmic contact, the other layer is a metal electrode positioned above the ITO transparent electrode 3, and the metal electrode is provided with electrode holes 1 at the corresponding array points of the nanowires 4 so as to ensure that laser energy can exit through the electrode holes 1.
The mask layer 6 has openings arranged periodically, the diameter of the openings is the same as that of the nanowires 4, the nanowires 4 grow out of the openings, and the minimum period of the openings is square, rectangle, diamond or parallelogram.
The N-DBR section 46 and the P-DBR section 42 are Al x GaAs/Al y GaAs periodic structure, x+.y and the difference between them is larger to create a higher refractive index difference. Al (Al) x GaAs and Al y GaAs is a nano-disk with thickness lambda/4 n (lambda is the luminescence wavelength of VCSEL, n is the refractive index of the disk), and the disks are periodically overlapped to form a DBR structure. Al (Al) x GaAs and Al y The band gap of GaAs is greater than the photon energy hc/λ (h is the planck constant and c is the speed of light in vacuum) to avoid photon absorption by the DBR. Period number N of N-DBR n Number n of periods greater than P-DBR p To ensure that the laser is emitted from the upper end surface of the nanowire.
The active region 44 is a single-layer nanodisk or two kinds of nanodisks that overlap periodically, the disk diameter being the nanowire 4 diameter.
The mask layer 6 is made of SiO 2 Or SiN x The material is used as a material for the glass,the insulating buried layer 5 is SiO 2 、SiN x A combination of one or more insulating dielectric materials.
The active region 44 may be a single nanodisk or may be two nanodisks that overlap periodically. The emission wavelength of a single nanodisk corresponds to the emission wavelength of a VCSEL, called quantum disk, and periodically overlapping nanodisks are divided into quantum well disks whose band gap corresponds to the emission wavelength of the VCSEL and quantum barrier disks for confining electrons and holes in the quantum well disks.
The upper and lower limiting sections 43, 45 have two functions: the first is to confine carriers in the active region 44 and the second is to control the cavity length by adjusting the lengths of the two segments. The sum of the equivalent lengths of the upper confinement section 43, the active region 44, and the lower confinement section 45 is equal to an integer multiple mλ of the VCSEL emission wavelength, m being a positive integer, and not too large to avoid multi-longitudinal mode lasing.
The P + GaAs contact section 41 has a very high P-type doping concentration for forming a good ohmic contact with the upper electrode.
The light emission wavelength of the nanowire 4 is any one wavelength in the range of 650nm to 1310 nm.
The diameter of the nanowire 4 is smaller than 1000nm and larger than 100nm.
The VCSEL array of the invention utilizes the quantum effect of the nano disk to improve the characteristic temperature; the diameter of the nanowire is smaller than 1 mu m, so that the nanowire has the advantage of single transverse mode emission naturally; the nanowires can release stress in two dimensions perpendicular to the growth direction, have higher tolerance to strain, and can realize larger-range material composition and wavelength regulation; the nanowire is of an epitaxial growth single crystal structure, and the problem of side wall damage is avoided.
The nanowire array for a particular wavelength is illustrated below:
example 1:
the embodiment of the invention is a nanowire VCSEL array with the luminescence wavelength of 850nm, and the structure of the nanowire VCSEL array is shown in figure 1, and the nanowire VCSEL array comprises an N-GaAs substrate, a mask layer 6, a nanowire VCSEL array, an insulating buried layer 5, a first electrode 2 and a second electrode 8. Wherein the first electrode 2 is an upper electrode, the second electrode 8 is a lower electrode, each nanowire 4 in the array can be seen as an independent nanowire 4, and the specific structure of the nanowire 4 is shown in fig. 3.
The doping concentration of the N-GaAs substrate is 2E18 cm -3 ～4E18 cm -3 So as to form a good ohmic contact with the second electrode 8.
The mask layer 6 is made of SiO 2 Or SiN x The thickness is 20-30 nm, and is not too thick so as not to influence the growth of the nanowire array. An opening pattern is formed on the mask layer 6 by adopting a stepping photoetching machine or an electron beam exposure technology, and an opening is formed on the surface of the GaAs substrate by adopting a dry etching technology and is used as a mask for the growth of the nanowire array. The periodic arrangement of the openings determines the nanowire VCSEL array alignment rules. Alternatively, the openings are arranged in a square periodic arrangement as shown in FIG. 4, with a diameter of 300nm.
Each nanowire VCSEL in the array has the same structure: comprising an N-GaAs section 47, an N-DBR section 46, a lower confinement section 45, an active region 44, an upper confinement section 43, a P-DBR section 42, a P + GaAs contact section 41.
In order to mask the etching damage of the substrate surface in the openings, the length of the N-GaAs segment 47 is greater than 200nm, and alternatively, the length of the N-GaAs segment 47 is 200nm.
The N-DBR section 46 is 300nm diameter Al 0.2 GaAs and Al 0.9 The GaAs nano discs are formed by periodical overlapping, the band gaps of the two materials are larger than photon energy with the wavelength of 850nm, photons cannot be absorbed, and when the thickness of the two discs is lambda/4 n and lambda=850 nm, al is contained in the two discs 0.2 GaAs and Al 0.9 The refractive index of GaAs can be calculated from the MSEO model:
obtaining Al 0.2 GaAs and Al 0.9 The thicknesses of the GaAs nano-disc are 58.3nm and 67.4nm respectively, and according to a transmission matrix method, the absorption loss of N-type doping on photons is considered, and the N-DBR reflection spectrum with 40 periods can be obtained as shown in FIG. 5. At 850nm, the reflectivity is more than 99.9 percent, and the reflection spectrum width with the reflectivity more than 99 percent reaches55nm, can meet the optical feedback requirement of VCSEL. Differently, the laser needs to exit the P-DBR, requiring the reflectivity of the P-DBR to be smaller than the N-DBR, optionally taking 25 cycles of the P-DBR.
The active region 44 has an emission wavelength of about 850nm, and In may be used to increase the gain and power of the VCSEL 0.1 GaAs/Al 0.2 The periodic structure of alternate growth of GaAs, optionally with a cycle number of 5, comprises 5 In 0.1 GaAs quantum well disk (each 5nm thick), 6 Al 0.2 GaAs quantum barrier discs (8 nm each thickness). The total thickness of the active region is 73nm.
The upper confinement section 43 and the lower confinement section 45 have a band gap width larger than that of the active region 44, so that Al is used as a material 0.5 The sum of the equivalent lengths of the GaAs, upper confinement section 43, active region 44, lower confinement section 45 is the cavity length of the VCSEL, equal to an integer multiple of wavelength λ.850nm VCSELs are typically used for high speed optical communications, where the cavity length should be as short as possible, so the cavity length is taken to be λ. Al (Al) 0.5 GaAs has a refractive index of 3.38 at 850nm, in 0.1 GaAs/Al 0.2 The equivalent refractive index of GaAs multi-quantum well is 3.64, the equivalent length is the length of each segment x the sum of the refractive indices: sigma (sigma) i L i ×n i . The equivalent length of the active region 44 is calculated to be 345.8nm, and the lengths of the upper and lower confinement sections 43 and 45 should be 292.1nm, respectively, in order to make the cavity length 850 nm. With these designs, the cavity mode of the nanowire VCSEL can be made 850nm, as shown in fig. 6.
The P+ GaAs contact segment 41 needs to be heavily doped so as to form ohmic contact, and the doping concentration should reach 2E19cm -3 . To facilitate deposition to prepare the insulating buried layer 5, a longer p+ GaAs contact section 41 is grown, optionally 300nm in length.
The insulating buried layer 5 completely buries the N-GaAs section, the N-DBR, the lower confinement section, the active region, the upper confinement section, the P-DBR of the nanowire VCSEL, and buries a portion of the p+gaas contact section. Alternatively, the p+ GaAs contact is buried to a length of 100nm, and then 200nm is exposed above the insulating buried layer 5. The insulating buried layer may be SiO 2 、SiN x Or TiO 2 One or a combination of several of these insulating dielectric materials.
Alternatively, siO is taken in the present embodiment 2 Is an insulating buried layer material.
An ITO transparent electrode 3 is arranged above the insulating buried layer 5, and the transparent electrode completely covers the P+ GaAs contact section exposed above the insulating buried layer 5 and forms ohmic contact with the P+ GaAs contact section. In order to completely cover the p+ GaAs contact section, the thickness of the transparent electrode layer should be greater than the exposed portion of the p+ GaAs contact section.
Optionally, taking the thickness of the transparent electrode as 230nm; and a metal electrode is arranged on the nanowire VCSEL array point, the diameter of the opening is larger than that of the nanowire, and optionally, the diameter of the opening is 350nm.
The second electrode 8 is a lower electrode and is a metal electrode on the back surface of the substrate.
Example 2:
the preparation method of the VCSEL array based on the nano-wire axial heterojunction comprises the following steps:
(1) Firstly, selecting a GaAs substrate, and depositing a mask layer 6 of 20-50 nm, such as SiO, on the surface of the substrate by adopting a magnetron sputtering or plasma-assisted chemical vapor deposition method 2 Or SiNx;
(2) Forming an open hole pattern on the mask layer 6 by adopting a stepping photoetching machine or an electron beam exposure technology, and forming an open hole on the mask layer 6 to the surface of the GaAs substrate by adopting a dry etching technology to serve as a mask for the growth of the nanowire array;
(3) The nanowire VCSEL array is grown section by section in a self-catalysis mode under the low temperature and low V/III ratio by adopting a metal organic chemical vapor deposition or molecular beam epitaxy technology, and the length of each section is accurately controlled by regulating and controlling the growth rate and the growth time;
(4) After the growth of the nanowire VCSEL array is completed, depositing an insulating buried layer 5 by adopting a magnetron sputtering or plasma-assisted chemical vapor deposition method, and covering the nanowire VCSEL array by controlling the deposition rate and the thickness of the insulating buried layer 5 by controlling the time;
(5) Etching the top of the insulating buried layer 5 by adopting a selective wet etching technology to expose part of the P+ GaAs contact section 41, and cleaning the surface of the P+ GaAs contact section 41 by adopting a plasma cleaning technology to remove impurities remained on the surface in the etching process;
(6) An ITO transparent electrode 3 is deposited on the insulating buried layer 5 and forms ohmic contact with the P+ GaAs contact section 41, and the transparent electrode 3 can well conduct current expansion and can not block the emission of laser;
(7) Forming a metal electrode pattern on the surface of the ITO transparent electrode 3 by adopting a stepping photoetching machine or an electron beam exposure technology, then depositing a metal electrode on the surface of the ITO by adopting a magnetron sputtering or electron beam evaporation mode, and stripping with glue to form an opening at a lattice point of the nanowire array for laser emission;
(8) Thinning, polishing and cleaning an N-GaAs substrate, and preparing a metal electrode on the back surface of the substrate by adopting a magnetron sputtering or electron beam evaporation mode to serve as a negative electrode of the VCSEL array;
(9) Scribing and splitting according to the requirement to form nanowire VCSEL array chips, and completing the preparation.
In the embodiment, the preparation method of the VCSEL array is designed, so that the preparation step of an oxidation hole is omitted, the preparation process of the device is simplified, and the preparation difficulty of the device is reduced; the selectable VCSEL emission wavelength range is expanded, and etching damage generated in the traditional VCSEL preparation process is avoided. The VCSEL array chip prepared by the embodiment remarkably improves the temperature stability, single-mode characteristics, light-emitting wavelength range and the like of the VCSEL through the quantum effect, high strain tolerance and other characteristics of the nanowire, and simultaneously avoids the problem of dry etching damage.
In the description of the present invention, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A nanowire axial heterojunction-based VCSEL array, characterized by: the novel VCSEL comprises a first electrode (2), an insulating buried layer (5), a mask layer (6), a substrate (7) and a second electrode (8) which are sequentially arranged, wherein nanowires (4) grow in the insulating buried layer (5) and the mask layer (6), each nanowire (4) is vertically arranged to form a nanowire array, and each nanowire (4) in the nanowire array independently forms a VCSEL structure.
2. A nanowire axial heterojunction based VCSEL array as claimed in claim 1, wherein: the nanowire (4) is formed by an axial heterostructure and sequentially comprises: an N-GaAs segment (47), an N-DBR segment (46), a lower confinement segment (45), an active region (44), an upper confinement segment (43), a P-DBR segment (42), and a P+ GaAs contact segment (41).
3. A nanowire axial heterojunction based VCSEL array as claimed in claim 2, wherein: the first electrode (2) is positioned above the insulating buried layer (5) and forms ohmic contact with the P+ GaAs contact section (41) of the nanowire (4), and the second electrode (8) is positioned below the substrate (7) and forms ohmic contact with the substrate (7).
4. A nanowire axial heterojunction based VCSEL array as claimed in claim 2, wherein: the insulating buried layer (5) is buried with an N-GaAs section (47), an N-DBR section (46), a lower limiting section (45), an active region (44), an upper limiting section (43), a P-DBR section (42) and a part of P+ GaAs contact section (41) of the nanowire, and the rest of the P+ GaAs contact section (41) is exposed on the insulating buried layer (5) and is used for forming ohmic contact with the first electrode (2).
5. A nanowire axial heterojunction based VCSEL array as claimed in claim 2, wherein: the first electrode (2) comprises two layers, one layer is an ITO transparent electrode (3), the ITO transparent electrode (3) and the P+ GaAs contact section (41) form ohmic contact, the other layer is a metal electrode positioned on the ITO transparent electrode (3), and an electrode opening (1) is arranged at a lattice point corresponding to the nanowire (4) on the metal electrode so as to ensure that laser can exit through the electrode opening (1).
6. A nanowire axial heterojunction based VCSEL array as claimed in claim 1, wherein: the mask layer (6) is provided with holes which are arranged periodically, the diameter of each hole is the same as that of the nanowire (4), the nanowire (4) grows out of each hole, and the minimum period of the hole arrangement is square, rectangle, diamond or parallelogram.
7. A nanowire axial heterojunction based VCSEL array as claimed in claim 2, wherein: the N-DBR section (46) and the P-DBR section (42) are made of Al x Ga 1-x As and Al y Ga 1-y The As nano-discs are formed by periodical overlapping, wherein x and y are Al components of AlGaAs respectively, and x is not equal to y, so that Al x Ga 1-x As and Al y Ga 1-y As has different refractive indices, the disk diameter is equal to the nanowire (4) diameter, and periodic overlapping forms the N-DBR section (46) and the P-DBR section (42) of the nanowire.
8. A nanowire axial heterojunction based VCSEL array as claimed in claim 2, wherein: the active region (44) is a single-layer nano-disc or two kinds of periodically overlapped nano-discs, and the diameter of the discs is the diameter of the nano-wires.
9. A nanowire axial heterojunction based VCSEL array as claimed in claim 1, wherein: the mask layer (6) adopts SiO 2 Or SiN x The insulating buried layer (5) is made of SiO 2 、SiN x A combination of one or more insulating dielectric materials.
10. A method for preparing a VCSEL array based on a nano-axial heterojunction, applied to the VCSEL array based on a nano-axial heterojunction according to any one of claims 1 to 9, comprising the steps of:
s1: firstly, selecting a substrate (7), and depositing a mask layer (6) on the surface of the substrate (7);
s2: forming an open hole pattern on the mask layer (6), and forming an open hole on the mask layer (6) to the surface of the substrate (7) to serve as a mask for the growth of the nanowire array;
s3: the nanowire array is grown segment by utilizing a metal organic chemical vapor deposition or molecular beam epitaxy technology and an autocatalysis mode, and the length of each segment is precisely controlled by regulating and controlling the growth rate and the growth time;
s4: after the growth of the nanowire array is completed, depositing an insulating buried layer (5), and controlling the thickness of the insulating buried layer (5) by controlling the deposition rate and time to cover the nanowire array;
s5: etching the top of the insulating buried layer (5) to expose part of the P+ GaAs contact section (41), and cleaning the surface of the P+ GaAs contact section (41) to remove impurities remained on the surface in the etching process;
s6: depositing an ITO transparent electrode (3) on the insulating buried layer (5) to form ohmic contact with the P+ GaAs contact section (41);
s7: forming a metal electrode pattern on the surface of an ITO transparent electrode (3), depositing a metal electrode on the surface of the ITO, and forming an opening at a lattice point of the nanowire array for laser emission;
s8: thinning, polishing and cleaning a substrate, and then preparing a metal electrode on the back of the substrate, wherein the metal electrode is used as a negative electrode of the nano array;
s9: scribing and splitting according to the requirement to form a nanowire array chip, and completing the preparation.
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