CN116631847A - Gallium oxide heterogeneous integrated structure and preparation method thereof - Google Patents

Gallium oxide heterogeneous integrated structure and preparation method thereof Download PDF

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Publication number
CN116631847A
CN116631847A CN202310498119.5A CN202310498119A CN116631847A CN 116631847 A CN116631847 A CN 116631847A CN 202310498119 A CN202310498119 A CN 202310498119A CN 116631847 A CN116631847 A CN 116631847A
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gallium oxide
wafer
integrated structure
hetero
layer
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欧欣
瞿振宇
游天桂
徐文慧
赵天成
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
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Abstract

The application provides a gallium oxide heterogeneous integrated structure and a preparation method thereof, wherein the surface of the gallium oxide heterogeneous integrated structure is etched to form a texture structure with grooves on the surface of the gallium oxide composite structure based on anisotropic etching of NaOH solution or KOH solution, so that the total effective heat dissipation area of the device is increased, the heat dissipation capacity of the gallium oxide-based device prepared based on the texture structure is enhanced, the heat dissipation problem of the gallium oxide-based device is solved, and the service life of the gallium oxide-based device is prolonged.

Description

Gallium oxide heterogeneous integrated structure and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductors, and relates to a gallium oxide heterogeneous integrated structure and a preparation method thereof.
Background
Gallium oxide (Ga) 2 O 3 ) By virtue of ultra-wide band gap and ultra-high breakdown field strength, the material becomes a fourth-generation semiconductor material with great development prospect. The Baliga figure of merit (BFOM) is far superior to silicon (Si), and the gallium oxide-based device has excellent performance in a high-power application scene with low power consumption.
In addition, since a large-sized gallium oxide single crystal can be obtained by a melt growth method, the cost thereof can be controlled at a low level, and the method is suitable for mass production. However, the thermal conductivity of gallium oxide is very low, only about 1/8 that of silicon, which makes heat dissipation one of the key issues restricting the development of gallium oxide-based devices.
Currently, heterogeneous integration of gallium oxide with highly thermally conductive substrates is an important way to improve the heat dissipation capability of the device. Although the method has great significance for realizing the heat dissipation capacity of the gallium oxide-based device, the heat dissipation problem of the gallium oxide-based device can not be completely solved only based on the method.
Therefore, it is necessary to provide a gallium oxide heterogeneous integrated structure and a preparation method thereof to further optimize the structure of a gallium oxide-based device so as to solve the heat dissipation problem of the gallium oxide-based device.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a gallium oxide hetero-integrated structure and a preparation method thereof, which are used for solving the heat dissipation problem of a gallium oxide-based device in the prior art.
To achieve the above and other related objects, the present application provides a method for preparing a gallium oxide hetero-integrated structure, comprising the steps of:
providing a gallium oxide wafer and a heterogeneous substrate wafer, wherein the gallium oxide wafer and the heterogeneous substrate wafer are provided with polished surfaces;
ion implantation is carried out from the polished surface of the gallium oxide wafer, and a defect layer is formed in the gallium oxide wafer;
bonding the polished surface of the gallium oxide wafer with the polished surface of the hetero-substrate wafer;
annealing and stripping along the defect layer to obtain a first composite structure comprising a surface damage layer, a gallium oxide layer and the heterogeneous substrate wafer stacked from top to bottom;
carrying out surface treatment on the first composite structure, and removing the surface damage layer to expose the gallium oxide layer;
growing a gallium oxide epitaxial layer on the surface of the gallium oxide layer in a homoepitaxy manner to obtain a second composite structure comprising the gallium oxide epitaxial layer, the gallium oxide layer and the heterogeneous substrate wafer stacked from top to bottom;
etching the surface of the second composite structure to prepare the gallium oxide heterogeneous integrated structure with the suede structure on the surface.
Optionally, the method for etching the surface of the second composite structure includes wet etching, wherein the etching solution includes one or a combination of NaOH solution and KOH solution; the concentration of the etching solution is 1-50%, the wet etching temperature is 20-200 ℃, and the wet etching time is 1-60 min.
Optionally, the homoepitaxy method includes one or a combination of vapor phase epitaxy, chemical vapor deposition, molecular beam epitaxy, and pulsed laser deposition.
Optionally, before etching the surface of the second composite structure or after etching the surface of the second composite structure, the method further comprises a step of forming a metal electrode; the method for preparing the metal electrode comprises one or a combination of an evaporation method, a sputtering method and a stripping method; the metal electrode comprises one or a combination of a Ti metal electrode, a Ni metal electrode, a Pt metal electrode, an Au metal electrode and an Ag metal electrode.
Optionally, the gallium oxide wafer comprises one of an alpha-gallium oxide wafer, a beta-gallium oxide wafer, a gamma-gallium oxide wafer, a delta-gallium oxide wafer, and an epsilon-gallium oxide wafer; the hetero-substrate wafer includes one of a silicon wafer, a silicon carbide wafer, an aluminum nitride wafer, and a gallium nitride wafer.
Optionally, the ion implantation includes one or a combination of H ion implantation and He ion implantation.
Optionally, the method of surface treating the first composite structure includes one or a combination of mechanical grinding, chemical mechanical polishing, dry etching, and wet etching.
Alternatively, the bonding method includes one of surface activated bonding, metal bonding, hydrophilic bonding, and anodic bonding.
The application also provides a gallium oxide heterogeneous integrated structure, which comprises a gallium oxide epitaxial layer, a gallium oxide layer and a heterogeneous substrate wafer which are stacked from top to bottom, wherein the surface of the gallium oxide heterogeneous integrated structure is provided with a suede structure.
Optionally, the gallium oxide hetero-integrated structure comprises a gallium oxide-based hetero-PN junction or a gallium oxide-based schottky barrier diode.
As described above, according to the gallium oxide heterogeneous integrated structure and the preparation method, the surface of the gallium oxide composite structure subjected to heterogeneous integration is etched to anisotropically etch materials based on NaOH solution or KOH solution, and the suede structure with the grooves is left on the surface of the gallium oxide composite structure, so that the total effective heat dissipation area of the device is increased, the heat dissipation capacity of the gallium oxide-based device prepared based on the structure is enhanced, the heat dissipation problem of the gallium oxide-based device is solved, and the service life of the gallium oxide-based device is prolonged.
Drawings
Fig. 1 is a schematic process flow diagram of a gallium oxide hetero-integrated structure according to an embodiment of the application.
Fig. 2 is a schematic structural diagram of a gallium oxide wafer according to an embodiment of the application.
Fig. 3 is a schematic diagram of a heterogeneous substrate wafer according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a defect layer formed by ion implantation according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of the bonding method according to the embodiment of the application.
Fig. 6 is a schematic diagram of the structure after annealing and stripping in the embodiment of the application.
Fig. 7 is a schematic diagram of a structure after homoepitaxially growing a gallium oxide epitaxial layer according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a structure after forming a metal electrode according to an embodiment of the application.
Fig. 9 is a schematic structural diagram of the etching process performed to form a suede structure according to an embodiment of the present application.
Description of element reference numerals
100. Gallium oxide wafer
Polishing surface of 100a gallium oxide wafer
101. Gallium oxide layer
200. Heterogeneous substrate wafer
200a polishing surface of foreign substrate wafer
300. Defect layer
400. Surface damage layer
500. Gallium oxide epitaxial layer
600. Metal electrode
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures, including embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact, and further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the embodiment provides a method for preparing a gallium oxide hetero-integrated structure, which includes the following steps:
s1: providing a gallium oxide wafer and a heterogeneous substrate wafer, wherein the gallium oxide wafer and the heterogeneous substrate wafer are provided with polished surfaces;
s2: ion implantation is carried out from the polished surface of the gallium oxide wafer, and a defect layer is formed in the gallium oxide wafer;
s3: bonding the polished surface of the gallium oxide wafer with the polished surface of the hetero-substrate wafer;
s4: annealing and stripping along the defect layer to obtain a first composite structure comprising a surface damage layer, a gallium oxide layer and the heterogeneous substrate wafer stacked from top to bottom;
s5: carrying out surface treatment on the first composite structure, and removing the surface damage layer to expose the gallium oxide layer;
s6: growing a gallium oxide epitaxial layer on the surface of the gallium oxide layer in a homoepitaxy manner to obtain a second composite structure comprising the gallium oxide epitaxial layer, the gallium oxide layer and the heterogeneous substrate wafer stacked from top to bottom;
s7: etching the surface of the second composite structure to prepare the gallium oxide heterogeneous integrated structure with the suede structure on the surface.
According to the embodiment, the surface of the hetero-integrated gallium oxide composite structure is etched, and the suede structure with the grooves is left on the surface of the gallium oxide composite structure, so that the total effective heat dissipation area of the device is increased, the heat dissipation capacity of the gallium oxide-based device prepared based on the method is enhanced, the heat dissipation problem of the gallium oxide-based device is solved, and the service life of the gallium oxide-based device is prolonged.
The preparation of the gallium oxide hetero-integrated structure is described below with reference to fig. 2to 9 of the specification.
First, referring to fig. 2 and 3, step S1 is performed to provide a gallium oxide wafer 100 and a hetero-substrate wafer 200, wherein the gallium oxide wafer 100 has a polishing surface 100a of the gallium oxide wafer and the hetero-substrate wafer 200 has a polishing surface 200a of the hetero-substrate wafer.
Specifically, the dimensions of the gallium oxide wafer 100 and the hetero-substrate wafer 200 may be selected as desired, including 2 inches to 12 inches, such as 4 inches, 6 inches, etc. The gallium oxide wafer 100 may include one of an alpha-gallium oxide wafer, a beta-gallium oxide wafer, a gamma-gallium oxide wafer, a delta-gallium oxide wafer, and an epsilon-gallium oxide wafer; the gallium oxide wafer 100 may include an N-type doped gallium oxide single crystal wafer or an intrinsic gallium oxide single crystal wafer; the foreign substrate wafer 200 may include one of a silicon wafer, a silicon carbide wafer, an aluminum nitride wafer, and a gallium nitride wafer; the hetero-substrate wafer 200 may include a P-type doped hetero-substrate wafer, an N-type doped hetero-substrate wafer, or an intrinsic hetero-substrate wafer, and may be specifically selected as needed.
Next, referring to fig. 4, step S2 is performed to perform ion implantation from the polished surface 100a of the gallium oxide wafer, and a defect layer 300 is formed in the gallium oxide wafer 100.
As an example, the ion implantation may include one or a combination of H ion implantation and He ion implantation.
Specifically, the ion implantation energy may be 20Kev to 200Kev, such as 20Kev, 100Kev, 200Kev, etc., and the dose may be 2×10 16 ions/cm 2 ～2×10 18 ions/cm 2 Such as 2X 10 16 ions/cm 2 、2×10 17 ions/cm 2 、2×10 17 ions/cm 2 The temperature can be 20-200 ℃, such as 20 ℃, 100 ℃, 150 ℃, 200 ℃ and the like.
Arrows in fig. 4 indicate the direction of ion implantation, wherein the polished surface 100a of the gallium oxide wafer serves as an implantation surface, and in an example, single-type ion implantation may be performed from the polished surface 100a of the gallium oxide wafer, that is, ion implantation includes H ion implantation or He ion implantation. When the implanted ions are H ions, the H ions may damage the crystal lattice of the gallium oxide wafer 100 at a predetermined depth, i.e., form the defect layer 300, so as to facilitate a subsequent lift-off process, wherein the depth at which the defect layer 300 is formed is determined by the energy of ion implantation, and the defect density required for separation can be determined by the dose of ion implantation. When the implanted ions are He ions, the He ions form the defect layer 300 at a predetermined depth in the gallium oxide wafer 100, the He ions are collected in the defect layer 300 and generate pressure, and during a subsequent lift-off process, a portion of the gallium oxide wafer 100 may be lifted off from the position where the defect concentration is maximum. In another example, co-implantation of two types of ions, i.e., H ions and He ions, may be performed from the polished surface 100a of the gallium oxide wafer, where the H ions may be used to form defects as described above, and the He ions may be trapped by the defects formed by the H ions and physically expand and combine with each other, which is equivalent to applying an additional force inside the defects generated by the H ions, so as to finally form a crack that may separate the gallium oxide wafer 100, thereby promoting the detachment of a portion of the gallium oxide wafer 100 from the position where the defect concentration is the largest, and may effectively promote the detachment of a portion of the gallium oxide wafer 100 under the condition of a lower ion implantation dose, i.e., may effectively reduce the total dose of ion implantation, thereby shortening the preparation period and saving the production cost.
Next, referring to fig. 5, step S3 is performed to bond the polished surface 100a of the gallium oxide wafer with the polished surface 200a of the hetero-substrate wafer.
As an example, the bonding method may include one of surface activated bonding, metal bonding, hydrophilic bonding, and anodic bonding.
Specifically, the bonding pressure can be 5 MPa-500 MPa, such as 5MPa, 30MPa, 50MPa, 100MPa, 500MPa, etc., and the vacuum degree can be 2×10 -7 Pa～1×10 -4 Pa, e.g. 2X 10 -7 Pa、1×10 -5 Pa、1×10 -4 Pa, etc., and the temperature may be room temperature, etc.
Next, referring to fig. 6, step S4 is performed to perform annealing, and lift-off is performed along the defect layer 300, so as to obtain a first composite structure including the surface damaged layer 400, the gallium oxide layer 101 and the hetero-substrate wafer 200 stacked from top to bottom.
Specifically, the annealing treatment of the first composite structure may be performed under an atmosphere formed by at least one of vacuum, nitrogen, oxygen, and inert gas, and the annealing temperature may be 200 ℃ to 1000 ℃, such as 200 ℃, 500 ℃, 1000 ℃, and the like, and the annealing time may be 5min to 72h, such as 5min, 1h, 24h, 72h, and the like. During the annealing process, the implanted ions diffuse to the stripping position, so as to promote the stripping of a portion of the gallium oxide wafer 100 from the position with the largest defect concentration of the defect layer 300, so as to obtain the first composite structure.
Next, step S5 is performed to perform surface treatment on the first composite structure, and remove the surface damaged layer 400 to expose the gallium oxide layer 101.
As an example, the surface treatment method may include one or a combination of mechanical polishing, chemical mechanical polishing, dry etching, and wet etching, and after the surface treatment process such as chemical mechanical polishing, the defect layer 300 and a portion of the gallium oxide material remaining on the surface of the gallium oxide layer 101 may be removed, so as to obtain the gallium oxide layer 101 with high quality.
Next, referring to fig. 7, step S6 is performed to grow a gallium oxide epitaxial layer 500 on the surface of the gallium oxide layer 101 by homoepitaxy, so as to obtain a second composite structure including stacking the gallium oxide epitaxial layer 500, the gallium oxide layer 101 and the hetero-substrate wafer 200 from top to bottom.
By way of example, methods employed for homoepitaxy may include one or a combination of vapor phase epitaxy, chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition.
Specifically, when the epitaxy mode is gas phase epitaxy delay, the growth temperature can be 600-1000 ℃, such as 600 ℃, 800 ℃, 1000 ℃, and the like, the Ga source can be GaCl, and the like, the partial pressure can be 10-200 Pa, such as 10Pa, 100Pa, 200Pa, and the like, and the O source can comprise O 2 One or a combination of ozone, oxygen plasma and air, and the carrier gas can be N 2 Or one or a combination of Ar; when the epitaxy mode is chemical vapor deposition, the growth temperature can be 500-1200deg.C, such as 500 deg.C, 800 deg.C, 1000 deg.C, 1200 deg.C, etc., ga source can be high purity Ga, triethyl gallium or acetyl acetonate gallium, etc., O source can be O 2 Or O 2 And water vapor, the carrier gas can be Ar, he, N 2 The growth chamber pressure may be 2to 100Torr, such as 2Torr, 50Torr, 100Torr, etc.; when the epitaxy mode is molecular beam epitaxy, the growth temperature can be 600-1000deg.C, such as 600deg.C, 800deg.C, 1000deg.C, ga source can be high purity Ga, O source can include O 2 One or a combination of ozone, oxygen plasma; when the epitaxy mode is pulse laser deposition, the substrate temperature can be 400-600deg.C, such as 400deg.C, 500deg.C, 600deg.C, etc., and the deposition atmosphere can be O 2 In combination with Ar, wherein O 2 The ratio of the growth gas to the growth gas can be 1-30%, such as 1%, 10%, 30%, etc., and the growth gas pressure can be 1×10 -3 Pa to 1Pa, e.g. 1X 10 -3 Pa、1×10 -2 Pa、1PaAnd the laser power density can be 1-20J/cm 2 Such as 1J/cm 2 、10J/cm 2 、20J/cm 2 Etc.
Where gallium oxide is the dopant material, the dopant source may comprise one or a combination of Sn, si, mg, fe, ge, al, in, as desired.
Next, referring to fig. 8, a step of forming a metal electrode 600 may be further included; the method for preparing the metal electrode 600 may include one or a combination of evaporation, sputtering, and stripping; the metal electrode 600 may include one or a combination of Ti metal electrode, ni metal electrode, pt metal electrode, au metal electrode, ag metal electrode.
Specifically, as shown in fig. 8, in the embodiment of the present application, the metal electrode 600 is formed on the surface of the gallium oxide epitaxial layer 500 and the heterogeneous substrate wafer 200 to form a vertical conductive device, but the present application is not limited thereto, and the metal electrode 600 may be formed on only one side of the gallium oxide epitaxial layer 500 to form a horizontal conductive device, and the preparation method, the material, the morphology, etc. of the metal electrode 600 may be set according to the needs, and are not limited thereto.
The gallium oxide hetero-integrated structure may include a gallium oxide-based hetero-PN junction or a gallium oxide-based Schottky barrier diode, but is not limited thereto.
Next, referring to fig. 9, step S7 is performed to etch the surface of the second composite structure, so as to prepare the gallium oxide hetero-integrated structure with a suede structure on the surface.
As an example, the method of etching the surface of the second composite structure may include wet etching, wherein the etching solution may include one or a combination of NaOH solution and KOH solution; the concentration of the etching solution may include 1 to 50%, such as 1%, 10%, 20%, 50%, etc., the wet etching temperature may include 20 to 200 ℃, such as 20 ℃, 100 ℃, 200 ℃, etc., and the wet etching time may include 1 to 60 minutes, such as 1 minute, 30 minutes, 60 minutes, etc.
Specifically, since the NaOH solution or KOH solution has anisotropic etching on the gallium oxide material, the silicon wafer, the silicon carbide wafer, the aluminum nitride wafer, and the gallium nitride wafer, the embodiment of the present application may form the textured structure with grooves on the gallium oxide epitaxial layer 500 and the hetero-substrate wafer 200, and of course, the topography of the textured structure formed may be different according to the difference of the materials, and the overall effective heat dissipation area of the device may be increased through the textured structure, so as to enhance the heat dissipation capability, thereby solving the heat dissipation problem of the gallium oxide-based device and improving the service life of the gallium oxide-based device.
In the embodiment of the present application, the metal electrode 600 is prepared before etching the surface of the second composite structure so as to reduce the influence of etching on the metal electrode 600, but the present application is not limited thereto, and in another embodiment, the metal electrode 600 may be prepared after etching the surface of the second composite structure, which is not limited herein.
Referring to fig. 8, the embodiment of the present application further provides a gallium oxide hetero-integrated structure, where the gallium oxide hetero-integrated structure includes a gallium oxide epitaxial layer 500, a gallium oxide layer 101 and a hetero-substrate wafer 200 stacked from top to bottom, and a textured structure is formed on the surface of the gallium oxide hetero-integrated structure.
Specifically, the gallium oxide hetero-integrated structure may be prepared by using the preparation method of the gallium oxide hetero-integrated structure, but is not limited thereto, and the gallium oxide semiconductor structure in this embodiment is prepared by using the preparation process, so that details about materials, structures, etc. of the gallium oxide hetero-integrated structure are not repeated here.
As an example, as shown in fig. 9, the gallium oxide hetero-integrated structure may further include a metal electrode 600, and the metal electrode 600 may include one or a combination of a Ti metal electrode, a Ni metal electrode, a Pt metal electrode, an Au metal electrode, and an Ag metal electrode. The material, morphology, etc. of the metal electrode 600 may be set as required, and are not limited thereto.
As an example, the gallium oxide hetero-integrated structure may include a vertical conduction type device or a horizontal conduction type device.
As an example, the gallium oxide hetero-integrated structure may include a gallium oxide-based hetero-PN junction or a gallium oxide-based schottky barrier diode.
In summary, according to the gallium oxide heterogeneous integrated structure and the preparation method, the surface of the gallium oxide composite structure subjected to heterogeneous integration is etched, so that the textured structure with the grooves is left on the surface of the gallium oxide composite structure based on anisotropic etching of NaOH solution or KOH solution, the total effective heat dissipation area of the device is increased, the heat dissipation capacity of the gallium oxide-based device prepared based on the structure is enhanced, the heat dissipation problem of the gallium oxide-based device is solved, and the service life of the gallium oxide-based device is prolonged.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the gallium oxide heterogeneous integrated structure is characterized by comprising the following steps of:
providing a gallium oxide wafer and a heterogeneous substrate wafer, wherein the gallium oxide wafer and the heterogeneous substrate wafer are provided with polished surfaces;
ion implantation is carried out from the polished surface of the gallium oxide wafer, and a defect layer is formed in the gallium oxide wafer;
bonding the polished surface of the gallium oxide wafer with the polished surface of the hetero-substrate wafer;
annealing and stripping along the defect layer to obtain a first composite structure comprising a surface damage layer, a gallium oxide layer and the heterogeneous substrate wafer stacked from top to bottom;
carrying out surface treatment on the first composite structure, and removing the surface damage layer to expose the gallium oxide layer;
growing a gallium oxide epitaxial layer on the surface of the gallium oxide layer in a homoepitaxy manner to obtain a second composite structure comprising the gallium oxide epitaxial layer, the gallium oxide layer and the heterogeneous substrate wafer stacked from top to bottom;
etching the surface of the second composite structure to prepare the gallium oxide heterogeneous integrated structure with the suede structure on the surface.
2. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: the method for etching the surface of the second composite structure comprises wet etching, wherein the etching solution comprises one or a combination of NaOH solution and KOH solution; the concentration of the etching solution is 1-50%, the wet etching temperature is 20-200 ℃, and the wet etching time is 1-60 min.
3. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: homoepitaxy employs methods including one or a combination of vapor phase epitaxy, chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition.
4. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: before etching the surface of the second composite structure or after etching the surface of the second composite structure, the method further comprises the step of forming a metal electrode; the method for preparing the metal electrode comprises one or a combination of an evaporation method, a sputtering method and a stripping method; the metal electrode comprises one or a combination of a Ti metal electrode, a Ni metal electrode, a Pt metal electrode, an Au metal electrode and an Ag metal electrode.
5. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: the gallium oxide wafer includes one of an alpha-gallium oxide wafer, a beta-gallium oxide wafer, a gamma-gallium oxide wafer, a delta-gallium oxide wafer, and an epsilon-gallium oxide wafer;
the hetero-substrate wafer includes one of a silicon wafer, a silicon carbide wafer, an aluminum nitride wafer, and a gallium nitride wafer.
6. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: the ion implantation includes one or a combination of H ion implantation and He ion implantation.
7. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: the method for carrying out surface treatment on the first composite structure comprises one or a combination of mechanical grinding, chemical mechanical polishing, dry etching and wet etching.
8. The method for preparing a gallium oxide hetero-integrated structure of claim 1 wherein: the bonding method comprises one of surface activation bonding, metal bonding, hydrophilic bonding and anode bonding.
9. A gallium oxide heterogeneous integrated structure, characterized in that: the gallium oxide heterogeneous integrated structure comprises a gallium oxide epitaxial layer, a gallium oxide layer and a heterogeneous substrate wafer which are stacked from top to bottom, and the surface of the gallium oxide heterogeneous integrated structure is provided with a suede structure.
10. The gallium oxide heterostructure of claim 9, wherein: the gallium oxide heterojunction integrated structure comprises a gallium oxide-based heterojunction PN junction or a gallium oxide-based Schottky barrier diode.
CN202310498119.5A 2023-05-04 2023-05-04 Gallium oxide heterogeneous integrated structure and preparation method thereof Pending CN116631847A (en)

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CN112382664A (en) * 2020-11-03 2021-02-19 广东省科学院半导体研究所 Flip MOSFET device and manufacturing method thereof
CN113223926A (en) * 2021-04-16 2021-08-06 西安电子科技大学 Preparation method of atomic-level high-quality gallium oxide epitaxial layer
CN115295404A (en) * 2022-08-08 2022-11-04 中国科学院上海微系统与信息技术研究所 Ga 2 O 3 Preparation method of base heterogeneous integrated pn junction

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Publication number Priority date Publication date Assignee Title
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
CN111223782A (en) * 2019-11-26 2020-06-02 中国科学院上海微系统与信息技术研究所 Gallium oxide semiconductor structure, vertical gallium oxide-based power device and preparation method
CN112382664A (en) * 2020-11-03 2021-02-19 广东省科学院半导体研究所 Flip MOSFET device and manufacturing method thereof
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