CN116610401A

CN116610401A - High-speed desktop sharing system capable of being dynamically reconfigured based on PCIe bus

Info

Publication number: CN116610401A
Application number: CN202310570457.5A
Authority: CN
Inventors: 梁华国; 刘新颖; 谢锦浩; 鲁迎春; 黄正峰; 易茂祥
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2023-05-19
Filing date: 2023-05-19
Publication date: 2023-08-18

Abstract

The invention discloses a high-speed desktop sharing system capable of being dynamically reconfigured based on a PCIe bus, which comprises the following components: PCIe upper computer test subsystem and PCIe lower computer FPGA subsystem; the PCIe upper computer test subsystem comprises a test configuration module, a single acquisition module and a continuous acquisition module; the PCIe lower computer FPGA subsystem comprises a PCIe image module, an image processing synchronous FIFO, a memory control initialization module, a writing storage asynchronous FIFO, a reading storage asynchronous FIFO1, a reading storage asynchronous FIFO2, a memory control user end module, an image display asynchronous FIFO, a display driving module and a dynamic clock output module. The invention enables the desktop sharing system to become more rapid, real-time and stable through the PCIe bus and the dynamic reconfiguration method.

Description

High-speed desktop sharing system capable of being dynamically reconfigured based on PCIe bus

Technical Field

The invention relates to the field of PCIe bus high-speed communication, in particular to a high-speed desktop sharing system capable of being dynamically reconfigured based on a PCIe bus.

Background

With the rapid development of information technology and technology, more and more data are required to be transmitted in the fields of work, scientific research, teaching and the like, and under such a background, the information transmission efficiency between different computers becomes very important, so that a desktop sharing system is rapidly developed and applied. While several problems with desktop sharing systems require significant attention and resolution: firstly, high delay does not occur in the transmission process, and the picture information is lagged, namely, the desktop sharing system has instantaneity; second, no picture jamming occurs in the transmission process, i.e. the desktop sharing system should have stability.

In the existing sharing system scheme, common desktop sharing systems can be divided into modes of network sharing, movable storage equipment transmission, screen projection and the like. However, the limitation of the above mentioned method is relatively large, for example, the transmission quality of network sharing is affected by network conditions, and even no network or no transmission occurs; the movable storage equipment cannot transmit real-time information; while screen projection cannot transmit other types of data and cannot transmit across resolutions.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a high-speed desktop sharing system based on a PCIe bus and capable of being dynamically reconfigured, so that the desktop sharing system can have higher real-time performance and reliable stability as required through the high-speed communication of the PCIe bus and a dynamic reconfiguration method.

In order to achieve the aim of the invention, the invention adopts the following technical scheme:

the invention discloses a high-speed desktop sharing system capable of being dynamically reconfigured based on a PCIe bus, which is characterized by comprising the following components: PCIe upper computer test subsystem and PCIe lower computer FPGA subsystem;

the PCIe upper computer test subsystem comprises a test configuration module, a single acquisition module and a continuous acquisition module;

The PCIe lower computer FPGA subsystem comprises a PCIe image module, an image processing synchronous FIFO, a memory control initialization module, a writing storage asynchronous FIFO, a reading storage asynchronous FIFO1, a reading storage asynchronous FIFO2, a memory control user end module, an image display asynchronous FIFO, a display driving module and a dynamic clock output module;

the test configuration module generates a function containing a resolution information data packet for sharing a desktop target end according to a header file provided by a PCIe card driver, so that the resolution information data packet for sharing the desktop target end in the function is issued to an FPGA subsystem of a PCIe lower computer by using the PCIe card driver;

the single acquisition module generates a function containing a shared desktop single-frame picture information data packet for adapting to the resolution of the shared desktop target end according to the header file provided by the PCIe card drive, so that the shared desktop single-frame picture information data packet for adapting to the resolution of the shared desktop target end in the function is issued to the PCIe lower computer FPGA subsystem by using the PCIe card drive; then a PCIe image module of the PCIe lower computer FPGA subsystem transmits a preset shared desktop single-frame picture information data packet tail to the single acquisition module;

The continuous acquisition module also generates a function containing a shared desktop single-frame picture information data packet for adapting to the resolution of a shared desktop target end according to the header file provided by the PCIe card drive, and continuously transmits the shared desktop single-frame picture information data packet in the function to the PCIe lower computer FPGA subsystem by using the PCIe card drive; then, a PCIe image module of the PCIe lower computer FPGA subsystem continuously transmits a preset shared desktop single-frame picture information data packet tail to the continuous acquisition module;

the PCIe image module generates image data image_data0[31:0] with the bit width of 32, an image processing synchronous FIFO write enable signal image_wren and an image processing synchronous FIFO write clock image_wrclk according to a clock user_clk generated by an internal PCIe IP core; writing the image data image_data0[31:0] with the bit width of 32 into an image processing synchronous FIFO according to the image processing synchronous FIFO write enable signal image_wren and an image processing synchronous FIFO write clock image_wrclk;

the PCIe image module generates an image processing synchronous FIFO read enable signal image_rden and an image processing synchronous FIFO read clock image_rdclk according to a clock user_clk generated by an internal PCIe IP core; reading image data image_data1[127:0] with the bit width of 128, which is generated by a PCIe image module and is generated after the image data image_data0[31:0] with the bit width of 32, from the image processing synchronous FIFO according to the image processing synchronous FIFO read enable signal image_rden and an image processing synchronous FIFO read clock image_rdclk;

The PCIe image module generates an image mark signal image_start of image data image_data1[127:0] according to a clock user_clk generated by an internal PCIe IP core;

the PCIe image module generates an information code sc_encoding [1:0] with the bit width of 2 according to a clock user_clk generated by an internal PCIe IP core and an information code sc_encoding [1:0] used for sharing desktop resolution information data packets in the function of the test configuration module;

the dynamic clock output module generates a first group of clocks dyn_clk1, a second group of clocks dyn_clk2, a third group of clocks dyn_clk3 and a zero clearing signal resetn according to a clock outclk2 generated by a first clock IP core and an information code scrn_encode [1:0] with the bit width of 2 generated by the PCIe image module;

the memory control initialization module generates a write storage asynchronous FIFO write clock init_wrclk and a write storage asynchronous FIFO write enable signal init_wren according to a clock user_clk generated by an internal PCIe IP core;

the memory control initialization module generates image data init_data0[181:0] with bit width 182 according to a clock user_clk generated by an internal PCIe IP core and image data image_data1[127:0] with bit width 128 generated by the image processing synchronous FIFO; writing the image data init_data0[181:0] with the bit width of 182 into the writing storage asynchronous FIFO according to the writing storage asynchronous FIFO writing clock init_wrclk and a writing storage asynchronous FIFO writing enabling signal init_wren;

The memory control initialization module generates a read storage asynchronous FIFO2 write clock init_wrclk2, a read storage asynchronous FIFO2 write enable init_wren2 and address data init_data2[27:0] with a bit width of 28 according to a clock user_clk generated by an internal PCIe IP core; writing the address data init_data2[27:0] with the bit width of 28 into the read storage asynchronous FIFO2 according to the read storage asynchronous FIFO2 write clock init_wrclk2 and the read storage asynchronous FIFO2 write enabling init_wren 2;

the memory control user side module generates a write storage asynchronous FIFO read clock ctrl_rdclk and a write storage asynchronous FIFO read enable signal ctrl_rden according to ui_clk generated by an internal DDR3 IP core; then, according to the write storage asynchronous FIFO read clock ctrl_rdclk and the write storage asynchronous FIFO read enable signal ctrl_rden, reading the image data init_data0[181:0] with the bit width of 182 generated by a memory control initialization module from the write storage asynchronous FIFO, generating the image data ctrl_data0[181:0] with the bit width of 182, and sending the image data ctrl_data0[181:0] to the DDR3SDRAM IP core, so as to be transmitted to the DDR3SDRAM chip through a physical connection line;

the memory control user side module generates image data ctrl_data1[127:0] with the bit width of 128, a read storage asynchronous FIFO1 write clock signal ctrl_wrclk1 and a read storage asynchronous FIFO1 write enable signal ctrl_wren1 according to ui_clk generated by an internal DDR3 IP core; thereby writing the image data ctrl_data1[127:0] with the bit width of 128 into the read storage asynchronous FIFO1 according to the read storage asynchronous FIFO1 write clock signal ctrl_wrclk1 and the read storage asynchronous FIFO1 write enable signal ctrl_wren1;

The memory control user side module generates a read storage asynchronous FIFO2 read clock ctrl_rdclk2 and a read storage asynchronous FIFO2 read enable ctrl_rden2 according to ui_clks generated by the internal DDR3 IP core; and according to the read storage asynchronous FIFO2 read clock ctrl_rdclk2 and the read storage asynchronous FIFO2 read enable ctrl_rden2, reading the address data init_data2[27:0] with the bit width of 28 generated after the memory control initialization module generates from the read storage asynchronous FIFO 2;

the memory control initialization module generates a read storage asynchronous FIFO1 read clock init_rdclk1 and a read storage asynchronous FIFO1 read enable signal init_rden1 according to a third group of clocks dyn_clk3 generated by the dynamic clock output module; and according to the read storage asynchronous FIFO1 read clock init_rdclk1 and the read storage asynchronous FIFO1 read enable signal init_rden1, reading image data init_data1[127:0] which is generated by a memory control user terminal module and has a bit width of 128 and is generated after the image data ctrl_data1[127:0] is read from the read storage asynchronous FIFO 1;

the memory control initialization module generates an image display asynchronous FIFO write clock display_wrclk and an image display asynchronous FIFO write enable signal display_wren according to a third group of clocks dyn_clk3 generated by the dynamic clock output module;

The memory control initialization module generates image data display_data0[127:0] with the bit width of 128 according to a third group clock dyn_clk3 generated by the dynamic clock output module and the image data init_data1[127:0] with the bit width of 128 generated by the read storage asynchronous FIFO; writing the image data display_data0[127:0] with the bit width of 128 into the image display asynchronous FIFO according to the image display asynchronous FIFO write clock display_wrclk and an image display asynchronous FIFO write enable signal display_wren;

the display driving module generates an image display asynchronous FIFO read clock display_rdclk and an image display asynchronous FIFO read enable signal display_rden according to a first group of clocks dyn_clk1 generated by the dynamic clock output module; and reading the image data display_data1[15:0] generated after the image data display_data0[127:0] with the bit width of 128 generated by the memory control initialization module from the image display asynchronous FIFO according to the image display asynchronous FIFO read clock display_rdclk and the image display asynchronous FIFO read enable signal display_rden.

The PCIe bus-based dynamically reconfigurable high-speed desktop sharing system of the present invention is also characterized in that the PCIe image module includes: the device comprises a channel configuration module, an image processing channel module and an image response channel module.

The channel configuration module comprises: a data filtering logic unit and a data encoding logic unit;

the data filtering logic unit generates resolution information data reso_info [39:0] and resolution information data filt [39:0] with bit widths of 40 according to a clock user_clk generated by an internal PCIe IP core and data chnl_data0[63:0] with bit widths of 64 acquired from the PCIe IP core;

the data coding logic unit performs two-bit resolution information coding according to the acquired resolution information data filt [39:0];

the image processing channel module includes: the system comprises a data filtering logic unit, a frame control logic unit, a data reorganizing logic unit, an image processing synchronous FIFO writing logic unit and an image processing synchronous FIFO reading logic unit;

the data filtering logic unit compares the acquired resolution information data reso_info [39:0] with the data packet length to distinguish whether the data packet is an effective data packet, and when the data packet is an effective data packet, a frame effective signal frame_en is generated and sent to the frame control logic unit;

the frame control logic unit generates a frame stop signal frame_stop after receiving a data packet of a frame picture;

the data reorganization logic unit quantitatively converts the data chnl_data1[63:0] with the bit width of 64 obtained from the PCIe IP core to generate image data image_data0[31:0] with the bit width of 32;

The image processing synchronous FIFO write logic unit generates an image processing synchronous FIFO write enable signal image_wren and an image processing synchronous FIFO write clock image_wrclk according to a clock user_clk generated by an internal PCIe IP core; clearing the rest data of the image processing synchronous FIFO according to a clear signal resetn of the dynamic clock output module;

the image processing synchronous FIFO read logic unit generates an image processing synchronous FIFO read enable signal image_rden and an image processing synchronous FIFO read clock image_rdclk according to a clock user_clk generated by an internal PCIe IP core, and generates an image data start signal image_start according to a read end count value rd_data_count0[10:0] of the image processing synchronous FIFO;

the image response channel module includes: the response data control logic unit and the response data generation logic unit;

the response data control logic unit generates an enabling signal enabling of effective response data according to a frame stop signal frame_stop generated by the image processing channel module and sends the enabling signal enabling to the response data generation logic unit;

and the response data generation logic unit generates response data chnl_data2[63:0] with the bit width of 64 according to an enabling signal enable which is generated by the response data control logic unit and is effective to the response data, and sends the response data chnl_data2[63:0] to a PCIe IP core, so that the response data is driven by a PCIe card and is uploaded to a single acquisition module of the PCIe upper computer test subsystem.

The memory control initialization module includes: the memory control initializing writing module and the memory control initializing reading module.

The memory control initialization write module includes: the device comprises an effective data cache logic unit, an address data control logic unit and a write storage asynchronous FIFO write logic unit;

the effective data caching logic unit generates an enabling signal enable1 and image data0[143:0] with the bit width of 144 according to an image data start signal image_start and an image data image_data1[127:0] acquired by the PCIe image module and sends the enabling signal enable1 and the image data0[143:0] to the write-storage asynchronous FIFO write logic unit;

the address data control logic unit generates address data1[27:0] according to an enabling signal enable1 and sends the address data to the write storage asynchronous FIFO write logic unit; initializing address data according to a reset signal resetn of the dynamic clock output module;

the write asynchronous FIFO write logic unit generates a write asynchronous FIFO write clock init_wrclk, a write asynchronous FIFO write enable signal init_wren and image data init_data0[181:0] with the bit width of 182 according to the image data0[143:0], the enable signal enable1 and the address data1[27:0 ].

The memory control initialization read module includes: the system comprises an address data control logic unit, a read-storage asynchronous FIFO2 writing logic unit, a read-storage asynchronous FIFO1 reading logic unit and an image display asynchronous FIFO writing logic unit;

The address data control logic unit generates an enable signal enable2 and address data2[27:0] with the bit width of 28 according to an initialization start signal init_start generated by the display driving module and sends the enable signal enable2 and the address data to the read-storage asynchronous FIFO2 writing logic unit;

the read storage asynchronous FIFO2 write logic unit generates a read storage asynchronous FIFO2 write clock init_wrclk2, read storage asynchronous FIFO2 write enable init_wren2 and address data init_data2[27:0] with the bit width of 28 according to an enable signal enable2 and address data2[27:0] with the bit width of 28;

the read storage asynchronous FIFO1 read logic unit generates a read storage asynchronous FIFO1 read clock init_rdclk1 and a read storage asynchronous FIFO read enable signal init_rden1 according to a third group of clocks dyn_clk3 generated by the dynamic clock output module;

the image display asynchronous FIFO write logic unit generates an image display asynchronous FIFO write clock display_wrclk, an image display asynchronous FIFO write enable signal display_wren and image data display_data0[127:0] according to the image data init_data1[127:0] generated by the read storage asynchronous FIFO1 and the read end count value rd_data_count1[6:0] of the read storage asynchronous FIFO 1.

The memory control client module includes: the system comprises a write storage asynchronous FIFO read logic unit, a read storage asynchronous FIFO2 read logic unit, a priority processing logic unit, a write storage logic unit, a read storage logic unit and a read storage asynchronous FIFO1 write logic unit.

The write storage asynchronous FIFO read logic unit generates a write storage asynchronous FIFO read clock ctrl_rdclk and a write storage asynchronous FIFO read enable signal ctrl_rden according to an enable signal enable3 generated by the priority processing logic unit and ui_clk generated by the internal DDR3 IP core;

the read storage asynchronous FIFO2 read logic unit generates a read storage asynchronous FIFO2 read clock ctrl_rdclk2 and a read storage asynchronous FIFO2 read enable ctrl_rden2 according to an enable signal enable4 generated by the priority processing logic unit and ui_clk generated by the internal DDR3 IP core;

the priority processing logic unit generates an enabling signal enabling 3 and an enabling signal enabling 4 according to a null signal ctrl_empty of the write storage asynchronous FIFO and a null signal ctrl_empty2 of the read storage asynchronous FIFO2, and sends the enabling signal enabling 3 and the enabling signal enabling 4 to the write storage asynchronous FIFO read logic unit, the write storage logic unit, the read storage asynchronous FIFO2 read logic unit and the read storage logic unit;

the write storage logic unit sends the image data into the DDR3 SDRAM IP core according to the enabling signal enable3 of the priority processing logic unit and the image data ctrl_data0[181:0] generated by the write storage asynchronous FIFO, so that the image data is transmitted into the DDR3 SDRAM chip through a physical connecting line;

The read storage logic unit sends address data into the DDR3 SDRAM IP core according to an enabling signal enable4 of the priority processing logic unit and address data ctrl_data2[27:0] generated by the read storage asynchronous FIFO2, so that the address data is transmitted into the DDR3 SDRAM chip through a physical connection line;

the read storage logic unit takes out the image data3[127:0] of the corresponding address according to the address data entering the DDR3 SDRAM IP core and sends the image data to the read storage asynchronous FIFO1 write logic unit;

the read storage asynchronous FIFO1 writing logic unit generates image data ctrl_data1[127:0] with the bit width of 128, a read storage asynchronous FIFO1 writing clock ctrl_wrclk1 and a read storage asynchronous FIFO writing enable ctrl_wren1 according to ui_clk generated by an internal DDR3 IP core and image data3[127:0] of the read storage logic.

The display driving module includes: the device comprises an image display asynchronous FIFO reading logic unit, an image data reorganizing logic unit, a display initializing logic unit and a display time sequence control logic unit;

the image display asynchronous FIFO read logic unit generates an initialization start signal init_start according to a write-end count value wr_data_count1[9:0] of the image display asynchronous FIFO;

the image display asynchronous FIFO reading logic unit generates an image display asynchronous FIFO reading clock display_rdclk and an image display asynchronous FIFO reading enabling signal display_rden according to an enabling signal enable5 generated by the display time sequence control logic unit and a first group of clocks dyn_clk1 generated by the dynamic clock output module;

The image data reorganization logic unit generates image data4[23:0] with the bit width of 24 according to the image data display_data1[15:0] read from the image display asynchronous FIFO and sends the image data4[23:0] to the display time sequence control logic unit;

the display initialization logic unit generates an enable signal enable6 according to a read end count value rd_data_count2[12:0] of the image display asynchronous FIFO and sends the enable signal enable6 to the display time sequence control logic unit;

the display initialization logic unit performs initialization operation on the display time sequence control logic unit according to a reset signal resetn generated by the dynamic clock output module, namely, even if an enable signal enable6 fails;

the display time sequence control logic unit generates display data display_data2[26:0] with the bit width of 27 according to the acquired enabling signals enable6, the image data4[23:0] and the resolution information coding sc_encode [1:0], converts the display data display_data2[26:0] into TMDS transmission signals and then sends the TMDS transmission signals to an HDMI physical connection line, so that the HDMI display normally displays contents.

The dynamic clock output module comprises a dynamic clock output writing logic unit and a reset generation logic unit;

the dynamic clock output writing logic unit generates data and addresses according to a clock outclk2 generated by a first clock IP core and a resolution information code scrn_encode [1:0] generated by the PCIe image module and writes the data and addresses into a second clock IP core through an AXI bus, so that the second clock IP core generates a first group of clocks dyn_clk1, a second group of clocks dyn_clk2 and a third group of clocks dyn_clk3 with different frequencies;

The reset generation logic unit outputs the data and the address generated by the write logic unit to generate a reset signal resetn according to the dynamic clock.

Compared with the prior art, the invention has the beneficial technical effects that:

1. based on the scheme of the existing desktop sharing system, the invention provides a high-speed desktop sharing system capable of being dynamically reconfigured based on a PCIe bus, which can realize desktop sharing under the condition of no network; meanwhile, in the PCIe bus, an interface protocol of PCIe 2.0x2 is adopted, the theoretical bandwidth is 1GB/s, and the actual transmission bandwidth of the desktop sharing system is up to 80% of the theoretical bandwidth, so that the desktop sharing system becomes higher, and the real-time problem of the conventional desktop sharing system is solved.

2. The invention provides a stable and effective method for dynamically reconfiguring a clock IP core, which uses a lightweight AXI bus to stably transmit data, occupies less FPGA logic resources, solves the stability problem of the conventional desktop sharing system, and avoids the phenomenon of picture blocking. Meanwhile, the target end of the sharing system can reach the display requirement of 1080P high-definition image quality at the highest, and multiple display resolutions are provided for users to select.

3. The invention provides a bilinear interpolation image scaling algorithm which can be applied to a PCIe upper computer test subsystem. The method can convert the source end resolution of the desktop sharing system to adapt to the target end resolution, and the image integrity is hardly affected in the process, so that the desktop sharing system can support wider source end and target end desktop resolutions, and the limitation of single resolution is eliminated.

Drawings

FIG. 1 is a block diagram of a dynamically reconfigurable high-speed desktop sharing system based on a PCIe bus in accordance with the present invention;

fig. 2 is a block diagram of a PCIE image module according to the present invention;

FIG. 3 is a block diagram of a memory control initialization module according to the present invention;

FIG. 4 is a block diagram of a memory control client module according to the present invention;

FIG. 5 is a block diagram of a display driver module according to the present invention;

FIG. 6 is a block diagram of a dynamic clock output module according to the present invention;

FIG. 7 is a schematic diagram of a structure of reorganized data in the data reorganizing logic unit according to the present invention;

FIG. 8 is a communication diagram of a dynamically reconfigurable high-speed desktop sharing system based on a PCIe bus in accordance with the present invention.

Detailed Description

In this embodiment, a PCIe bus-based dynamically reconfigurable high-speed desktop sharing system is characterized by comprising: PCIe upper computer test subsystem and PCIe lower computer FPGA subsystem;

As shown in fig. 1, the PCIe host test subsystem includes: the device comprises a test configuration module, a single acquisition module and a continuous acquisition module;

the PCIe lower computer FPGA subsystem comprises: the system comprises a PCIe image module, an image processing synchronous FIFO, a memory control initialization module, a write memory asynchronous FIFO, a read memory asynchronous FIFO1, a read memory asynchronous FIFO2, a memory control user end module, an image display asynchronous FIFO, a display driving module and a dynamic clock output module; both sets of clocks outclk1, outclk2 are homologous clocks generated by the first clock IP core; three groups of clocks dyn_clk1, dyn_clk2 and dyn_clk3 are all homologous clocks generated by the dynamic clock output module;

the driver adopts a driver provided by a RIFFA framework, the main function of the RIFFA driver is to manage a memory and a PCIE interface, and the user space program can call a library to realize the driving of the RIFFA at the bottom layer and finally realize the data communication between the PC and the FPGA board card;

and the test configuration module generates a function containing the resolution information data packet for the shared desktop target end according to the header file provided by the PCIe card driver, so that the resolution information data packet for the shared desktop target end in the function is issued to the PCIe lower computer FPGA subsystem by using the PCIe card driver. The system shares high-definition image quality with highest resolution reaching 1080P at the target end of the desktop;

The single acquisition module generates a function containing a shared desktop single-frame picture information data packet for adapting to the resolution of the shared desktop target end according to the header file provided by the PCIe card driver, so that the shared desktop single-frame picture information data packet for adapting to the resolution of the shared desktop target end in the function is issued to the PCIe lower computer FPGA subsystem by using the PCIe card driver; then a PCIe image module of the PCIe lower computer FPGA subsystem transmits a preset shared desktop single-frame picture information data packet tail to a single acquisition module, and simultaneously indicates that the single acquisition module has a receiving and transmitting function; a bilinear interpolation image scaling algorithm is also provided in the function of the single acquisition module, so that arbitrary image scaling is performed for the shared desktop source end. The system shares the ultrahigh definition image quality with the highest resolution of 2K at the source end of the desktop;

the continuous acquisition module also generates a function containing a shared desktop single-frame picture information data packet for adapting to the resolution of a shared desktop target end according to the header file provided by the PCIe card driver, continuously transmits the shared desktop single-frame picture information data packet in the function to the PCIe lower computer FPGA subsystem by using the PCIe card driver, and then continuously transmits the package tail of the preset shared desktop single-frame picture information data packet to the continuous acquisition module by using the PCIe image module of the PCIe lower computer FPGA subsystem. Meanwhile, the continuous acquisition module is indicated to have a receiving and transmitting function; the continuous acquisition module comprises a single acquisition module, and can also perform random image scaling aiming at the shared desktop source end, so that the continuous acquisition module has consistency in function realization;

The PCIe image module generates image data image_data0[31:0] with the bit width of 32 according to a clock user_clk generated by an internal PCIe IP core, an image processing synchronous FIFO write enable signal image_wren and an image processing synchronous FIFO write clock image_wrclk, and writes the image data image_data0[31:0] into an image processing synchronous FIFO according to the image processing synchronous FIFO write enable signal image_wren and the image processing synchronous FIFO write clock image_wrclk; the image processing synchronization FIFO generates a full signal image full. The image_full high level indicates that the image processing synchronization FIFO is already full, and data cannot be written into the image processing synchronization FIFO continuously;

the PCIe image module generates an image processing synchronous FIFO read enable signal image_rden and an image processing synchronous FIFO read clock image_rdclk according to a clock user_clk generated by an internal PCIe IP core, and generates image data image_data1[127:0] with a bit width of 128 according to the image processing synchronous FIFO read enable signal image_rden and the image processing synchronous FIFO read clock image_rdclk after reading the image data image_data0[31:0] with the bit width of 32 generated by the PCIe image module from the image processing synchronous FIFO; the image processing synchronization FIFO generates a null signal image_empty. The image_empty high level indicates that the image processing synchronization FIFO has been empty and that data cannot continue to be read out of the image processing synchronization FIFO;

the PCIe image module generates an information code scrn_encoding [1:0] with the bit width of 2 according to a clock user_clk generated by an internal PCIe IP core and an information data packet with the resolution ratio of the shared desktop target end in the function of the test configuration module; information coding of 0 indicates that the resolution of the target end of the shared desktop is 1024×768, information coding of 1 indicates that the resolution of the target end of the shared desktop is 1280×768, and information coding of 2 indicates that the resolution of the target end of the shared desktop is 1920×1080;

the dynamic clock output module generates a first group of clocks dyn_clk1, a second group of clocks dyn_clk2, a third group of clocks dyn_clk3 and a zero clearing signal resetn according to a clock outclk2 generated by a first clock IP core and an information code scrn_encode [1:0] with the bit width of 2 generated by a PCIe image module;

the memory control initialization module generates image data init_data0[181:0] with the bit width of 182 according to a clock user_clk generated by an internal PCIe IP core and image data image_data1[127:0] with the bit width of 128 generated by an image processing synchronous FIFO; writing the image data init_data0[181:0] into the writing storage asynchronous FIFO according to the writing storage asynchronous FIFO writing clock init_wrclk and the writing storage asynchronous FIFO writing enabling signal init_wren; the write store asynchronous FIFO generates a full signal initfull. The init_full high level indicates that the write store asynchronous FIFO is full and cannot continue writing data to the write store asynchronous FIFO;

The memory control user terminal module generates a write storage asynchronous FIFO read clock ctrl_rdclk and a write storage asynchronous FIFO read enable signal ctrl_rden according to ui_clk generated by the internal DDR3 IP core; reading the image data init_data0[181:0] generated by the memory control initialization module from the write storage asynchronous FIFO according to the write storage asynchronous FIFO read clock ctrl_rdclk and the write storage asynchronous FIFO read enable signal ctrl_rden to generate image data ctrl_data0[181:0] with the bit width of 182, and transmitting the image data ctrl_data0[181:0] to the DDR3 SDRAM chip through a physical connection line; DDR3 SDRAM belongs to external chip, and it links to each other with the FPGA chip through the physical connection line. The write store asynchronous FIFO generates a null signal ctrl_empty. The ctrl_empty high level indicates that the write store asynchronous FIFO has been empty and cannot continue reading data from the write store asynchronous FIFO;

the memory control initialization module generates a read storage asynchronous FIFO2 write clock init_wrclk2, a read storage asynchronous FIFO2 write enable init_wren2 and address data init_data2[27:0] with a bit width of 28 according to a clock user_clk generated by an internal PCIe IP core; writing address data init_data2[27:0] into the read-storage asynchronous FIFO2 according to a read-storage asynchronous FIFO2 write clock init_wrclk2 and a read-storage asynchronous FIFO2 write enable init_wren 2; the read store asynchronous FIFO2 generates a full signal initfull 2. The init_full2 high level indicates that the read-storage asynchronous FIFO2 is already full, and data cannot be written into the read-storage asynchronous FIFO2 continuously;

The memory control user side module generates a read storage asynchronous FIFO2 read clock ctrl_rdclk2 and a read storage asynchronous FIFO2 read enable ctrl_rden2 according to ui_clk generated by the internal DDR3 IP core; and generating address data ctrl_data2[27:0] with a bit width of 28 after reading the address data init_data2[27:0] generated by the memory control initialization module from the read storage asynchronous FIFO2 according to the read storage asynchronous FIFO2 read clock ctrl_rdclk2 and the read storage asynchronous FIFO2 read enable ctrl_rden2; the read store asynchronous FIFO2 generates a null signal ctrl_empty2. The ctrl_empty2 high indicates that the read store asynchronous FIFO2 has been empty and is unable to continue reading data from the read store asynchronous FIFO 2;

the memory control user side module generates image data ctrl_data1[127:0] with the bit width of 128, a read storage asynchronous FIFO1 write clock signal ctrl_wrclk1 and a read storage asynchronous FIFO1 write enable signal ctrl_wren1 according to ui_clk generated by an internal DDR3 IP core; thereby writing the image data ctrl_data1[127:0] into the read-storage asynchronous FIFO1 according to the read-storage asynchronous FIFO1 write clock signal ctrl_wrclk1 and the read-storage asynchronous FIFO1 write enable signal ctrl_wren1; the read store asynchronous FIFO1 generates a full signal ctrl_full1. The ctrl_full1 high level indicates that the read store asynchronous FIFO1 is already full and cannot continue writing data to the read store asynchronous FIFO 1;

The memory control initialization module generates a read storage asynchronous FIFO1 read clock init_rdclk1 and a read storage asynchronous FIFO1 read enable signal init_rden1 according to a third group of clocks dyn_clk3 generated by the dynamic clock output module; and according to the read clock init_rdclk1 of the read storage asynchronous FIFO1 and the read enable signal init_rden1 of the read storage asynchronous FIFO1, reading the image data init_data1[127:0] which is generated by the memory control client module and has the bit width of 128 from the read storage asynchronous FIFO 1; the read store asynchronous FIFO1 generates a null signal init_empty1.init_empty1 high indicates that the read store asynchronous FIFO1 has been empty and cannot continue reading data from the read store asynchronous FIFO 1;

the memory control initialization module generates image data display_data0[127:0] with the bit width of 128 according to the third group of clocks dyn_clk3 generated by the dynamic clock output module and the image data init_data1[127:0] with the bit width of 128 generated by the read storage asynchronous FIFO; writing image data display_data0[127:0] into the image display asynchronous FIFO according to an image display asynchronous FIFO write clock display_wrclk and an image display asynchronous FIFO write enable signal display_wren; the image display asynchronous FIFO generates a full signal display full. The display_full high level indicates that the image display asynchronous FIFO is full, and data cannot be written into the image display asynchronous FIFO continuously;

The display driving module generates an image display asynchronous FIFO read clock display_rdclk and an image display asynchronous FIFO read enable signal display_rden according to a first group of clocks dyn_clk1 generated by the dynamic clock output module; and reads the image data display_data1[15:0] generated after the image data display_data0[127:0] with the bit width of 128 generated by the memory control initialization module from the image display asynchronous FIFO according to the image display asynchronous FIFO read clock display_rdclk and the image display asynchronous FIFO read enable signal display_rden. And the converted TMDS transmission signals are sent to an HDMI interface physical connection line, so that the HDMI display can normally display contents. The HDMI interface belongs to an external element and is connected with the FPGA chip through a physical connecting wire. The image display asynchronous FIFO generates a null signal display_empty. The display_empty high indicates that the image display asynchronous FIFO has been empty and no data can be read from the image display asynchronous FIFO.

In this embodiment, as shown in fig. 2, the PCIe image module includes: the system comprises a channel configuration module, an image processing channel module and an image response channel module;

the data coding logic unit performs two-bit resolution information coding according to the acquired resolution information data filt [39:0]; an information encoding of 0 means a resolution of 1920×1080; an information encoding of 1 means a resolution of 1280×768; encoding information as 2 means that the resolution is 1024×768;

the data filtering logic unit compares the acquired resolution information data reso_info [39:0] with the data packet length to distinguish whether the data packet is a valid data packet, and when the data packet is a valid data packet, generates a frame valid signal frame_en and sends the frame valid signal frame_en to the frame control logic unit. And when the data packet is invalid, the frame valid signal frame_en is shielded, and the PCIe card drive is required to be reused to send the shared desktop single-frame picture information data packet which is used for adapting to the resolution of the shared desktop target end in the single acquisition module function to the PCIe lower computer FPGA subsystem. The data packet length is obtained by analyzing after being acquired from a PCIe IP core;

as shown in fig. 7, the data reorganizing logic unit generates data1 and data 2 after extracting some fixed bits according to the data chnl_data1[63:0] with the bit width of 64 obtained from the PCIe IP core, and then the data1 and the data 2 are spliced to form image data image_data0[31:0] with the bit width of 32;

the image processing synchronous FIFO write logic unit generates an image processing synchronous FIFO write enable signal image_wren and an image processing synchronous FIFO write clock image_wrclk according to a clock user_clk generated by the internal PCIe IP core; writing the image data image_data0[31:0] with the bit width of 32 into the image processing synchronous FIFO according to the image processing synchronous FIFO write enable signal image_wren and the image processing synchronous FIFO write clock image_wrclk; in order to ensure the integrity of one frame of image, clearing the rest data of the image processing synchronous FIFO according to a clear signal resetn of the dynamic clock output module;

the image processing synchronous FIFO read logic unit generates an image processing synchronous FIFO read enable signal image_rden and an image processing synchronous FIFO read clock image_rdclk according to a clock user_clk generated by an internal PCIe IP core; reading image data image_data1[127:0] with the bit width of 128 from the image processing synchronous FIFO according to an image processing synchronous FIFO read enable signal image_rden and an image processing synchronous FIFO read clock image_rdclk; then, an image data start signal image_start is generated according to the read end count value rd_data_count0[10:0] of the image processing synchronization FIFO. Limited by the type of the DDR3SDRAM chip externally arranged at this time, the bit width of a read data port of the image processing synchronous FIFO is 128. When the read-end count value rd_data_count0[10:0] of the image processing synchronization FIFO is 64, it is indicated that the image processing synchronization FIFO has cached 64 image data image_data1[127:0] with a bit width of 128 for other modules to use;

the response data control logic unit generates an enabling signal enabling effective in response data according to a frame stop signal frame_stop generated by the image processing channel module, and sends the enabling signal enabling effective in response data to the response data generation logic unit;

the response data generation logic unit generates response data chnl_data2[63:0] with the bit width of 64 according to the response data effective enabling signal generated by the response data control logic unit, and sends the response data chnl_data2[63:0] to the PCIe IP core, namely the preset packet tail of the shared desktop single-frame picture information data packet, and then the response data is uploaded to a single acquisition module of the PCIe upper computer test subsystem through a PCIe card driver. And the single acquisition module analyzes the package tail of the single frame picture information data package of the shared desktop to complete the desktop sharing.

In this embodiment, as shown in fig. 3, the memory control initialization module includes: a memory control initialization writing module and a memory control initialization reading module;

The effective data cache logic unit generates an enabling signal enable1 and image data0[143:0] with the bit width of 144 according to an image data start signal image_start and image data1[127:0] acquired by the PCIe image module and sends the enabling signal enable1 and the image data0[143:0] to the write-storage asynchronous FIFO write logic unit. The image data0[143:0] is a part of the image data init_data0[181:0] generated by the write storage asynchronous FIFO write logic unit;

the address data control logic unit generates address data1[27:0] according to an enable signal enable1 and sends the address data to the write storage asynchronous FIFO write logic unit; and initializing address data according to a reset signal resetn of the dynamic clock output module. The address data1[27:0] is a part of the image data init_data0[181:0] generated by the write storage asynchronous FIFO write logic unit. DDR3 SDRAM is used for storing image data, and before storing the image data, an address needs to be indicated, namely the corresponding address stores the corresponding image data;

the write asynchronous FIFO write logic unit generates a write asynchronous FIFO write clock init_wrclk, a write asynchronous FIFO write enable signal init_wren and image data init_data0[181:0] with the bit width of 182 according to the image data0[143:0], the enable signal enable1 and the address data1[27:0 ]; writing the image data init_data0[181:0] into the writing storage asynchronous FIFO according to the writing storage asynchronous FIFO writing clock init_wrclk and the writing storage asynchronous FIFO writing enabling signal init_wren;

the address data control logic unit generates an enable signal enable2 and address data2[27:0] with the bit width of 28 according to an initialization start signal init_start generated by the display driving module and sends the enable signal enable2 and the address data to the read-storage asynchronous FIFO2 writing logic unit. Because the DDR3 SDRAM stores image data at corresponding addresses, specific addresses need to be indicated when the image data are read;

the read storage asynchronous FIFO2 write logic unit generates a read storage asynchronous FIFO2 write clock init_wrclk2, a read storage asynchronous FIFO2 write enable init_wren2 and address data init_data2[27:0] with the bit width of 28 according to the enable signal enable2 and the address data2[27:0] with the bit width of 28; writing address data init_data2[27:0] into the read-storage asynchronous FIFO2 according to a read-storage asynchronous FIFO2 write clock init_wrclk2 and a read-storage asynchronous FIFO2 write enable init_wren 2;

the read storage asynchronous FIFO1 read logic unit generates a read storage asynchronous FIFO1 read clock init_rdclk1 and a read storage asynchronous FIFO read enable signal init_rden1 according to a third group of clocks dyn_clk3 generated by the dynamic clock output module; and reads the image data init_data1[127:0] from the read store asynchronous FIFO1 according to the read store asynchronous FIFO1 read clock init_rdclk1 and the read store asynchronous FIFO1 read enable signal init_rden1. The image data init_data1[127:0] generated by the read-storage asynchronous FIFO1 is part of the image data display_data0[127:0 ];

The image display asynchronous FIFO write logic unit generates an image display asynchronous FIFO write clock display_wrclk, an image display asynchronous FIFO write enable signal display_wren and image data display_data0[127:0] according to the image data init_data1[127:0] generated by the read storage asynchronous FIFO1 and the read end count value rd_data_count1[6:0] of the read storage asynchronous FIFO 1. Limited by the type of the DDR3 SDRAM chip externally arranged at this time, the bit width of a read data port of the read-storage asynchronous FIFO1 is 128. When the read-side count value rd_data_count1[6:0] of the read-storage asynchronous FIFO1 is 64, it is indicated that the read-storage asynchronous FIFO1 has cached 64 image data init_data1[127:0] with a bit width of 128 for other modules to read.

In this embodiment, as shown in fig. 4, the memory control client module includes: the system comprises a write storage asynchronous FIFO read logic unit, a read storage asynchronous FIFO2 read logic unit, a priority processing logic unit, a write storage logic unit, a read storage logic unit and a read storage asynchronous FIFO1 write logic unit;

the priority processing logic unit generates an enable signal enable3 and an enable signal enable4 according to a null signal ctrl_empty of the write storage asynchronous FIFO and a null signal ctrl_empty2 of the read storage asynchronous FIFO2, and the enable signal enable3 is sent to the write storage asynchronous FIFO read logic unit and the write storage logic unit; enabling signal enable4 is sent to a read storage asynchronous FIFO2 read logic unit and a read storage logic unit; the write storage asynchronous FIFO generates a null signal ctrl_empty, when the null signal ctrl_empty is high level, the data in the write storage asynchronous FIFO is read, and then the data ctrl_data0[181:0] read from the write storage asynchronous FIFO is sent into the DDR3 SDRAM IP core through a write storage logic unit; the read storage asynchronous FIFO2 generates a null signal ctrl_empty2, when the null signal ctrl_empty2 is in a high level, the data in the read storage asynchronous FIFO2 is completely read, address data ctrl_data2[27:0] read from the read storage asynchronous FIFO2 is sent into the DDR3 SDRAM IP core through a read storage logic unit, and finally the corresponding data stored by the corresponding address is read from the DDR3 SDRAM IP core through the read storage logic unit;

The write storage logic unit sends the image data into the DDR3 SDRAM IP core according to the enabling signal enable3 of the priority processing logic unit and the image data ctrl_data0[181:0] generated by the write storage asynchronous FIFO, so that the image data is transmitted into the DDR3 SDRAM chip through a physical connection line;

the read-store asynchronous FIFO1 write logic unit generates image data ctrl_data1[127:0] with a bit width of 128, a read-store asynchronous FIFO1 write clock ctrl_wrclk1 and a read-store asynchronous FIFO write enable ctrl_wren1 from ui_clk generated by the internal DDR3 IP core and image data3[127:0] of the read-store logic.

In this embodiment, as shown in fig. 5, the display driving module includes: the device comprises an image display asynchronous FIFO reading logic unit, an image data reorganizing logic unit, a display initializing logic unit and a display time sequence control logic unit;

the image display asynchronous FIFO read logic unit generates an initialization start signal init_start according to a write-end count value wr_data_count1[9:0] of the image display asynchronous FIFO; when the write-end count value wr_data_count1[9:0] of the image display asynchronous FIFO is less than 320, the data amount of the image display asynchronous FIFO buffer memory is insufficient, and the data needs to be read from the DDR3 SDRAM IP core again to be filled into the image display asynchronous FIFO;

The image display asynchronous FIFO read logic unit generates an image display asynchronous FIFO read clock display_rdclk and an image display asynchronous FIFO read enable signal display_rden according to an enable signal enable5 generated by the display time sequence control logic unit and a first group of clocks dyn_clk1 generated by the dynamic clock output module;

the display initialization logic unit generates an enable signal enable6 according to a read end count value rd_data_count2[12:0] of the image display asynchronous FIFO and sends the enable signal enable6 to the display time sequence control logic unit; when the read-end count value rd_data_count2[12:0] of the image display asynchronous FIFO is 2560, the data amount of the image display asynchronous FIFO buffer memory is enough to be displayed, and an enable signal enable6 is used for starting the normal execution of display time sequence control logic;

the display initialization logic unit performs initialization operation on the display time sequence control logic unit according to the reset signal resetn generated by the dynamic clock output module, namely even if the enable signal enable6 is invalid;

The display time sequence control logic unit generates display data display_data2[26:0] with the bit width of 27 according to the acquired enabling signals enable6, the image data4[23:0] and the resolution information code scrn_encode [1:0], and converts the display data display_data2[26:0] into TMDS transmission signals through an 8b10b coding module and a parallel-serial module provided by an Xilinx official, and then transmits the TMDS transmission signals to an HDMI physical connection line, so that the HDMI display normally displays contents. The system uses an external HDMI interface, and the HDMI interface adopts TMDS standard to transmit data.

In this embodiment, as shown in fig. 6, the dynamic clock output module includes a dynamic clock output write logic unit and a reset generation logic unit;

the dynamic clock output writing logic unit generates data and addresses according to a clock outclk2 generated by the first clock IP core and resolution information code scrn_encode [1:0] generated by the PCIe image module and writes the data and addresses into the second clock IP core through an AXI bus according to a lightweight AXI time sequence, so that the second clock IP core generates a first group of clocks dyn_clk1, a second group of clocks dyn_clk2 and a third group of clocks dyn_clk3 with different frequencies. The resolution information codes have three codes, so the second clock IP core will also generate a first set of clocks dyn_clk1, a second set of clocks dyn_clk2 and a third set of clocks dyn_clk3 with three different frequencies. The input clock of the second clock IP core is a clock outclk2 generated by the first clock IP core;

The reset generation logic unit outputs the data and address generated by the write logic unit to generate a reset signal resetn according to the dynamic clock. The clear signal is sent to the PCIe image module, the memory control initialization module and the display driving module.

As shown in fig. 8, the PCIe host testing subsystem of the high-speed desktop sharing system uses PCIe card driver to send the data of the shared desktop source end to the PCIe host FPGA subsystem, and then performs high-speed real-time display on the shared desktop target end. The PCIe interface, the DDR3 SDRAM chip, the HDMI interface and the FPGA chip are all independent external devices.

In summary, the present invention provides a PCIe bus-based dynamically reconfigurable high-speed desktop sharing system, wherein a bilinear interpolation image scaling algorithm applicable in a PCIe host test subsystem is provided, and the algorithm can convert the source resolution of the desktop sharing system to adapt to the target resolution. The method for dynamically reconfiguring the clock IP core stably and effectively is provided, and the lightweight AXI bus is used for stably transmitting data, so that less FPGA logic resources are occupied, the stability problem of the conventional desktop sharing system is solved, and the phenomenon of picture blocking is avoided. Finally, a PCIe bus is adopted, and an interface protocol of PCIe 2.0 multiplied by 2 is adopted to achieve high bandwidth utilization rate, so that the real-time problem of the existing desktop sharing system is solved, and meanwhile, the desktop sharing can be performed under the condition of no network.

Claims

1. A PCIe bus-based dynamically reconfigurable high-speed desktop sharing system, comprising: PCIe upper computer test subsystem and PCIe lower computer FPGA subsystem;

2. The PCIe bus-based dynamically reconfigurable high-speed desktop sharing system of claim 1, wherein the PCIe image module comprises: the system comprises a channel configuration module, an image processing channel module and an image response channel module;

3. The PCIe bus-based dynamically reconfigurable high-speed desktop sharing system of claim 1, wherein the memory control initialization module comprises: a memory control initialization writing module and a memory control initialization reading module;

the write asynchronous FIFO write logic unit generates a write asynchronous FIFO write clock init_wrclk, a write asynchronous FIFO write enable signal init_wren and image data init_data0[181:0] with the bit width of 182 according to the image data0[143:0], the enable signal enable1 and the address data1[27:0 ];

4. The PCIe bus-based dynamically reconfigurable high-speed desktop sharing system of claim 1, wherein the memory control client module comprises: the system comprises a write storage asynchronous FIFO read logic unit, a read storage asynchronous FIFO2 read logic unit, a priority processing logic unit, a write storage logic unit, a read storage logic unit and a read storage asynchronous FIFO1 write logic unit;

5. The PCIe bus-based dynamically reconfigurable high-speed desktop sharing system of claim 1, wherein the display driver module comprises: the device comprises an image display asynchronous FIFO reading logic unit, an image data reorganizing logic unit, a display initializing logic unit and a display time sequence control logic unit;

6. The PCIe bus-based dynamically reconfigurable high-speed desktop sharing system of claim 1, wherein the dynamic clock output module comprises a dynamic clock output write logic unit, a reset generation logic unit;