CN116598340A - SiC MOSFET and manufacturing process method thereof - Google Patents
SiC MOSFET and manufacturing process method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
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- 239000002184 metal Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 28
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- 229910010271 silicon carbide Inorganic materials 0.000 description 51
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 235000012239 silicon dioxide Nutrition 0.000 description 8
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- 238000010586 diagram Methods 0.000 description 4
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- 239000004065 semiconductor Substances 0.000 description 4
- -1 Silicon carbide metal oxide Chemical class 0.000 description 3
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
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- 239000011574 phosphorus Substances 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- 229910018481 Ni—Cu Inorganic materials 0.000 description 1
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
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Abstract
The application relates to a SiC MOSFET and a manufacturing process method thereof, which can reduce the follow current loss of a parasitic body diode, ensure the normal conduction and reverse voltage withstanding characteristics of the SiC MOSFET, and the SiC MOSFET comprises a drain electrode metal layer, a substrate, a drift layer, a gate insulating layer, a gate, source electrode metal layers, a P+ Ge doped region, a well region and a source region which are distributed on two sides of the gate from bottom to top, wherein the P+ Ge doped region, the well region and the source region are positioned in the drift layer, the well region is positioned in the top regions on two sides of the drift layer, the P+ Ge doped region longitudinally penetrates through the well region and then contacts with the drift layer, and the well region is divided into two regions: the source region is positioned at the right-angle inner side of the L-shaped region, the outer side end of the P+ Ge doped region is contacted with the inner side end of the L-shaped region, the inner side end of the P+ Ge doped region is contacted with the outer side end of the source region and the bottom side end of the L-shaped region, the source metal layer is positioned at the top ends of the source region and the P+ Ge doped region, and the P+ Ge doped region and the drift layer form a heterojunction.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a planar gate SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) with controllable conduction voltage drop.
Background
Silicon carbide metal oxide field effect transistors (i.e., siC MOSFETs), which are typical of third generation semiconductors, are widely used in high voltage and high speed switches for 5G, smart cars, power electronics, etc. because of their small parasitic capacitance, small breakdown field, small volume, fast heat dissipation, low energy loss, etc., when SiC MOSFETs are used as free wheeling diodes, due to their wide bandgap characteristics, parasitic body diodes present between their sources and drains have a higher forward voltage drop than dedicated free wheeling diodes, and their turn-on voltage drop is typically 2V-3V, which is much greater than Si material devices, in which case the problem of large free wheeling loss of the parasitic body diodes occurs in application.
Disclosure of Invention
Aiming at the technical problem of large freewheel loss of a parasitic body diode in the prior art, the application provides the SiC MOSFET which has simple and reasonable structural design and can reduce the freewheel loss of the parasitic body diode.
In order to achieve the above purpose, the application adopts the following technical scheme:
the SiC MOSFET comprises a drain metal layer, a substrate, a drift layer, a gate insulating layer, a gate and source metal layers, wherein the drain metal layer, the substrate, the drift layer, the gate insulating layer, the gate and the source metal layers are sequentially distributed on two sides of the gate, and the SiC MOSFET is characterized by further comprising a P+Ge doped region, a well region and a source region, wherein the P+Ge doped region, the well region and the source region are positioned in the drift layer, the well region is positioned in top regions on two sides of the drift layer, and the P+Ge doped region longitudinally penetrates through the well region and then contacts with the drift layer, and divides the well region into two regions: the source region is located at the right-angle inner side of the L-shaped region, the outer side end of the P+ Ge doped region is in contact with the inner side end of the L-shaped region, the inner side end of the P+ Ge doped region is in contact with the outer side end of the source region and the bottom side end of the L-shaped region, the source metal layer is located at the top ends of the source region and the P+ Ge doped region and forms ohmic contact with the source region and the P+ Ge doped region respectively, and the P+ Ge doped region and the drift layer form heterojunction.
It is further characterized in that,
the substrate is a SiC substrate;
further, the thickness of the P+ Ge doped region is 160 times of the thickness of the thinnest part of the well region, and the doping concentration of the P+ Ge doped region is 160 times of the thickness of the well region;
further, the doping concentration of the well region is 6×10 17 cm-3~1.2×10 18 cm-3, the doping concentration of the source region is 1×10 18 cm-3~2×10 18 cm-3；
Further, the drift layer is an N+ SiC doped region, and the P+ Ge doped region and the N+ SiC doped region form a heterojunction;
further, the L-shaped region comprises a vertical region and a horizontal region, the thickness range of the vertical region is 200 nm-400 nm, the thickness range of the horizontal region is 20 nm-50 nm, and the thickness of the source region is the difference between the thickness of the horizontal region and the thickness of the vertical region.
A method of making a SiC MOSFET, the method comprising:
s1, providing a substrate;
s2, depositing a drain metal layer at the bottom end of the substrate, and epitaxially growing a drift layer at the top end of the substrate;
s3, injecting ions into the tops of two sides of the drift layer to form a well region;
s4, etching the position, close to the outer edge, of the middle part of the well region to form a second through hole penetrating through the well region, and dividing the well region into two strip-shaped regions by the second through hole: the first strip-shaped region and the second strip-shaped region epitaxially grow a P+Ge doped region in the second through hole;
s5, implanting ions into the outer side area of the top end of the second strip-shaped area to form a source area;
s6, depositing a source metal layer at the top ends of the source region and the P+Ge doped region;
and S7, sequentially depositing a gate insulating layer and a gate layer in the middle of the top end of the drift layer.
It is further characterized in that,
in step S3, the step of forming the well region by using a photolithography process and an ion implantation process includes: s31, covering a first barrier layer on the top end of the drift layer;
s32, etching and exposing the first barrier layer to form a first through hole, wherein the top ends of two sides of the drift layer are exposed by the first through hole;
s33, implanting ions into the tops of the two sides of the drift layer through the first through hole by adopting an ion implantation process to form the well region;
s34, removing the first barrier layer;
further, the material of the trap area is SIC, and the implanted ions of the trap area are boron ions;
further, in step S4, the step of forming the p+ge doped region by using a photolithography process and a deposition process includes:
s41, covering a second barrier layer on the drift layer and the top end of the well region;
s42, sequentially etching and exposing the second barrier layer and the well region, and forming a second through hole in the well region;
s43, depositing a P+Ge material in the second through hole to form a P+Ge doped region;
s44, removing the second barrier layer;
further, in step S5, the step of forming the source region by using a photolithography process and an ion implantation process includes:
s51, covering a third barrier layer on the top ends of the second strip-shaped region and the P+Ge doped region;
s52, etching and exposing the third barrier layer to form a third through hole, wherein the third through hole exposes the outer side area of the top end of the second strip-shaped area;
s53, implanting ions into the outer side area of the top end of the second strip-shaped area through the third through hole to form the source area;
s54, removing the third barrier layer;
further, the source region is made of SIC, and the implanted ions are phosphorus ions;
further, in step S6, the step of forming the source metal layer by using a photolithography process and a deposition process includes:
s61, covering a fourth barrier layer on the top ends of the first strip-shaped region, the P+Ge doped region and the source region;
s62, etching and exposing the fourth barrier layer to form a fourth through hole, wherein the top ends of the P+Ge doped region and the source region are exposed by the fourth through hole;
s63, depositing a metal material in the fourth through hole to form a source metal layer;
s64, removing the fourth barrier layer;
further, the source electrode metal layer is made of nickel-copper alloy;
further, in step S7, the step of forming the gate insulating layer by using a photolithography process and a deposition process includes: s71, covering a fifth barrier layer in the middle of the top end of the drift layer;
s72, etching exposure is carried out on the fifth barrier layer to form a fifth through hole, and the middle of the top end of the drift layer is exposed by the fifth through hole;
s73, depositing a gate insulating layer in the fifth through hole;
s74, depositing a metal material on the top end of the gate insulating layer to form a gate metal layer;
further, the material of the gate insulating layer is silicon dioxide;
further, the gate metal layer is made of aluminum;
further, the first to fifth barrier layers are made of silicon dioxide.
The structure of the application can achieve the following beneficial effects: the P+ Ge doped region is arranged in the SiC MOSFET, the P+ Ge doped region and the drift layer form a heterojunction, the heterojunction is used as a working mechanism of the parasitic body diode, a carrier injection phenomenon exists, the follow current capacity of the parasitic body diode can be improved, and as the conduction performance of the Ge material is better than that of the Si material in the traditional follow current diode, the conduction voltage drop of the parasitic body diode in the SiC MOSFET can be effectively reduced, and the power consumption of the parasitic body diode is reduced due to the reduction of the conduction voltage drop under the condition that the conduction current is unchanged, namely the follow current loss of the parasitic body diode is reduced.
In addition, the SiC MOSFET device only comprises a single heterojunction formed by the P+Ge doped region and the drift layer, the conduction voltage drop of the single heterojunction is about 0.4V, and compared with the two junction structures in the traditional SiC MOSFET device, the conduction voltage drop of the single heterojunction is lower, and under the condition that the freewheel capacity of the parasitic body diode is unchanged, the power consumption of the parasitic body diode is reduced due to the reduction of the conduction voltage drop, namely, the freewheel power consumption of the parasitic body diode is reduced.
In the SiC MOSFET, the P+Ge doped region and the drift layer form a heterojunction freewheel passage, and the freewheel passage is not overlapped or contacted with a normal conduction channel of the device, so that the heterojunction has no influence on the conduction channel of the device, namely has no influence on the gate characteristic of the device, and the conduction voltage drop of the heterojunction is not influenced by the conduction currents of other heterojunctions or other passages, so that the controllability of the conduction voltage drop is high, and the normal conduction of the device is ensured.
Drawings
FIG. 1 is a schematic cross-sectional view of a SiC MOSFET of the present application;
FIG. 2 is a schematic diagram of a cross-sectional structure of a well region formed in step S33 in the process of fabricating a SiC MOSFET of the present application;
FIG. 3 is a schematic cross-sectional view of the formation of a P+ Ge doped region at step S43 in the process of fabricating a SiC MOSFET of the present application;
FIG. 4 is a schematic cross-sectional view of the source region formed in step S53 in the process of manufacturing a SiC MOSFET of the present application;
FIG. 5 is a schematic diagram showing a cross-sectional structure of a source metal layer formed in step S63 in the process of fabricating a SiC MOSFET of the present application;
FIG. 6 is a schematic diagram of a cross-sectional structure of a deposited gate insulating layer at step S73 in the process of fabricating a SiC MOSFET of the present application;
FIG. 7 is a schematic diagram of a cross-sectional structure of a deposited gate at step S74 in a process for fabricating a SiC MOSFET of the present application;
FIG. 8 is a flow chart of a process for fabricating a SiC MOSFET of the present application;
reference numerals: the semiconductor device comprises a drain metal layer 1, a substrate 2, a drift layer 3, a gate insulating layer 4, a gate 5, source metal layers 6 distributed on two sides of the gate 5, a P+Ge doped region 7, a well region 8, a strip region 81, an L-shaped region 82, a first strip region 801, a second strip region 802, a source region 9 and first to fifth barrier layers 101 to 105.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It is noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of the present application and in the foregoing figures, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.
Referring to fig. 1, a SiC MOSFET with a low body diode turn-on voltage includes a drain metal layer 1, a substrate 2, a drift layer 3, a gate insulating layer 4, a gate 5, source metal layers 6 distributed on two sides of the gate 5, a p+ Ge doped region 7, a well region 8, and a source region 9 sequentially distributed from bottom to top, wherein the substrate 2 is a SiC substrate, the p+ Ge doped region 7, the well region 8, and the source region 9 are located at the top of the drift layer 3, the well region 8 is located at the top regions on two sides of the drift layer 3, and after the p+ Ge doped region 7 longitudinally penetrates the well region 8, the bottom contacts the drift layer 3 and divides the well region 8 into two regions: the strip-shaped region 81 and the L-shaped region 82, the source region 9 is located at the right-angle inner side of the L-shaped region 82, the outer side end of the P+ Ge doped region 7 is contacted with the inner side end of the strip-shaped region 81, the inner side end of the P+ Ge doped region 7 is contacted with the outer side end of the source region 9 and the bottom side end of the L-shaped region 82, the source metal layer 6 is located at the top ends of the source region 9 and the P+ Ge doped region 7, and the P+ Ge doped region 7 and the drift layer 3 form a heterojunction.
The thickness of the P + Ge doped region 7 is 160 times the thickness of the thinnest part of the well region 8 (i.e., the lateral region thickness), and the doping concentration of the P + Ge doped region 7 is 160 times the thickness of the well region 8. Because the breakdown field intensity of the Ge material is 160 times of that of the SiC material, the thickness of the Ge material is 160 times of that of the SiC material in order to ensure the reverse breakdown voltage of the device; since the thinnest portion of the well region is most likely to be broken down, the thickness of the p+ge doped region needs to be set to 160 times the thickness of the thinnest portion of the well region.
The L-shaped region 82 includes a vertical region with a thickness ranging from 200nm to 400nm, preferably 300nm in this embodiment, and a thickness ranging from 20nm to 50nm, preferably 30nm in this embodiment, and the thickness of the horizontal region is the thinnest thickness of the well region 8, and the thickness of the source region 9 is the difference between the thicknesses of the horizontal region and the vertical region. The thickness of the P+Ge doped region is 160 times of the thickness of the thinnest part of the well region through limiting the thickness ranges of the vertical region, the horizontal region and the source region.
The doping concentration of the well region 8 is 6X 1017cm < -3 > to 1.2X11018 cm < -3 >, and the doping concentration of the source region 9 is 1X 1018cm < -3 > to 2X 1018cm < -3 >; the drift layer 3 is an n+ SiC doped region, the p+ Ge doped region 7 and the n+ SiC doped region form a heterojunction, and the junction barrier of the heterojunction is smaller than that of the pn junction of SiC, so that the conduction voltage drop of the parasitic body diode of the SiC MOSFET of the present application is smaller than that of the conventional parasitic body diode, and the conduction voltage drop of the parasitic body diode of the SiC MOSFET of the present application (i.e., the conduction voltage drop of the heterojunction) is 0.4V.
A process for fabricating the SiC MOSFET described above, referring to fig. 8, the method comprises:
s1, providing a substrate 2;
s2, depositing a drain electrode metal layer 1 at the bottom end of the substrate 2, wherein the drain electrode metal layer is made of nickel-titanium alloy, and epitaxially growing a drift layer 3 at the top end of the substrate 2;
s3, injecting ions into the tops of two sides of the drift layer to form a well region 8, wherein the specific steps comprise:
s31, covering a first barrier layer 101 on the top end of the drift layer 3, wherein the first barrier layer 101 is made of silicon dioxide;
s32, etching exposure is carried out on the first barrier layer 101 to form a first through hole, and the top ends of two sides of the drift layer 3 are exposed by the first through hole;
s33, adopting an ion implantation process, and implanting boron (namely B) ions into the tops of the two sides of the drift layer through the first through hole to form a well region, wherein the well region 8 is made of SiC, and referring to FIG. 2;
s34, cleaning the first barrier layer 101 by adopting a wet cleaning mode;
s4, etching the position, close to the outer edge, of the middle of the well region 8 to form a second through hole penetrating through the well region 8, and dividing the well region 8 into two strip-shaped regions through the second through hole: the first stripe-shaped region 801 and the second stripe-shaped region 802 deposit p+ Ge material in the second through hole to form a p+ Ge doped region 7, which specifically includes:
s41, covering a second barrier layer 102 on the top ends of the drift layer 3 and the well region 8, wherein the second barrier layer 102 is made of silicon dioxide;
s42, sequentially etching and exposing the second barrier layer 102 and the well region 8, and forming a second through hole in the well region 8;
s43, depositing a P+Ge material in the second through hole to form a P+Ge doped region 7, referring to FIG. 3;
and S44, cleaning the second barrier layer 102 by adopting a wet cleaning mode.
S5, implanting ions into the outer side area of the top end of the second strip-shaped area 802 to form a source area, wherein the specific steps comprise:
s51, covering a third barrier layer 103 on the top end of the second strip-shaped region 802 and the top end of the P+Ge doped region, wherein the third barrier layer 103 is made of silicon dioxide;
s52, etching and exposing the third barrier layer 103 to form a third through hole, wherein the third through hole exposes the top outer side area of the second strip-shaped area 802;
s53, injecting phosphorus (namely P) ions into the top outer side area of the second strip-shaped area 802 through the third through hole to form a source area 9, wherein the source area is made of SiC, and referring to FIG. 4;
s54, the third barrier layer 103 is removed.
S6, depositing a source metal layer 6 on the top ends of the source region 9 and the P+Ge doped region 7, wherein the specific steps comprise: s61, covering the top ends of the first strip-shaped region 801, the P+Ge doped region 7 and the source region 9 with a fourth barrier layer 104, wherein the fourth barrier layer 104 is made of silicon dioxide;
s62, etching and exposing the fourth barrier layer 104 to form a fourth through hole, wherein the top ends of the P+Ge doped region 7 and the source region 9 are exposed by the fourth through hole;
s63, depositing a metal material in the fourth through hole to form a source metal layer 6, wherein the metal material of the source metal layer is nickel-copper alloy (namely Ni-Cu), and referring to FIG. 5;
and S64, cleaning the fourth barrier layer 104 by adopting a wet cleaning mode.
S7, sequentially depositing a gate insulating layer 4 and a gate 5 at the middle part of the top end of the drift layer, wherein the specific steps comprise:
s71, covering a fifth barrier layer 105 on the top end of the drift layer 3 and the outer surface of the source metal layer 6, wherein the fifth barrier layer 105 is made of silicon dioxide;
s72, etching exposure is carried out on the fifth barrier layer 105, a fifth through hole is formed, and the middle of the top end of the drift layer 3 is exposed by the fifth through hole;
s73, depositing a gate insulating layer 4 in the fifth through hole, wherein the material of the gate insulating layer is silicon dioxide, and referring to FIG. 6;
s74, a metal material is deposited on top of the gate insulating layer 4, and the metal material is aluminum, so as to form the gate 5, referring to fig. 7.
In summary, the source metal layer 6 covers the top ends of the source region 9 and the P+ Ge doped region 7 by limiting the thickness ranges of the vertical region, the horizontal region and the source region, ohmic contact is formed between the source metal layer 6 and the P+ Ge doped region 7, the P+ Ge doped region extends into the drift layer, ohmic contact is formed between the drift layer and the source metal layer, and heterojunction structure design is formed between the P+ Ge doped region and the N+ SiC doped region of the drift layer, so that forward conduction characteristic and reverse withstand voltage characteristic of the SiC MOSFET device are ensured.
Currently commonly used SiC MOSFET devices generally include two junction structures, e.g., two junction structures: the p+ Ge doped region (i.e. P-type Ge epitaxial region) and the p+ SiC doped region (i.e. p+ SiC injection region) have different conduction voltage drops (the conduction voltage drop of the two junctions is about 0.4V, the conduction voltage of the pn junction is about 1.4V, the total conduction voltage drop is about 1.8V, the power consumption of the parasitic diode is p=18v×i, wherein I is the conduction current of the parasitic diode), and a low-resistance path is easy to exist between the two junctions, so that a conduction current (for example, the current between the p+ SiC injection region, the P-type Ge epitaxial region and the P-well injection region) flowing along the low-resistance path is generated between the two heterojunctions, and the conduction current accounts for the proportion of the body diode current: the proportion value is affected by the width of the transverse structure of the device and the doping concentration of the drift layer and the well region, the internal loss of the device is increased due to the existence of the conduction current, the voltage division effect is achieved, the conduction voltage drop of the heterojunction is affected, the problem that the conduction voltage drop cannot reach a preset conduction voltage threshold value to affect the normal conduction of the flywheel diode occurs, and the normal conduction of the SiC MOSFET device is affected.
Compared with the existing two heterojunction structures, the single heterojunction structure of the SiC MOSFET device simplifies the structure of the device, reduces the size of the device, simplifies the manufacturing process flow of the whole device, has no influence on the gate characteristic of the device and does not influence the normal conduction of the gate, and the reason is that: the heterojunction freewheel channel (namely the freewheel channel formed by the source metal layer, the source region, the P+Ge doped region, the drift layer, the SiC substrate and the drain metal layer) is not overlapped or contacted with the normal conduction channel (namely the conduction channel formed by the gate metal layer, the gate insulating layer, the drift layer, the SiC substrate and the drain metal layer) of the SiC MOSFET device, so that the heterojunction has no influence on the conduction channel of the device, namely the gate characteristic of the device. In addition, the conduction voltage drop of the heterojunction formed by the P+Ge doped region 7 and the drift layer 3 is not influenced by the conduction current of other heterojunctions or other paths, so that the controllability of the conduction voltage drop is high, and the normal conduction of the device is ensured.
In the SiC MOSFET device, the heterojunction formed by the P+ Ge doped region 7 and the drift layer 3 and the improvement of parameters of each structural layer (the thickness of the P+ Ge doped region, the doping concentration of the well region, the doping concentration of the source region, the thickness range of the vertical region, the thickness range of the horizontal region and the thickness of the source region) effectively ensure that the thickness of the P+ Ge doped region is 160 times of the thickness of the thinnest part of the well region, reduce the risk of breakdown of the thinnest part of the well region, namely avoid the problem of reverse withstand voltage degradation of the SiC MOSFET possibly caused by the change of the heterojunction structure and ensure the reverse withstand voltage characteristic of the SiC MOSFET device. In addition, the improvement ensures that the conduction voltage drop of the parasitic body diode (i.e. heterojunction) in the SiC MOSFET device is maintained at about 0.4V, the conduction current I of the parasitic body diode is unchanged (i.e. the follow current capability is unchanged), and according to the power consumption calculation formula P=U×I, compared with the power consumption of the conduction voltage drop U=1.8V of the existing two junction structures under the condition that the current I is unchanged, the follow current power consumption of the parasitic diode is obviously reduced.
It is to be understood that the foregoing detailed description of the application is merely illustrative of the application and is not limited to the embodiments of the application. It will be understood by those of ordinary skill in the art that the present application may be modified or substituted for elements thereof to achieve the same technical effects; as long as the use requirement is met, the application is within the protection scope of the application.
Claims (10)
1. The SiC MOSFET comprises a drain metal layer (1), a substrate (2), a drift layer (3), a gate insulating layer (4), a gate (5) and source metal layers (6) distributed on two sides of the gate (5) from bottom to top, and is characterized by further comprising a P+ Ge doped region (7), a well region (8) and a source region (9), wherein the P+ Ge doped region (7), the well region (8) and the source region (9) are positioned in the drift layer (3), the well region (8) is positioned in top areas on two sides of the drift layer (3), the P+ Ge doped region (7) and the source region (9) are positioned in the well region (8), and the P+ Ge doped region (7) longitudinally penetrates through the well region (8) and then contacts the drift layer (3) and divides the well region (8) into two areas: the device comprises a strip-shaped region (81) and an L-shaped region (82), wherein a source region (9) is located on the right-angle inner side of the L-shaped region (82), the outer side end of a P+ Ge doped region (7) is in contact with the inner side end of the strip-shaped region (81), the inner side end of the P+ Ge doped region (7) is in contact with the outer side end of the source region (9) and the bottom side end of the L-shaped region (82), a source metal layer (6) is located on the top ends of the source region (9) and the P+ Ge doped region (7) and forms ohmic contact with the source region (9) and the P+ Ge doped region (7) respectively, and the P+ Ge doped region (7) and the drift layer (3) form a heterojunction.
2. SiC MOSFET according to claim 1, characterized in that the substrate (2) is a SiC substrate, the thickness of the p+ge doped region (7) being 160 times the thickness of the thinnest part of the well region (8), the doping concentration of the p+ge doped region (7) being 160 times the thickness of the well region (8).
3. SiC MOSFET according to claim 2, characterized in that the doping concentration of the well region (8) is 6 x 1017cm "3-1.2 x 1018 cm" 3 and the doping concentration of the source region (9) is 1 x 1018cm "3-2 x 1018 cm" 3.
4. SiC MOSFET according to claim 1, characterized in that the drift layer (3) is an n+ SiC doped region, the p+ Ge doped region (7) forming a heterojunction with the n+ SiC doped region.
5. SiC MOSFET according to claim 1, characterized in that the L-shaped region (82) comprises a vertical region with a thickness in the range 200nm to 400nm, a lateral region with a thickness in the range 20nm to 50nm, and the source region (9) has a thickness which is the difference between the lateral region and the vertical region thickness.
6. A process for fabricating a SiC MOSFET according to claim 1, comprising:
s1, providing a substrate (2);
s2, depositing a drain metal layer (1) at the bottom end of the substrate (2), and epitaxially growing a drift layer (3) at the top end of the substrate (2);
s3, injecting ions into the tops of two sides of the drift layer (3) to form a well region (8);
s4, etching the position, close to the outer edge, of the middle part of the well region (8) to form a second through hole penetrating through the well region (8), and dividing the well region (8) into two strip-shaped regions by the second through hole: a first strip-shaped region (801) and a second strip-shaped region (802), and a P+Ge doped region (7) is epitaxially grown in the second through hole;
s5, implanting ions into the outer side area of the top end of the second strip-shaped area (802) to form a source area (9);
s6, depositing a source metal layer (6) at the top ends of the source region (9) and the P+Ge doped region (7);
and S7, sequentially depositing a gate insulating layer (4) and a gate (5) at the middle part of the top end of the drift layer (3).
7. The method according to claim 6, wherein in step S3, the well region (8) is formed by using a photolithography process and an ion implantation process, the steps comprising: s31, covering a first barrier layer (101) on the top end of the drift layer (3);
s32, etching exposure is carried out on the first barrier layer (101) to form a first through hole, and the top ends of two sides of the drift layer (3) are exposed by the first through hole;
s33, implanting ions into the tops of the two sides of the drift layer (3) through the first through hole by adopting an ion implantation process to form the well region (8);
s34, removing the first barrier layer (101).
8. The method according to claim 7, wherein in step S4, the step of forming the p+ge doped region (7) by using a photolithography process and a deposition process includes:
s41, covering a second barrier layer (102) on the top ends of the drift layer (3) and the well region (8);
s42, sequentially etching and exposing the second barrier layer (102) and the well region (8), and forming a second through hole in the well region (8);
s43, depositing a P+Ge material in the second through hole to form a P+Ge doped region (7);
s44, removing the second barrier layer (102).
9. The method of claim 8, wherein in step S5, the step of forming the source region using a photolithography process and an ion implantation process comprises:
s51, covering a third barrier layer (103) on the top ends of the second strip-shaped region (802) and the P+ Ge doped region (7);
s52, etching and exposing the third barrier layer (103) to form a third through hole, wherein the third through hole exposes the top outer side area of the second strip-shaped area (802);
s53, implanting ions into the top outer side area of the second strip-shaped area (802) through the third through hole to form the source area (9);
s54, removing the third barrier layer (103).
10. The SiC MOSFET manufacturing process according to claim 9, wherein in step S6, the step of forming the source metal layer (6) using a photolithography process and a deposition process includes:
s61, covering a fourth barrier layer (104) on the top ends of the first strip-shaped region (801), the P+Ge doped region (7) and the source region (9);
s62, etching exposure is carried out on the fourth barrier layer (104) to form a fourth through hole, and the top ends of the P+Ge doped region (7) and the source region (9) are exposed through the fourth through hole;
s63, depositing a metal material in the fourth through hole to form a source metal layer (6);
s64, removing the fourth barrier layer;
in step S7, the step of forming the gate insulating layer by using a photolithography process and a deposition process includes: s71, covering a fifth barrier layer (105) on the middle part of the top end of the drift layer (3);
s72, etching exposure is carried out on the fifth barrier layer (105) to form a fifth through hole, and the middle part of the top end of the drift layer (3) is exposed by the fifth through hole;
s73, depositing and forming a gate insulating layer (4) in the fifth through hole;
and S74, depositing a metal material on the top end of the gate insulating layer (4) to form a gate (5).
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| US20050133794A1 (en) * | 2003-12-18 | 2005-06-23 | Nissan Motor Co., Ltd. | Semiconductor device |
| JP2006066770A (en) * | 2004-08-30 | 2006-03-09 | Nissan Motor Co Ltd | Semiconductor device |
| CN108258052A (en) * | 2018-01-11 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | The process of super-junction device |
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