CN218849501U - VDMOS device - Google Patents
VDMOS device Download PDFInfo
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- CN218849501U CN218849501U CN202223386109.2U CN202223386109U CN218849501U CN 218849501 U CN218849501 U CN 218849501U CN 202223386109 U CN202223386109 U CN 202223386109U CN 218849501 U CN218849501 U CN 218849501U
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Abstract
The utility model discloses a VDMOS device, include: a substrate layer; the epitaxial layer is grown on one side of the substrate layer; the P-body layer is arranged on one side of the epitaxial layer, which is far away from the substrate layer; the ohmic contact layer is arranged on one side of the P-body layer, which is far away from the epitaxial layer; the source electrode electronic layer is parallel to the ohmic contact layer and is arranged on one side of the P-body layer away from the epitaxial layer; the first metal layer covers the ohmic contact layer and the source electrode electronic layer; the channel is arranged between the first metal layer and the epitaxial layer and is close to one side, far away from the ohmic contact layer, of the source electrode electronic layer; the grid polycrystalline silicon layer is arranged on the channel; the source electrode polycrystalline silicon layer is arranged on one side, away from the first metal layer, of the grid electrode polycrystalline silicon layer in the channel; the tail end of the source electrode polycrystalline silicon layer is connected with the first metal layer through a second metal layer, and the second metal layer is Schottky barrier metal; the tail end of the grid polycrystalline silicon layer is isolated from the tail end of the source polycrystalline silicon layer through a third isolation layer. Adopt the utility model discloses, use new isolation structure, improved anti ESD ability.
Description
Technical Field
The utility model relates to a semiconductor device field especially relates to a VDMOS device.
Background
The shielded gate field effect transistor is developed on the basis of the traditional groove VDMOS, and has an upper layer polycrystal and a lower layer polycrystal, wherein the upper layer polycrystal is of a gate control gate structure and is similar to the traditional groove structure, and the lower layer polycrystal is connected with a source electrode through a wiring to play a role of shielding the gate electrode. Compared with the conventional trench VDMOS, the trench VDMOS has smaller on-resistance and lower Miller capacitance under the same voltage resistance, and has faster switching speed. Due to the complex practical application environment, the reliability requirement on the power VDMOS is higher, the power device product is very easily influenced by ESD in the production, manufacturing, assembly and working processes, the internal damage and the reliability of the product are reduced, the ESD weak point of the power VDMOS is the breakdown of a thin-layer gate oxide layer at a gate source end, and the shielding gate VDMOS has a double-gate structure, and the failure point of the shielding gate VDMOS is the breakdown of an oxide layer between an upper polycrystalline structure and a lower polycrystalline structure. Isolation of two-layer poly structures two main methods of formation are, one is to form isolation by deposition of silicon dioxide, and the other is to form dielectric isolation by thermal oxidation of polysilicon. The first silicon dioxide formed by deposition is not easy to control the thickness during etching, and the etching is easy to cause oxide layer damage, thereby reducing the breakdown voltage at two ends of a gate source; the second type of polysilicon is an oxide layer formed by thermal oxidation, and the oxide layer has poor quality and poor ESD resistance.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides a VDMOS device for at least, solve among the prior art VDMOS device anti ESD ability also relatively poor problem.
According to the utility model provides a VDMOS device, include:
the substrate layer is an N-type heavily doped layer;
the epitaxial layer grows on one side of the substrate layer, and is an N-type lightly doped layer;
the P-body layer is arranged on one side of the epitaxial layer, which is far away from the substrate layer;
the ohmic contact layer is arranged on one side of the P-body layer, which is far away from the epitaxial layer;
the source electrode electronic layer is parallel to the ohmic contact layer and is arranged on one side, away from the epitaxial layer, of the P-body layer;
the first metal layer covers the ohmic contact layer and the source electrode electronic layer and is electrically connected with the ohmic contact layer and the source electrode electronic layer;
the channel is arranged between the first metal layer and the epitaxial layer and is close to one side, far away from the ohmic contact layer, of the source electrode electronic layer;
the grid polycrystalline silicon layer is arranged in the channel and is isolated from the first metal layer, the P-body layer and the source electrode electronic layer through first isolation layers;
the source electrode polycrystalline silicon layer is arranged on one side of the grid electrode polycrystalline silicon layer, which is far away from the first metal layer, and is isolated from the epitaxial layer through a second isolation layer;
the head end of the grid polycrystalline silicon layer is flush with the head end of the source polycrystalline silicon layer, the tail end of the source polycrystalline silicon layer is connected with the first metal layer through a second metal layer, and the second metal layer is Schottky barrier metal; the tail end of the grid polycrystalline silicon layer is isolated from the tail end of the source polycrystalline silicon layer through a third isolation layer, and the depth of the third isolation layer in the direction from the first metal layer to the substrate layer is larger than that of the grid polycrystalline silicon layer.
According to some embodiments of the invention, the thickness of the first isolation layer is less than the thickness of the second isolation layer.
According to some embodiments of the invention, the first isolation layer has a thickness of 30-150nm.
According to some embodiments of the invention, the thickness of the second isolation layer is 0.1-0.8um.
According to some embodiments of the invention, the gate polysilicon layer is a P-type heavily doped layer and the source polysilicon layer is an N-type lightly doped layer.
According to some embodiments of the invention, the doping impurity of the gate polysilicon layer is boron or aluminum.
According to some embodiments of the present invention, the source polysilicon layer is doped with phosphorus or arsenic at a doping concentration of 1E15-1E17cm -3 。
According to some embodiments of the invention, the schottky barrier metal is titanium or nickel.
Adopt the technical scheme of the utility model, oxide layer between the traditional double-deck polycrystalline structure turns into neotype PN junction and keeps apart, source electrode polycrystalline silicon layer adopts the schottky barrier metal to be connected with first metal level source electrode metal simultaneously, make to form PN junction diode and schottky diode between grid and the source electrode, when reaching and reducing miller electric capacity effect, can also be when electrostatic discharge, make the diode puncture earlier, directly from the parasitic diode release energy between the grid source, thereby anti ESD ability has further been improved.
The above description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the present invention is given.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. In the drawings:
fig. 1 is a schematic structural diagram of a VDMOS device in an embodiment of the present invention;
fig. 2 is an equivalent circuit schematic diagram of a VDMOS device in an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
An embodiment of the utility model provides a VDMOS device, refer to fig. 1, include:
the substrate 1 is an N-type heavily doped layer.
And the epitaxial layer 2 is grown on one side of the substrate layer 1, and the epitaxial layer 2 is an N-type lightly doped layer.
And the P-body layer 3 is arranged on one side of the epitaxial layer 2 far away from the substrate layer 1 and is a P-type lightly doped layer.
And the ohmic contact layer 4 is arranged on one side of the P-body layer 3 far away from the epitaxial layer 2, is a P-type heavily doped layer and is used for providing ohmic contact.
And the source electrode electronic layer 5 is parallel to the ohmic contact layer 4 and is arranged on one side of the P-body layer 3 far away from the epitaxial layer 2, and the source electrode electronic layer is an N-type heavily doped layer and is used for providing source electrode electrons for the device during working.
And the first metal layer 6 covers the ohmic contact layer 4 and the source electrode electronic layer 5 and is electrically connected with the ohmic contact layer 4 and the source electrode electronic layer 5.
And the channel is arranged between the first metal layer 6 and the epitaxial layer 3, and is close to one side, far away from the ohmic contact layer 4, of the source electrode electronic layer 5. The trenches occupy part of the space of the epitaxial layer 2 that can be obtained by etching or otherwise treating the epitaxial layer 2 during production.
And the grid polycrystalline silicon layer 7 is arranged in the channel and is isolated from the first metal layer 6, the P-body layer 3 and the source electrode electronic layer 5 through a first isolation layer 9. The first isolation layer 9 is mainly used to provide electrical isolation between the gate and the source.
And the source polycrystalline silicon layer 8 is arranged on one side of the grid polycrystalline silicon layer 7 far away from the first metal layer 6 and is isolated from the epitaxial layer 2 through a second isolation layer 10.
The head end of the gate polysilicon layer 7 is flush with the head end of the source polysilicon layer 8, the tail end of the source polysilicon layer 8 is connected with the first metal layer 6 through a second metal layer 11, and the second metal layer 11 is schottky barrier metal. The tail end of the gate polysilicon layer 7 is isolated from the tail end of the source polysilicon layer 8 by a third isolation layer 12, and the depth of the third isolation layer 12 in the direction from the first metal layer 6 to the substrate layer 2 is greater than the depth of the gate polysilicon layer 7, that is, the bottommost position of the third isolation layer 12 is lower than the bottommost position of the gate polysilicon layer 7, so as to achieve the effect of electrical isolation.
On the basis of the above-described embodiment, various modified embodiments are further proposed, and it is to be noted herein that, in order to make the description brief, only the differences from the above-described embodiment are described in the various modified embodiments.
According to some embodiments of the present invention, the thickness of the first isolation layer 9 is smaller than the thickness of the second isolation layer 10.
According to some embodiments of the present invention, the thickness of the first isolation layer 9 is 30-150nm, which is mainly adjusted according to the requirement of the threshold voltage of the device.
According to some embodiments of the present invention, the thickness of the second isolation layer 10 is 0.1-0.8um, which needs a thicker thickness because it needs to bear a larger withstand voltage.
According to some embodiments of the present invention, the first isolation layer 9 and the second isolation layer 10 are gate oxide layers.
According to some embodiments of the present invention, the oxide layer of the source polysilicon layer source trace and the third isolation layer 12 is formed by means of HDP deposition.
According to some embodiments of the present invention, the gate polysilicon layer 7 is a P-type heavily doped layer, and the source polysilicon layer 8 is an N-type lightly doped layer.
According to some embodiments of the present invention, the doping impurity of the gate polysilicon layer 7 is boron or aluminum.
According to some embodiments of the present invention, the doped impurity of the source polysilicon layer is phosphorus or arsenic with a doping concentration of 1E15-1E17cm -3 And the breakdown voltage of the integrated PN junction diode and Schottky diode is regulated and controlled by controlling the doping concentration, so that the breakdown voltage is ensured to be smaller than the voltage of the first isolation layer.
According to some embodiments of the present invention, the schottky barrier metal may be one of titanium, nickel, vanadium, platinum or other suitable metal, and generally adopts a low barrier metal, so as to ensure that the connection resistance between the source polysilicon layer and the source metal layer (first metal layer) is the lowest, so as to achieve the shielding effect on the gate.
According to some embodiments of the present invention, the contact area of the schottky barrier metal and the first metal layer can be adjusted, and the larger the contact area is, the larger the ESD-resistant effect of the device is.
According to some embodiments of the present invention, the above embodiments are N-channel devices, and for a P-channel VDMOS device, it is only necessary to form corresponding N-type regions opposite to P-type regions, and no specific description is made here.
The VDMOS device of the present invention is described in detail in a specific embodiment with reference to fig. 1. It is to be understood that the following description is illustrative only and is not intended as a specific limitation on the invention. All adopt the utility model discloses a similar structure and similar change all should be listed in the protection scope of the utility model.
In this embodiment, the VDMOS device includes: the substrate 1 is an N-type heavily doped layer. And the epitaxial layer 2 is grown on one side of the substrate layer 1, and the epitaxial layer 2 is an N-type lightly doped layer. And the P-body layer 3 is arranged on one side of the epitaxial layer 2 far away from the substrate layer 1 and is a P-type lightly doped layer. And the ohmic contact layer 4 is arranged on one side of the P-body layer 3 far away from the epitaxial layer 2, is a P-type heavily doped layer and is used for providing ohmic contact. And the source electrode electronic layer 5 is parallel to the ohmic contact layer 4 and is arranged on one side of the P-body layer 3 far away from the epitaxial layer 2, and the source electrode electronic layer is an N-type heavily doped layer and is used for providing source electrode electrons for the device during working. A first metal layer 6 covering the ohmic contact layer 4 and the source electrodeAnd the electron layer 5 is electrically connected with the ohmic contact layer 4 and the source electrode electron layer 5. And the channel is arranged between the first metal layer 6 and the epitaxial layer 3, and is close to one side, far away from the ohmic contact layer 4, of the source electrode electronic layer 5. The trenches occupy part of the space of the epitaxial layer 2 that can be obtained by etching or otherwise treating the epitaxial layer 2 during production. The grid polycrystalline silicon layer 7 is of a P-type heavily doped structure and can adopt an in-situ doping process, the doped impurities are boron, the grid polycrystalline silicon layer 7 is arranged in the channel and is isolated from the first metal layer 6, the P-body layer 3 and the source electrode electronic layer 5 through a first isolation layer 9, and the thickness of the first isolation layer is 30-150nm. The first isolation layer 9 is mainly used to provide electrical isolation between the gate and the source. A source polycrystalline silicon layer 8 which adopts an N-type lightly doped structure, the doped impurity is phosphorus, the doping is carried out by adopting an ion implantation mode, and the doping concentration is 1E15-1E17cm -3 And the source polycrystalline silicon layer 8 is arranged on the grid polycrystalline silicon layer 7 and is far away from one side of the first metal layer 6, the epitaxial layer 2 is isolated through the second isolation layer 10, and the thickness of the second isolation layer is 0.1-0.8um. The head end of the gate polysilicon layer 7 is flush with the head end of the source polysilicon layer 8, the tail end of the source polysilicon layer 8 is connected with the first metal layer 6 through a second metal layer 11, the second metal layer 11 is schottky barrier metal, and the schottky barrier metal is titanium. The tail end of the gate polysilicon layer 7 is isolated from the tail end of the source polysilicon layer 8 by a third isolation layer 12, and the depth of the third isolation layer 12 in the direction from the first metal layer 6 to the substrate layer 2 is greater than the depth of the gate polysilicon layer 7, that is, the bottommost position of the third isolation layer 12 is lower than the bottommost position of the gate polysilicon layer 7, so as to achieve the electrical isolation effect.
By adopting the technical scheme of the embodiment, the grid polycrystalline diode is integrated in the groove, the oxide layer isolation of the traditional structure is converted into novel PN junction isolation, wherein the grid polycrystalline silicon layer adopts a P + type structure, the source polycrystalline silicon layer adopts an N-type structure, and meanwhile, schottky barrier contact is adopted at the connecting part of the source polycrystalline silicon layer and the first metal layer, so that direct conduction between grid sources is prevented. An equivalent circuit is shown in fig. 2, a PN junction diode D1 formed by a gate polysilicon layer and a source polysilicon layer and a schottky diode S1 formed by schottky barrier metal and a source polysilicon layer are arranged between a gate G and a source S, so that when a forward voltage is applied between GS, the schottky diode S1 is reversely cut off to achieve a gate-source electrical isolation effect, when a reverse voltage is applied between GS, the PN junction diode D1 is reversely cut off to achieve a gate-source electrical isolation effect, and the device is in a blocking state, two poles of a gate source are short-circuited, and the PN junction diode D1 and the schottky diode S1 are both in a cut-off state due to a high potential of a drain D, and since the schottky leakage is about 3 orders of magnitude larger than the PN leakage, the connection resistance between the gate polysilicon layer and the source is smaller, and a miller capacitance reduction effect is achieved.
The current rising speed is very fast when the diode structure is in reverse breakdown, so the current leakage capacity of the diode is obviously stronger than that of a dielectric oxide layer, and the breakdown of the oxide layer has the damage characteristic, and the damage positions are communicated with each other along with the accumulation of time to form a leakage channel, so that a device is damaged, the diode can be repeatedly broken, and the ESD resistance capacity of the diode is obviously stronger than that of the dielectric oxide layer. The embodiment of the utility model provides an in integrated PN junction diode D1 and schottky diode S1 'S breakdown voltage is less than gate oxide breakdown voltage, and when ESD come temporarily, diode D1 or S1 puncture earlier, and the energy is direct to be released from the parasitic diode between the bars source, can effectively improve shielding bars VDMOS' S anti ESD ability.
It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention, and those skilled in the art can make various modifications and changes. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be noted that well-known methods, structures and techniques have not been shown in detail in the description of the specification in order not to obscure the understanding of this description.
Claims (8)
1. A VDMOS device, comprising:
the substrate layer is an N-type heavily doped layer;
the epitaxial layer grows on one side of the substrate layer, and is an N-type lightly doped layer;
the P-body layer is arranged on one side of the epitaxial layer, which is far away from the substrate layer;
the ohmic contact layer is arranged on one side of the P-body layer, which is far away from the epitaxial layer;
the source electrode electronic layer is parallel to the ohmic contact layer and is arranged on one side, away from the epitaxial layer, of the P-body layer;
the first metal layer covers the ohmic contact layer and the source electrode electronic layer and is electrically connected with the ohmic contact layer and the source electrode electronic layer;
the channel is arranged between the first metal layer and the epitaxial layer and is close to one side, far away from the ohmic contact layer, of the source electrode electronic layer;
the grid polycrystalline silicon layer is arranged in the channel and is isolated from the first metal layer, the P-body layer and the source electrode electronic layer through first isolation layers;
the source polycrystalline silicon layer is arranged on one side of the grid polycrystalline silicon layer, which is far away from the first metal layer, and is isolated from the epitaxial layer through a second isolation layer;
the head end of the grid polycrystalline silicon layer is flush with the head end of the source polycrystalline silicon layer, the tail end of the source polycrystalline silicon layer is connected with the first metal layer through a second metal layer, and the second metal layer is Schottky barrier metal; the tail end of the grid polycrystalline silicon layer is isolated from the tail end of the source polycrystalline silicon layer through a third isolation layer, and the depth of the third isolation layer in the direction from the first metal layer to the substrate layer is larger than that of the grid polycrystalline silicon layer.
2. The VDMOS device of claim 1, wherein a thickness of the first isolation layer is less than a thickness of the second isolation layer.
3. The VDMOS device of claim 2, wherein the first isolation layer has a thickness of 30-150nm.
4. The VDMOS device of claim 2, wherein the second isolation layer has a thickness of 0.1-0.8um.
5. The VDMOS device of claim 1, wherein the gate polysilicon layer is a heavily P-doped layer and the source polysilicon layer is a lightly N-doped layer.
6. The VDMOS device of claim 5, wherein the doping impurity of the gate polysilicon layer is boron or aluminum.
7. The VDMOS device of claim 5, wherein the source polysilicon layer is doped with phosphorus or arsenic at a concentration of 1E15-1E17cm -3 。
8. The VDMOS device of claim 1, wherein the schottky barrier metal is titanium or nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223386109.2U CN218849501U (en) | 2022-12-16 | 2022-12-16 | VDMOS device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223386109.2U CN218849501U (en) | 2022-12-16 | 2022-12-16 | VDMOS device |
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| CN218849501U true CN218849501U (en) | 2023-04-11 |
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| CN202223386109.2U Active CN218849501U (en) | 2022-12-16 | 2022-12-16 | VDMOS device |
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