CN116594934A - Communication system, communication method, communication device and communication equipment based on SPI bus - Google Patents

Communication system, communication method, communication device and communication equipment based on SPI bus Download PDF

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Publication number
CN116594934A
CN116594934A CN202310544453.XA CN202310544453A CN116594934A CN 116594934 A CN116594934 A CN 116594934A CN 202310544453 A CN202310544453 A CN 202310544453A CN 116594934 A CN116594934 A CN 116594934A
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China
Prior art keywords
slave
interface
spi
master
equipment
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Inventor
刘青贺
方慧麒
宗成禹
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Hangzhou Changchuan Technology Co Ltd
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Hangzhou Changchuan Technology Co Ltd
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Priority to CN202310544453.XA priority Critical patent/CN116594934A/en
Publication of CN116594934A publication Critical patent/CN116594934A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application relates to a communication system, a communication method, a communication device and electronic equipment based on an SPI bus. The communication system comprises embedded chip master equipment provided with a master equipment SPI interface and a master equipment IO interface and MCU slave equipment provided with a slave equipment SPI interface and a slave equipment IO interface; the master equipment SPI interface is connected with the slave equipment SPI interface, and the master equipment IO interface is connected with the slave equipment IO interface; in the SPI communication stage of slave equipment writing and master equipment reading, the MCU slave equipment sends an interrupt request signal to the master equipment IO interface through the slave equipment IO interface according to a preset interval; the embedded chip master device sends a clock signal to the slave device SPI interface through the master device SPI interface when receiving the interrupt request signal; the MCU slave device transmits data to the master device SPI interface through the slave device SPI interface based on the clock signal. By adopting the application, the MCU slave device can actively send data, and the communication flow is simpler.

Description

Communication system, communication method, communication device and communication equipment based on SPI bus
Technical Field
The present application relates to the field of communications technologies, and in particular, to a communication system, a communication method, a communication device, and a communication device based on an SPI bus.
Background
SPI (Serial Peripheral Interface) is a serial peripheral interface for supporting master-slave mode settings when communicating between devices. When SPI bus is used for data transmission, CS pin of master device carries out chip selection to slave device, after slave device is selected, master device provides clock for device communication through SCLK pin, and outputs data through MOSI pin, and slave device receives data in communication stage of master device writing slave device reading; in the communication stage of writing the slave device into the master device for reading, the master device provides a clock for device communication through the SCLK pin, the slave device outputs data through the MISO pin, and the master device receives the data, so that the data transmission is completed. The data read-write operation of SPI bus communication is initiated by the master device, and the clock can only be provided by the master device.
Generally, an MCU (microprocessor) is configured to support a master-slave device, and other embedded chips are also configured to support a master-slave device. In the existing application scenario, the MCU or other embedded chips are mostly used as a main device to communicate with peripheral hardware, such as Flash, ADC (analog-to-digital converter), DAC (digital-to-analog converter) and other hardware devices; for communication between the MCU and other embedded chips by using SPI buses, the MCU is mostly used as a master device, and the other embedded chips are used as slave devices. Taking an embedded chip as an FPGA as an example, and taking an MCU as a master device and an FPGA as a slave device for SPI communication; but this approach is not applicable to use scenarios where all data initiators such as memory testers are FPGAs; if the MCU is adopted as the slave device and the FPGA is adopted as the master device, the FPGA is required to actively transmit data according to the existing communication mode, namely the slave device can normally communicate only after waiting for the master device to provide a clock, and the processing flow is complex.
Disclosure of Invention
Accordingly, in order to solve the above-mentioned problems, it is necessary to provide a communication system, a communication method, a device and a device based on an SPI bus, which can use an MCU as a slave device and have a simple flow.
A communication system based on an SPI bus, comprising:
the embedded chip master device comprises a master device SPI interface and a master device IO interface;
the MCU slave equipment comprises a slave equipment SPI interface and a slave equipment IO interface, wherein the master equipment SPI interface is connected with the slave equipment SPI interface so that the embedded chip master equipment and the MCU slave equipment carry out SPI communication, and the master equipment IO interface is connected with the slave equipment IO interface;
in the SPI communication stage of slave equipment writing master equipment reading, the MCU slave equipment sends an interrupt request signal to the master equipment IO interface through the slave equipment IO interface according to a preset interval;
the embedded chip master device sends a clock signal to the slave device SPI interface through the master device SPI interface when receiving the interrupt request signal; and the MCU slave equipment transmits data to the master equipment SPI interface through the slave equipment SPI interface based on the clock signal.
In one embodiment, in the above communication system based on an SPI bus, in a phase of master writing an SPI communication read by a slave, the embedded chipset master sends a clock signal and an instruction to the slave SPI through the master SPI;
the MCU slave device receives the clock signal and the command through the SPI interface of the slave device and responds.
In one embodiment, the interrupt request signal is a falling edge or a rising edge.
In one embodiment, after all data of the slave device are sent by the MCU, the slave device IO interface is restored to send a preset level signal.
In one embodiment, the number of the master device IO interfaces and the slave device IO interfaces is one.
In one embodiment, the embedded chip master device is any one of an FPGA master device, an ARM master device, and a DSP master device.
A communication method based on an SPI bus, comprising:
in the SPI communication stage of slave writing master reading, the MCU slave sends an interrupt request signal to a master IO interface of the embedded chip master according to a preset interval through the slave IO interface;
the embedded chip master device sends a clock signal to a slave device SPI interface of the MCU slave device through the master device SPI interface when receiving the interrupt request signal;
and the MCU slave equipment transmits data to the master equipment SPI interface through the slave equipment SPI interface based on the clock signal.
A communication method based on an SPI bus, for use in an MCU slave device including a slave device IO interface and a slave device SPI interface, the method comprising:
in the SPI communication stage of writing the slave device into the master device, sending an interrupt request signal to a master device IO interface of the embedded chip master device through the slave device IO interface according to a preset interval;
and when receiving a clock signal sent by the embedded chip master device according to the interrupt request signal, sending data to the embedded chip master device through the SPI interface of the slave device based on the clock signal.
In one embodiment, the communication method based on the SPI bus further includes:
and in the SPI communication stage of the master device writing slave device reading, receiving a clock signal and an instruction sent by the embedded chip master device through the slave device SPI interface and responding.
A communication method based on SPI bus is used in embedded chip master equipment comprising a master equipment IO interface and a master equipment SPI interface, and the method comprises the following steps:
in the SPI communication stage of writing the master device into the slave device, when the master device IO interface receives an interrupt request signal sent by the MCU slave device, a clock signal is sent to the MCU slave device through the master device SPI interface;
and receiving data sent by the MCU slave device based on the clock signal through the SPI interface of the master device.
In one embodiment, the SPI bus-based method further comprises:
and in the SPI communication stage of writing the slave device by the master device, sending a clock signal and an instruction to the MCU slave device through the SPI interface of the master device.
A communication device based on an SPI bus, for use in an MCU slave device including a slave device IO interface and a slave device SPI interface, the device comprising:
the interrupt sending module is used for sending an interrupt request signal to the main equipment IO interface of the embedded chip main equipment according to a preset interval through the auxiliary equipment IO interface in the SPI communication stage of writing the main equipment into and reading the main equipment;
and the data transmitting module is used for transmitting data to the embedded chip master device through the SPI interface of the slave device based on the clock signal when receiving the clock signal transmitted by the embedded chip master device according to the interrupt request signal.
A communication device based on an SPI bus, for use in an embedded chip master device including a master device IO interface and a master device SPI interface, the device comprising:
the interrupt receiving module is used for sending a clock signal to the MCU slave device through the SPI interface of the master device when the IO interface of the master device receives an interrupt request signal sent by the MCU slave device in the SPI communication stage of writing the master device into the slave device for reading;
and the data receiving module is used for receiving data sent by the MCU slave equipment based on the clock signal through the SPI interface of the master equipment.
An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor when executing the computer program performs the steps of:
in the SPI communication stage of writing the slave device into the master device, sending an interrupt request signal to a master device IO interface of the embedded chip master device through the slave device IO interface according to a preset interval;
when receiving a clock signal sent by the embedded chip master device according to the interrupt request signal, sending data to the embedded chip master device through the SPI interface of the slave device based on the clock signal;
or the processor, when executing the computer program, performs the steps of:
in the SPI communication stage of writing the master device into the slave device, when the master device IO interface receives an interrupt request signal sent by the MCU slave device, a clock signal is sent to the MCU slave device through the master device SPI interface;
and receiving data sent by the MCU slave device based on the clock signal through the SPI interface of the master device.
According to the communication system, the communication method, the communication device and the electronic equipment based on the SPI bus, in the SPI communication stage that the slave writes the master and reads, the interrupt request signal is sent to the embedded chip master at intervals through the MCU slave, so that the embedded chip master sends a clock signal to the MCU slave, and the MCU slave sends data to the embedded chip master based on the clock signal. Therefore, the SPI communication mode with the MCU as the slave device and the embedded chip as the master device is realized, and the function of actively transmitting data from the MCU slave device to the embedded chip master device is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a communication system based on an SPI bus in one embodiment;
FIG. 2 is a schematic diagram of a communication system based on an SPI bus in another embodiment;
FIG. 3 is a timing diagram of the SPI communication phase of a master writing slave reading in one embodiment;
FIG. 4 is a timing diagram of the SPI communication phase of a slave writing master reading in one embodiment;
FIG. 5 is a flow chart of a communication method based on an SPI bus in one embodiment;
FIG. 6 is a flow chart of an SPI bus-based communication method for MCU slaves in one embodiment;
FIG. 7 is a flow chart of an SPI bus-based communication method for an embedded chip master device in one embodiment;
FIG. 8 is a block diagram of a communication device based on an SPI bus for an MCU slave device in one embodiment;
FIG. 9 is a block diagram of an SPI bus-based communication device for an embedded chip master, in one embodiment.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
Referring to fig. 1, in one embodiment, a communication system based on an SPI bus is provided, comprising an embedded chip master device 10 and an MCU slave device 20. The embedded chip master 10 is a master using an embedded chip, and the MCU slave 20 is a slave using an MCU. In this embodiment, the embedded chip refers to other types of embedded chips except for the MCU, and the embedded chip master device 10 is a master device other than the MCU.
The embedded chip master device 10 comprises a master device SPI interface 101 and a master device IO interface 102; the MCU slave 20 includes a slave SPI interface 201 and a slave IO interface 202. The master SPI interface 101 is connected to the slave SPI interface 201, so that the embedded chip master 10 communicates with the MCU slave 20 through SPI, and the master IO interface 102 is connected to the slave IO interface 202.
Specifically, the master device and the slave device perform SPI communication in a master-slave mode, and the SPI communication comprises a SPI communication stage of writing the slave device into and reading the slave device from the master device and a SPI communication stage of writing the slave device into and reading the master device from the slave device. The SPI communication stage of the slave device writing the slave device reading refers to a stage of the slave device sending an instruction to the slave device, and the SPI communication stage of the slave device writing the master device reading refers to a stage of the slave device returning data to the master device.
In this embodiment, in the SPI communication stage of the slave writing to the master reading, the MCU slave 20 sends an interrupt request signal to the master IO interface 102 through the slave IO interface 202 at a preset interval, so that the embedded chip master 10 receives the interrupt request signal through the master IO interface 102. The embedded chip master 10 transmits a clock signal to the slave SPI interface 201 through the master SPI interface 101 upon receiving the interrupt request signal, so that the MCU slave 20 receives the clock signal through the slave SPI interface 201. The MCU slave 20 transmits data to the master SPI interface 101 through the slave SPI interface 201 based on a clock signal, so that the embedded chip master 10 receives data uploaded by the MCU slave 20 through the master SPI interface 101. That is, the MCU slave 20 transmits an interrupt request signal to the embedded chip master 10 at intervals, causing the embedded chip master 10 to provide a clock signal, and the MCU slave 20 transmits data to the embedded chip master 10 based on the clock signal. Specifically, after the MCU slave 20 transmits an interrupt request signal once, data of a preset byte is transmitted based on a clock signal provided by the embedded chip master 10, after the data transmission of the preset byte is completed, the next interrupt request signal is transmitted, after the embedded chip master 10 provides the clock signal, the MCU slave 20 transmits data of the next preset byte again, and the cycle is performed until all data transmission is completed, and the transmission of the interrupt request signal is stopped.
Wherein the master IO interface 102 and the slave IO interface 202 may be IO pins. Master SPI interface 101 and slave SPI interface 201 each include a MOSI (master output slave input) pin, a MISO (master input slave output) pin, a CS (chip select) pin, and a SCLK (clock) pin. The CS pin is used for performing chip selection on the MCU slave device 20, after selecting one MCU slave device 20, in the SPI communication stage of the slave device writing master device reading, after the MCU slave device 20 sends an interrupt request signal through the slave device IO interface 202, the embedded chip master device 10 sends a clock signal to the SCLK pin of the MCU slave device 20 through the SCLK pin, and the MCU slave device 20 sends data to the MISO pin of the embedded chip master device 10 through the MISO pin based on the clock signal.
Specifically, the preset interval is longer than the time required for the MCU slave device 20 to transmit the data of the preset byte, that is, the interval time for transmitting the interrupt request signal is longer than the time required for each transmission of the data, so that it is ensured that the MCU slave device 20 transmits the interrupt request signal after the completion of the transmission of the data of the preset byte. For example, the MCU slave device 20 may transmit two bytes of data at a time, and the preset interval is greater than the time required to transmit two bytes of data.
In the above communication system based on the SPI bus, the embedded chip master device 10 and the MCU slave device 20 are both provided with an SPI interface and an IO interface, and in the SPI communication stage in which the slave device writes the master device and reads, the MCU slave device 20 sends an interrupt request signal to the master device IO interface 102 at intervals through the slave device IO interface 202; the embedded chip master 10 transmits a clock signal to the slave SPI interface 201 through the master SPI interface 101, and the final MCU slave 20 transmits data to the embedded chip master 10 through the slave SPI interface 201 based on the clock signal. In this way, the MCU slave 20 actively transmits the interrupt request signal at intervals to inform the embedded chip master 10 of providing the clock signal, so that the MCU slave 20 can transmit data to the embedded chip master 10 at intervals, an SPI communication manner using the MCU slave and the embedded chip as the master is implemented, and a function of actively transmitting data from the MCU slave 20 to the embedded chip master 10 is implemented.
In one embodiment, the embedded chip master is any one of an FPGA master, an ARM master, and a DSP master.
Taking the embedded chip master device as an example, the FPGA master device is adopted, the MCU slave device 20 can actively send data to the FPGA master device, and the SPI communication problem of taking the FPGA as the master device and the MCU as the slave device can be solved. The FPGA is used as a main device, and the method is suitable for a use scene that all data originators of a memory tester are the FPGA.
In one embodiment, in the above communication system based on the SPI bus, in the SPI communication stage of the master writing the slave reading, the embedded chipset master 10 sends a clock signal and an instruction to the slave SPI interface 201 through the master SPI interface 101; the MCU slave 20 receives clock signals and commands and responds through the slave SPI interface 201.
For example, master SPI interface 101 and slave SPI interface 201 each include a MOSI pin, a MISO pin, a CS pin, and an SCLK pin. After the embedded chip master device 10 selects one MCU slave device 20 through the CS pin, in the SPI communication stage of the master device writing slave device reading, the embedded chip master device 10 sends a clock signal to the SCLK pin of the MCU slave device 20 through the SCLK pin, and synchronously sends an instruction to the MOSI pin of the MCU slave device 20 through the MOSI pin. Specifically, in the SPI communication stage of the master writing slave reading, the MISO pin of the MCU slave 20 does not perform any operation, and returns to 0 by default; after the embedded chip master device 10 sends all data, the MCU slave device 20 performs corresponding action processing, such as peripheral control, power on control and other operations; when the operation of the MCU slave device 20 is completed and the data preparation is completed, the SPI communication stage of the slave device writing master device reading can be entered, and an interrupt request signal is sent through the slave device IO interface 202. Further, the MCU slave device 20 may receive the command through the SPI interrupt.
In one embodiment, the interrupt request signal is a falling edge or a rising edge. IO interruption is realized by adopting a falling edge or rising edge mode. In this embodiment, the interrupt triggering mode is edge triggering. Taking the falling edge as an example, the MCU slave 20 sends a falling edge to the master IO interface 102 through the slave IO interface 202, triggers the embedded chip master 10 to interrupt through the falling edge, and the embedded chip master 10 responds to the interrupt and sends a clock signal through the master SPI interface 101. It will be appreciated that in other embodiments, the interrupt request signal may be in other forms, such as a level signal, and correspondingly, the interrupt trigger mode is level trigger.
In one embodiment, after all data of the slave device 20 is transmitted, the slave device IO interface 202 is restored to transmit the preset level signal. In this embodiment, the slave IO interface 202 transmits a preset level signal, such as a high level signal, by default, and the slave IO interface resumes the preset level signal without transmitting an interrupt request signal, so that the false triggering of the interrupt can be reduced. Further, the embedded chip master 10 may transmit any data to the MCU slave 20 when the slave IO interface 202 is restored to a preset level signal such as a high level.
In one embodiment, the number of master IO interfaces 102 and slave IO interfaces 202 is one. That is, the embedded chip master device 10 is provided with a master device IO interface 102, the mcu slave device 20 is provided with a slave device IO interface 202, and the master device IO interface 102 and the slave device IO interface 202 are connected through a pin connection line. Therefore, the data can be actively sent out from the equipment by using one IO interface in SPI communication, a plurality of IO pins are not needed for the mutual notification data receiving and sending of the master equipment and the slave equipment, and the occupation of pin resources and IO connection leads are saved.
In a detailed embodiment, as shown in fig. 2, the FPGA acts as a master device, the MCU acts as a slave device, and data interaction is performed through an SPI interface and an IO interface, where the SPI interface includes a MOSI pin, a MISO pin, a CS pin, and an SCLK pin. In the SPI communication stage of the master device writing slave device reading, a timing diagram is shown in fig. 3, the FPGA master device sends a clock signal through an SCLK pin, synchronously sends data to the MCU slave device through an MOSI pin, and sends data at intervals in a mode of sending two bytes each time; the MCU slave device receives data through SPI interrupt, but the MISO pin of the MCU slave device does not do any operation, and returns to 0 by default; after the FPGA main equipment transmits data, the MCU slave equipment performs corresponding action processing. In the SPI communication stage of the slave device writing master device reading, a timing diagram is shown in fig. 4, when the MCU slave device finishes operation and data preparation is finished, the FPGA master device is informed of the falling edge through the IO interface, the FPGA master device sends a clock signal to the MCU slave device to provide a clock source, the MCU slave device sends data to the FPGA master device through the MISO pin, and the MCU slave device sends data according to the mode of sending two bytes of data each time.
In one embodiment, a communication method based on an SPI bus is provided, which is suitable for the SPI communication between an embedded chip master device and an MCU slave device in the above communication system based on an SPI bus, as shown in fig. 5, and the method includes the following steps:
s510: in the SPI communication stage of slave device writing master device reading, MCU slave device sends interrupt request signal to master device IO interface of embedded chip master device according to preset interval through slave device IO interface.
S530: and the embedded chip master device sends a clock signal to the slave device SPI interface of the MCU slave device through the master device SPI interface when receiving the interrupt request signal.
S550: the MCU slave device transmits data to the master device SPI interface through the slave device SPI interface based on the clock signal.
According to the communication method based on the SPI bus, in the SPI communication stage of writing the slave device into the master device, the interrupt request signal is sent to the embedded chip master device at intervals through the MCU slave device, so that the embedded chip master device sends the clock signal to the MCU slave device, and the MCU slave device sends data to the embedded chip master device based on the clock signal. Therefore, the SPI communication mode with the MCU as the slave device and the embedded chip as the master device is realized, and the function of actively transmitting data from the MCU slave device to the embedded chip master device is realized.
In one embodiment, after step S550, the method further includes: and after all data of the slave equipment are transmitted by the MCU, recovering the IO interface of the slave equipment to transmit a preset level signal.
In one embodiment, the communication method based on the SPI bus further includes: in the SPI communication stage of writing the slave device to read by the master device, the embedded chip master device sends a clock signal and an instruction to the slave device SPI through the master device SPI; the MCU slave receives the clock signal and the command through the slave SPI interface and responds.
In one embodiment, a communication method based on an SPI bus is provided, and the communication method is used in MCU slave equipment comprising a slave equipment IO interface and a slave equipment SPI interface, and the MCU slave equipment communicates with an embedded chip master equipment comprising a master equipment IO interface and a master equipment SPI interface. As shown in fig. 6, the method includes:
s610: in the SPI communication stage of slave writing master reading, an interrupt request signal is sent to a master IO interface of the embedded chip master through the slave IO interface according to a preset interval.
Specifically, when the embedded chip master device detects that the master device IO interface receives an interrupt request signal, the embedded chip master device sends a clock signal through the master device SPI interface.
S630: and when receiving a clock signal sent by the embedded chip master device according to the interrupt request signal, sending data to the embedded chip master device through the SPI interface of the slave device based on the clock signal.
According to the communication method based on the SPI bus applied to the MCU slave device, in the SPI communication stage of writing the master device into the slave device, the interrupt request signal is sent to the embedded chip master device at intervals through the MCU slave device, so that the embedded chip master device sends a clock signal to the MCU slave device, and the MCU slave device sends data to the embedded chip master device based on the clock signal. Therefore, the SPI communication mode with the MCU as the slave device and the embedded chip as the master device is realized, and the function of actively transmitting data from the MCU slave device to the embedded chip master device is realized.
In one embodiment, after step S630, the method further includes: and after all the data are transmitted, recovering the IO interface of the slave device to transmit a preset level signal.
In one embodiment, the communication method based on the SPI bus applied to the MCU slave device further includes: and in the SPI communication stage of the master device writing slave device reading, receiving a clock signal and an instruction sent by the embedded chip master device through the SPI interface of the slave device and responding.
In one embodiment, a communication method based on an SPI bus is provided, and the communication method is used in an embedded chip master device comprising a master device IO interface and a master device SPI interface, and the embedded chip master device is communicated with an MCU slave device comprising a slave device SPI interface and a slave device IO interface. As shown in fig. 7, the method includes:
s710: in the SPI communication stage of writing the slave device into the master device for reading, when the master device IO interface receives an interrupt request signal sent by the MCU slave device, a clock signal is sent to the MCU slave device through the master device SPI interface.
In the SPI communication stage of slave device writing master device reading, the MCU slave device sends an interrupt request signal to a master device IO interface of the embedded chip master device according to a preset interval through the slave device IO interface, so that the embedded chip master device can receive the interrupt request signal through the master device IO interface.
S730: and receiving data sent by the MCU slave device based on the clock signal through the SPI interface of the master device.
The MCU slave device receives the clock signal and sends data to the master device SPI interface through the slave device SPI interface, so that the embedded chip master device can receive the data actively sent by the MCU slave device.
According to the SPI bus-based communication method applied to the embedded chip master device, in the SPI communication stage of writing the slave device into the master device and reading the slave device, the embedded chip master device receives the interrupt request signal sent by the MCU slave device, responds to the interrupt request signal to send a clock signal to the MCU slave device, and then receives data sent by the MCU slave device based on the clock signal. Therefore, the SPI communication mode using the MCU as the slave device is realized, the function of actively transmitting data from the MCU to the embedded chip master device is realized, and compared with the complex process that the slave device can only passively wait for the master device to actively provide a clock source in the prior art, the communication process is simpler.
In one embodiment, the communication method based on the SPI bus applied to the embedded chip master device further includes: and in the SPI communication stage of the master equipment writing slave equipment reading, a clock signal and an instruction are sent to the MCU slave equipment through the SPI interface of the master equipment.
It should be understood that, although the steps in the flowcharts of fig. 5-7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of fig. 5-7 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in other steps.
In one embodiment, as shown in fig. 8, a communication device based on an SPI bus is provided, and is used in an MCU slave device including a slave device IO interface and a slave device SPI interface, where the MCU slave device communicates with an embedded chip master device including a master device SPI interface and a master device IO interface. As shown in fig. 8, the apparatus includes an interrupt transmission module 810 and a data transmission module 830. Wherein:
the interrupt sending module 810 is configured to send, during an SPI communication phase of the slave writing to the master, an interrupt request signal to a master IO interface of the embedded chip master at a preset interval through the slave IO interface.
The data sending module 830 is configured to send data to the embedded chip master device through the slave SPI interface based on the clock signal when receiving the clock signal sent by the embedded chip master device according to the interrupt request signal.
The communication device based on the SPI bus applied to the MCU slave device uses the interrupt sending module 810 to send an interrupt request signal to the embedded chip master device at intervals in the SPI communication stage of the slave device writing master device reading, so that the embedded chip master device sends a clock signal to the MCU slave device, and uses the data sending module 830 to send data to the embedded chip master device based on the clock signal. Therefore, the SPI communication mode with the MCU as the slave device and the embedded chip as the master device is realized, and the function of actively transmitting data from the MCU slave device to the embedded chip master device is realized.
In one embodiment, the communication device based on the SPI bus applied to the MCU slave device further includes a level restoration module, configured to restore the slave device IO interface to transmit a preset level signal after the data transmission module 830 finishes transmitting all data.
In one embodiment, the communication device based on the SPI bus applied to the MCU slave device further includes an instruction receiving module, configured to receive, through the slave device SPI interface, a clock signal and an instruction sent by the embedded chip master device and respond in an SPI communication stage in which the master device writes the slave device to read.
In one embodiment, a communication device based on an SPI bus is provided, for use in an embedded chip master device including a master IO interface and a master SPI interface, the embedded chip master device communicating with an MCU slave device including a slave SPI interface and a slave IO interface. As shown in fig. 9, the apparatus includes an interrupt receiving module 910 and a data receiving module 930, wherein:
the interrupt receiving module 910 is configured to send, in an SPI communication stage in which the slave writes to the master, a clock signal to the MCU slave through the master SPI interface when the master IO interface receives an interrupt request signal sent by the MCU slave.
The data receiving module 930 is configured to receive, through the master SPI interface, data sent by the MCU slave based on the clock signal.
The communication device based on the SPI bus, which is applied to the embedded chip master device, uses the interrupt receiving module 910 to receive the interrupt request signal sent by the MCU slave device in the SPI communication stage of the slave device writing the master device reading, and responds to the interrupt request signal to send the clock signal to the MCU slave device, and uses the data receiving module 930 to receive the data sent by the MCU slave device based on the clock signal. Therefore, the SPI communication mode using the MCU as the slave device is realized, the function of actively transmitting data from the MCU to the embedded chip master device is realized, and compared with the complex process that the slave device can only passively wait for the master device to actively provide a clock source in the prior art, the communication process is simpler.
In one embodiment, the communication device based on the SPI bus applied to the embedded chip master device further includes an instruction sending module, configured to send, during an SPI communication phase in which the master device writes the slave device to read, a clock signal and an instruction to the MCU slave device through the master device SPI interface.
For specific limitations of the SPI bus-based communication device, reference may be made to the corresponding limitations of the SPI bus-based communication method described above, and no further description is given here. The modules in the communication device based on the SPI bus can be all or partially realized by software, hardware and a combination thereof. The above modules may be embedded in hardware or independent of a processor in the electronic device, or may be stored in software in a memory in the electronic device, so that the processor may call and execute operations corresponding to the above modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.
In one embodiment, an electronic device is provided, including a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the steps of the SPI bus-based communication method for the MCU slave device in the above embodiments, or implement the steps of the SPI bus-based communication method for the embedded chip master device in the above embodiments.
Wherein the electronic device includes, but is not limited to, a chip tester. For example, in one embodiment, the electronic device may be a memory tester. In other embodiments, the electronic device may also be other types of testers.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (14)

1. A communication system based on an SPI bus, comprising:
the embedded chip master device comprises a master device SPI interface and a master device IO interface;
the MCU slave equipment comprises a slave equipment SPI interface and a slave equipment IO interface, wherein the master equipment SPI interface is connected with the slave equipment SPI interface so that the embedded chip master equipment and the MCU slave equipment carry out SPI communication, and the master equipment IO interface is connected with the slave equipment IO interface;
in the SPI communication stage of slave equipment writing master equipment reading, the MCU slave equipment sends an interrupt request signal to the master equipment IO interface through the slave equipment IO interface according to a preset interval;
the embedded chip master device sends a clock signal to the slave device SPI interface through the master device SPI interface when receiving the interrupt request signal; and the MCU slave equipment transmits data to the master equipment SPI interface through the slave equipment SPI interface based on the clock signal.
2. A communication system based on an SPI bus as defined in claim 1,
in the SPI communication stage of writing slave equipment to read by the master equipment, the embedded chip master equipment sends a clock signal and an instruction to the slave equipment SPI interface through the master equipment SPI interface;
the MCU slave device receives the clock signal and the command through the SPI interface of the slave device and responds.
3. The SPI bus-based communication system of claim 1 wherein the interrupt request signal is either a falling edge or a rising edge.
4. The SPI bus-based communication system of claim 1 wherein said MCU resumes said slave IO interface to transmit a preset level signal after all data of said slave has been transmitted.
5. The SPI bus-based communication system according to any of claims 1-4, wherein the number of master IO interfaces and slave IO interfaces is one.
6. The SPI bus-based communication system according to any of claims 1-4, wherein the embedded chip master is any one of an FPGA master, an ARM master, and a DSP master.
7. A communication method based on an SPI bus, comprising:
in the SPI communication stage of slave writing master reading, the MCU slave sends an interrupt request signal to a master IO interface of the embedded chip master according to a preset interval through the slave IO interface;
the embedded chip master device sends a clock signal to a slave device SPI interface of the MCU slave device through the master device SPI interface when receiving the interrupt request signal;
and the MCU slave equipment transmits data to the master equipment SPI interface through the slave equipment SPI interface based on the clock signal.
8. A communication method based on SPI bus is characterized in that,
the method is used for the MCU slave equipment comprising a slave equipment IO interface and a slave equipment SPI interface, and comprises the following steps:
in the SPI communication stage of writing the slave device into the master device, sending an interrupt request signal to a master device IO interface of the embedded chip master device through the slave device IO interface according to a preset interval;
and when receiving a clock signal sent by the embedded chip master device according to the interrupt request signal, sending data to the embedded chip master device through the SPI interface of the slave device based on the clock signal.
9. The method as recited in claim 8, further comprising:
and in the SPI communication stage of the master device writing slave device reading, receiving a clock signal and an instruction sent by the embedded chip master device through the slave device SPI interface and responding.
10. A communication method based on SPI bus is characterized in that,
the method is used in the embedded chip master device comprising a master device IO interface and a master device SPI interface, and comprises the following steps:
in the SPI communication stage of writing the master device into the slave device, when the master device IO interface receives an interrupt request signal sent by the MCU slave device, a clock signal is sent to the MCU slave device through the master device SPI interface;
and receiving data sent by the MCU slave device based on the clock signal through the SPI interface of the master device.
11. The method as recited in claim 10, further comprising:
and in the SPI communication stage of writing the slave device by the master device, sending a clock signal and an instruction to the MCU slave device through the SPI interface of the master device.
12. A communication device based on SPI bus is characterized in that,
the device is used for MCU slave equipment comprising a slave equipment IO interface and a slave equipment SPI interface, and comprises:
the interrupt sending module is used for sending an interrupt request signal to the main equipment IO interface of the embedded chip main equipment according to a preset interval through the auxiliary equipment IO interface in the SPI communication stage of writing the main equipment into and reading the main equipment;
and the data transmitting module is used for transmitting data to the embedded chip master device through the SPI interface of the slave device based on the clock signal when receiving the clock signal transmitted by the embedded chip master device according to the interrupt request signal.
13. A communication device based on SPI bus is characterized in that,
the device is used in an embedded chip master device comprising a master device IO interface and a master device SPI interface, and comprises:
the interrupt receiving module is used for sending a clock signal to the MCU slave device through the SPI interface of the master device when the IO interface of the master device receives an interrupt request signal sent by the MCU slave device in the SPI communication stage of writing the master device into the slave device for reading;
and the data receiving module is used for receiving data sent by the MCU slave equipment based on the clock signal through the SPI interface of the master equipment.
14. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 8 to 9 when executing the computer program or the processor implements the steps of the method of any of claims 10 to 11 when executing the computer program.
CN202310544453.XA 2023-05-12 2023-05-12 Communication system, communication method, communication device and communication equipment based on SPI bus Pending CN116594934A (en)

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CN202310544453.XA CN116594934A (en) 2023-05-12 2023-05-12 Communication system, communication method, communication device and communication equipment based on SPI bus

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