CN116581154B - SGT device and process method thereof - Google Patents
SGT device and process method thereof Download PDFInfo
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- CN116581154B CN116581154B CN202310849595.7A CN202310849595A CN116581154B CN 116581154 B CN116581154 B CN 116581154B CN 202310849595 A CN202310849595 A CN 202310849595A CN 116581154 B CN116581154 B CN 116581154B
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 113
- 229920005591 polysilicon Polymers 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000005530 etching Methods 0.000 claims abstract description 44
- 238000005516 engineering process Methods 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims abstract description 33
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 33
- 230000015556 catabolic process Effects 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 238000011049 filling Methods 0.000 claims abstract description 17
- 238000001039 wet etching Methods 0.000 claims abstract description 17
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000000227 grinding Methods 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 16
- 229910052796 boron Inorganic materials 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 230000005684 electric field Effects 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides a process method of an SGT device and the SGT device, the process method comprises the steps of providing an N-type epitaxial substrate, etching a first groove on the N-type epitaxial substrate, growing a first oxide layer on the inner wall of the first groove in a thermal oxidation mode, filling N-type doped polysilicon, grinding and etching back to form a shielding gate in the first groove by adopting a CMP technology, etching the first oxide layer on the inner wall of the first groove to a preset depth by adopting a wet etching technology, growing a second oxide layer with a preset thickness on the inner wall of the second groove by adopting a thermal oxidation mode, sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, grinding and flattening by adopting a CMP technology, and finally carrying out high-temperature annealing after well doping to obtain the SGT device with high breakdown voltage.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a process method of an SGT device and the SGT device.
Background
MOSFETs can be broadly divided into the following categories: a planar MOSFET; trench MOSFET is mainly used in low voltage field; SGT (Shielded Gate Transistor, shielded gate trench) MOSFETs, mainly for medium and low voltage applications; SJ- (superjunction) MOSFETs are mainly used in high voltage applications.
The SGT MOSFET structure has a charge coupling effect, horizontal depletion is introduced on the basis of vertical depletion of PN junctions of the traditional trench MOSFET device, and the device can obtain higher breakdown voltage under the condition of adopting epitaxial materials with the same doping concentration. Deeper trench depths may take advantage of more silicon volume to absorb EAS (Energy Avalanche Stress, avalanche energy test) energy so the SGT may perform better in avalanche and be more tolerant of avalanche breakdown and surge currents. In the application fields of switching power supplies, motor control, power battery systems and the like, the SGT MOSFET is matched with advanced packaging, so that the efficiency and the power density of the system are improved.
In the conventional process, after a trench is dug on an epitaxial substrate, a sidewall oxide layer is formed by thermal oxidation, then polysilicon is filled into the trench, the polysilicon is etched downwards to form a shielding gate, then the oxide layer on the sidewall is removed by wet etching, gate oxide is generated by oxidation, and then polysilicon is refilled to form a gate, wherein the peak of the electric field intensity of the SGT obtained by the process is at the PN junction formed by a well region and an EPI (silicon grown by an epitaxial technology) and the bottom of the trench.
The breakdown voltage of the SGT can be characterized by the integral area of the electric field intensity curve along the direction of the groove, and the larger the integral area, the higher the breakdown voltage. Although the conventional SGT introduces horizontal depletion, the peak of the electric field intensity is in an M shape at the PN junction formed by the well region and the EPI and the bottom of the trench, and the middle part of the electric field intensity is provided with a recess, so that the voltage-withstanding capability is limited.
Disclosure of Invention
Based on the above, the invention aims to provide a process method of an SGT device and the SGT device, and aims to solve the problems that in the prior art, the peak of electric field intensity is at the bottom of a PN junction and a groove formed by a well region and an EPI, the electric field intensity distribution is M-shaped, and the middle part is provided with a recess, so that the pressure resistance is limited.
According to one embodiment of the invention, a process for forming an SGT device includes:
providing an N-type epitaxial substrate, and etching the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove;
growing a first oxide layer on the inner wall of the first groove in a thermal oxidation mode;
filling N-type doped polysilicon in a first groove with the first oxide layer, and grinding and etching back after adopting a CMP technology to form a shielding gate in the first groove;
etching the first oxide layer on the inner wall of the first groove to a preset depth by adopting a wet etching technology so as to form a second groove for filling the P-type doped polysilicon subsequently;
growing a second oxide layer with a preset thickness on the inner wall of the second groove in a thermal oxidation mode;
sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and grinding by adopting a CMP technology;
after well doping, a high temperature anneal is performed to obtain SGT devices with high breakdown voltages.
Further, the depth of the first groove is 5.5-6.5 μm.
Further, in the step of growing the first oxide layer on the inner wall of the first groove in a thermal oxidation mode, oxygen is introduced at the temperature of 800-1100 ℃ to grow the first oxide layer with the thickness of 5600-6500A.
Further, in the step of filling the first trench with the first oxide layer with the N-type doped polysilicon, and polishing and etching back by adopting a CMP technology to form a shielding gate in the first trench, the distance between the surface of the shielding gate and the surface of the N-type epitaxial substrate is 1.3 μm-1.7 μm.
Further, in the step of etching the first oxide layer on the inner wall of the first trench to a preset depth by using a wet etching technology, the preset depth is 2.5 μm to 3.5 μm.
Further, in the step of growing the second oxide layer with the preset thickness on the inner wall of the second groove by means of thermal oxidation, the thickness of the second oxide layer is 400-600 a.
Further, in the step of sequentially depositing the P-type doped polysilicon and the N-type doped polysilicon in the second trench and flattening the polysilicon by adopting a CMP technique, the P-type doped polysilicon is boron doped polysilicon, wherein the doping concentration of boron is 10 17 atoms/cm 3 ~10 21 atoms/cm 3 。
Further, the P-type doped polysilicon and the N-type doped polysilicon are sequentially deposited in the second trench, and in the step of flattening by adopting the CMP technology, the thickness of the deposited N-type doped polysilicon is 1.2 μm to 1.4 μm.
Further, in the step of performing high-temperature annealing after the well doping to obtain the SGT device with high breakdown voltage, the annealing temperature is 800-1000 ℃.
According to the SGT device, the SGT device is manufactured through the technical method of the SGT device.
Compared with the prior art: the invention provides a process method of an SGT device and the SGT device, the process method comprises the steps of providing an N-type epitaxial substrate, etching a first groove on the N-type epitaxial substrate, growing a first oxide layer on the inner wall of the first groove in a thermal oxidation mode, filling N-type doped polycrystalline silicon, polishing and etching back to form a shielding gate in the first groove by adopting a CMP technology, etching the first oxide layer on the inner wall of the first groove to a preset depth by adopting a wet etching technology, growing a second oxide layer with a preset thickness on the inner wall of the second groove by adopting a thermal oxidation mode, sequentially depositing P-type doped polycrystalline silicon and N-type doped polycrystalline silicon in the second groove, polishing by adopting a CMP technology, finally carrying out high-temperature annealing after well doping to obtain the SGT device with high breakdown voltage, specifically, increasing the integral voltage of the electric field in the two positions of a PN junction formed by the second groove and the N-type epitaxial substrate and increasing the peak strength of the electric field in the middle position of the groove, and increasing the integral voltage of the electric field, so as to achieve the integral voltage of the electric field.
Drawings
FIG. 1 is a flow chart illustrating a process for forming an SGT device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a process for fabricating an SGT device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of SGT electric field intensity distribution curves.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 and 2, fig. 1 is a flowchart illustrating a process method of an SGT device according to an embodiment of the present invention, and fig. 2 is a schematic diagram illustrating a preparation process of an SGT device according to an embodiment of the present invention, where the process method specifically includes the following steps:
s100: providing an N-type epitaxial substrate, and etching the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove;
specifically, the N-type epitaxial substrate 1 may be a silicon substrate, and first a first trench is etched on the N-type epitaxial substrate 1, where the depth of the first trench is 5.5 μm to 6.5 μm.
S200: growing a first oxide layer on the inner wall of the first groove in a thermal oxidation mode;
specifically, after the first trench is etched, oxygen is introduced at the temperature of 800-1100 ℃, and a first oxide layer 2 with the thickness of 5600-6500 a is grown to cover the surface of the first trench, wherein a high-quality oxide layer is generated in a thermal oxygen mode to be used as effective isolation between the subsequent shielding gate and the N-type epitaxial substrate 1, if the thickness is too thin, the isolation effect is poor, and if the thickness is too thick, gaps are generated in the middle when the subsequent polysilicon is filled, so that the quality of the SGT device is affected.
S300: filling N-type doped polysilicon in a first groove with the first oxide layer, and grinding and etching back after adopting a CMP technology to form a shielding gate in the first groove;
specifically, the first trench is filled with the N-type doped polysilicon 3, and then polished flat by CMP (Chemical Mechanical Planarization, chemical mechanical polishing) technology, and etched back, wherein the distance between the surface of the shielding gate and the surface of the N-type epitaxial substrate 1 is controlled to be 1.3 μm-1.7 μm, and the shielding gate can be used as a field plate depleted in the horizontal direction.
S400: etching the first oxide layer on the inner wall of the first groove to a preset depth by adopting a wet etching technology so as to form a second groove for filling the P-type doped polysilicon subsequently;
specifically, the first oxide layer 2 on the inner wall of the first trench is etched by 2.5 μm to 3.5 μm to form a second trench for filling the P-type doped polysilicon 4 later, and it should be noted that the bottom of the second trench is located in the middle region in the depth direction of the first trench.
S500: growing a second oxide layer with a preset thickness on the inner wall of the second groove in a thermal oxidation mode;
specifically, the second oxide layer (not shown) is a gate oxide layer, and the thickness is 400 a to 600 a.
S600: sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and grinding by adopting a CMP technology;
specifically, first, a P-type doped polysilicon 4 is deposited, wherein the P-type doped polysilicon 4 is a boron-doped polysilicon with a boron doping concentration of 10 17 atoms/cm 3 ~10 21 atoms/cm 3 The P-type doped polysilicon 4 is used as a diffusion source for subsequent impurities, and is diffused to the next EPI (using epitaxially grown silicon) through the gate oxide layer, i.e., the second oxide layer, of the sidewall) In the substrate, namely an N-type epitaxial substrate 1, N-type doped polysilicon 5 with the thickness of 1.2 mu m-1.4 mu m is deposited above the substrate after back etching to form a grid electrode, and then a CMP technology is adopted for flattening.
S700: after well doping, a high temperature anneal is performed to obtain SGT devices with high breakdown voltages.
Specifically, after well doping, annealing is performed at the temperature of 800-1000 ℃, at this time, boron in the P-type doped polysilicon deposited earlier is diffused into the N-type epitaxial substrate beside through the gate oxide layer on the sidewall, and as a diffusion region is denoted by a in fig. 2, a PN junction is formed, so that the depletion of the middle region of the SGT trench is enhanced, and the breakdown voltage of the SGT device is improved.
It should be noted that, in the conventional SGT process with the "cap" top-bottom structure, since the etching oxide layer is wet etching, the oxide layers on the left and right sides of the top of the shielding gate are also etched during the etching of the sidewall oxide layer, so that two grooves are naturally formed, and after the subsequent gate POLY is filled, the "cap" gate is formed to enclose the top of the shielding gate.
The technical scheme is that on the basis of the original process, polysilicon gates on the left side and the right side unique to a hat-shaped SGT are utilized, and the original N-type polysilicon is changed into double-layer P-type polysilicon and N-type polysilicon by changing the polysilicon doping types on the two sides of a shielding gate. The specific method comprises the following steps: after a groove is dug on an N-type epitaxial substrate, a side wall oxide layer is generated through thermal oxidation, then polysilicon forming a shielding gate is filled, CMP is performed to be flattened, etching is performed on the side wall oxide layer to generate a groove on the shielding gate, and then the groove is oxidized to form the gate oxide layer. Then, P-type doped polysilicon is deposited, etched back to a certain depth, then a polysilicon gate is deposited, and then the subsequent well and source doping annealing is performed, wherein P-type impurity boron in the groove can diffuse into the mesa at the side surface through the oxide layer, and a PN junction is formed with the N-type epitaxial substrate, so that the depletion in the horizontal direction is enhanced.
Therefore, an electric field intensity peak is additionally arranged between the PN junction formed by the well region and the N-type epitaxial substrate and the bottom of the groove, and the area of electric field intensity curve integration is increased, so that breakdown voltage is improved.
Referring to fig. 3, a schematic diagram of an electric field intensity distribution curve of the SGT is shown, wherein in a region a where boron diffuses in a middle region of the trench, the electric field intensity becomes higher due to depletion enhancement, and compared with the prior art, the curve integration area becomes larger, and the breakdown voltage becomes higher.
The invention is further illustrated by the following examples:
example 1
The embodiment provides a process method of an SGT device, which comprises the following steps:
(1) Providing an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove depth of 5.5 mu m;
(2) Introducing oxygen in a thermal oxidation mode at the temperature of 800 ℃ to grow a first oxide layer with the thickness of 5600 a;
(3) Filling N-type doped polysilicon in a first groove with a first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is controlled to be 1.3 mu m;
(4) Etching the first oxide layer on the inner wall of the first groove by adopting a wet etching technology to form a second groove for filling the P-type doped polysilicon subsequently;
(5) Growing a second oxide layer with the thickness of 400A on the inner wall of the second groove in a thermal oxidation mode;
(6) Sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and flattening by adopting a CMP technology, wherein the P-type doped polysilicon is boron-doped polysilicon, and the boron doping concentration is 10 17 atoms/cm 3 After back etching, depositing 1.2 mu m polysilicon above the P-type doped polysilicon to form a grid electrode;
(7) After well doping, an anneal is performed at 800 ℃ to obtain SGT devices with high breakdown voltages.
Example 2
The embodiment provides a process method of an SGT device, which comprises the following steps:
(1) Providing an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove depth of 5.5 mu m;
(2) Introducing oxygen in a thermal oxidation mode at the temperature of 800 ℃ to grow a first oxide layer with the thickness of 5600 a;
(3) Filling N-type doped polysilicon in a first groove with a first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is controlled to be 1.3 mu m;
(4) Etching the first oxide layer on the inner wall of the first groove by adopting a wet etching technology to form a second groove for filling the P-type doped polysilicon subsequently;
(5) Growing a second oxide layer with the thickness of 400A on the inner wall of the second groove in a thermal oxidation mode;
(6) Sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and flattening by adopting a CMP technology, wherein the P-type doped polysilicon is boron-doped polysilicon, and the boron doping concentration is 10 17 atoms/cm 3 After back etching, depositing 1.2 mu m polysilicon above the P-type doped polysilicon to form a grid electrode;
(7) After well doping, an anneal is performed at 800 ℃ to obtain SGT devices with high breakdown voltages.
Example 3
The embodiment provides a process method of an SGT device, which comprises the following steps:
(1) Providing an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove depth of 5.5 mu m;
(2) Introducing oxygen in a thermal oxidation mode at the temperature of 800 ℃ to grow a first oxide layer with the thickness of 5600 a;
(3) Filling N-type doped polysilicon in a first groove with a first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is controlled to be 1.3 mu m;
(4) Etching the first oxide layer on the inner wall of the first groove by adopting a wet etching technology to form a second groove for filling the P-type doped polysilicon subsequently;
(5) Growing a second oxide layer with the thickness of 400A on the inner wall of the second groove in a thermal oxidation mode;
(6) Sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and flattening by adopting a CMP technology, wherein the P-type doped polysilicon is boron-doped polysilicon, and the boron doping concentration is 10 17 atoms/cm 3 After back etching, depositing 1.2 mu m polysilicon above the P-type doped polysilicon to form a grid electrode;
(7) After well doping, an anneal is performed at 800 ℃ to obtain SGT devices with high breakdown voltages.
Example 4
The embodiment provides a process method of an SGT device, which comprises the following steps:
(1) Providing an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove depth of 6 mu m;
(2) Introducing oxygen in a thermal oxidation mode at the temperature of 900 ℃ to grow a first oxide layer with the thickness of 5900A;
(3) Filling N-type doped polysilicon in a first groove with a first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is controlled to be 1.5 mu m;
(4) Etching the first oxide layer on the inner wall of the first groove by adopting a wet etching technology to form a second groove for filling the P-type doped polysilicon subsequently;
(5) Growing a second oxide layer with the thickness of 500A on the inner wall of the second groove in a thermal oxidation mode;
(6) Sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and flattening by adopting a CMP technology, wherein the P-type doped polysilicon is boron-doped polysilicon, and the boron doping concentration is 10 18 atoms/cm 3 After back etching, depositing 1.3 mu m polysilicon above the P-type doped polysilicon to form a grid;
(7) After well doping, an anneal is performed at 900 ℃ to obtain SGT devices with high breakdown voltages.
Example 5
The embodiment provides a process method of an SGT device, which comprises the following steps:
(1) Providing an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove depth of 6.5 mu m;
(2) Introducing oxygen in a thermal oxidation mode at the temperature of 1000 ℃ to grow a first oxide layer with the thickness of 6200A;
(3) Filling N-type doped polysilicon in a first groove with a first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is controlled to be 1.7 mu m;
(4) Etching the first oxide layer on the inner wall of the first groove by adopting a wet etching technology to form a second groove for filling the P-type doped polysilicon subsequently;
(5) Growing a second oxide layer with the thickness of 600A on the inner wall of the second groove in a thermal oxidation mode;
(6) Sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and flattening by adopting a CMP technology, wherein the P-type doped polysilicon is boron-doped polysilicon, and the boron doping concentration is 10 19 atoms/cm 3 1.4 mu m of P-type doped polysilicon is deposited above after back etchingForming a grid electrode by polysilicon;
(7) After well doping, annealing is performed at a temperature of 1000 ℃ to obtain SGT devices with high breakdown voltages.
Example 6
The embodiment provides a process method of an SGT device, which comprises the following steps:
(1) Providing an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove depth of 5.5 mu m;
(2) Introducing oxygen in a thermal oxidation mode at the temperature of 800 ℃ to grow a first oxide layer with the thickness of 5600 a;
(3) Filling N-type doped polysilicon in a first groove with a first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is controlled to be 1.3 mu m;
(4) Etching the first oxide layer on the inner wall of the first groove by adopting a wet etching technology to form a second groove for filling the P-type doped polysilicon subsequently;
(5) Growing a second oxide layer with the thickness of 400A on the inner wall of the second groove in a thermal oxidation mode;
(6) Sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and flattening by adopting a CMP technology, wherein the P-type doped polysilicon is boron-doped polysilicon, and the boron doping concentration is 10 21 atoms/cm 3 After back etching, depositing 1.2 mu m polysilicon above the P-type doped polysilicon to form a grid electrode;
(7) After well doping, an anneal is performed at 800 ℃ to obtain SGT devices with high breakdown voltages.
Comparative example 1
The present comparative example provides an SGT device prepared by conventional processes, i.e., after a trench is dug in an epitaxial substrate, a sidewall oxide layer is formed by thermal oxidation, then polysilicon is filled into the trench, the polysilicon is etched down to form a shield gate, then the sidewall oxide layer is removed by wet etching, and then POLY (polysilicon) is refilled after gate oxide is formed by oxidation.
Comparative example 2
The present comparative example provides a process for SGT devices, which differs from that of example 1 in that in step (4), the first oxide layer on the inner wall of the first trench is etched by 2 μm using a wet etching technique to form a second trench for subsequently filling P-type doped polysilicon.
The SGT devices prepared in comparative examples 1 and 2 were subjected to a breakdown voltage test of 100V by subjecting example 1 to example 6, and the specific results are as follows:
as can be seen from the table, the breakdown voltage of the SGT device prepared by the method in the example of the present invention is significantly improved, the highest breakdown voltage can reach 114V, while the breakdown voltages of the SGT devices prepared in comparative examples 1 and 2 are only 110V and 106V, respectively, and in particular, as can be seen from examples 1 to 2, the breakdown voltage at the first oxide etch depth of 3 μm is higher than the breakdown voltage at the first oxide etch depth of 2.5 μm, and when the first oxide etch depth exceeds 3 μm, the breakdown voltage is not further improved, and when the first oxide etch depth is less than 2.5 μm, the breakdown voltage is reduced, as can be seen in combination with comparative example 2. In comparative example 1, the breakdown voltage of the SGT device was slightly better than in comparative example 1 when only N-doped polysilicon was deposited in the second trench and P-doped polysilicon was not filled. In addition, in example 6, the breakdown voltage of the SGT device would instead decrease when the boron doping concentration is too high, with other conditions unchanged.
The embodiment of the invention also provides an SGT device, which is prepared by the technical method of the SGT device.
In summary, the method for manufacturing the SGT device and the SGT device according to the embodiments of the present invention provide an N-type epitaxial substrate, etch a first trench on the N-type epitaxial substrate, then grow a first oxide layer on the inner wall of the first trench by thermal oxidation, fill N-type doped polysilicon, polish the first oxide layer by CMP, etch back the first oxide layer to form a shield gate in the first trench, etch the first oxide layer to a predetermined depth by wet etching, then grow a second oxide layer to a predetermined thickness on the inner wall of the second trench by thermal oxidation, sequentially deposit P-type doped polysilicon and N-type doped polysilicon in the second trench by CMP, polish the second oxide layer by CMP, finally polish the second oxide layer by CMP, and anneal the second oxide layer at a high temperature to obtain the SGT device with a high breakdown voltage.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (8)
1. A process for forming an SGT device, said process comprising:
providing an N-type epitaxial substrate, and etching the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first groove;
growing a first oxide layer on the inner wall of the first groove in a thermal oxidation mode;
filling N-type doped polysilicon in a first groove with the first oxide layer, and carrying out back etching after flattening by adopting a CMP technology to form a shielding gate in the first groove, wherein the distance between the surface of the shielding gate and the surface of an N-type epitaxial substrate is 1.3-1.7 mu m;
etching the first oxide layer on the inner wall of the first groove to a preset depth by adopting a wet etching technology to form a second groove for filling P-type doped polysilicon, wherein the preset depth is 2.5-3.5 mu m;
growing a second oxide layer with a preset thickness on the inner wall of the second groove in a thermal oxidation mode;
sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, and grinding by adopting a CMP technology;
after well doping, high temperature annealing is performed, and boron in the deposited P-type doped polysilicon diffuses into the lateral N-type epitaxial substrate through the second oxide layer of the sidewall to obtain an SGT device with high breakdown voltage.
2. The method of claim 1, wherein the first trench has a depth of 5.5 μm to 6.5 μm.
3. The method according to claim 1, wherein in the step of growing the first oxide layer on the inner wall of the first trench by thermal oxidation, oxygen is introduced at a temperature of 800 ℃ to 1100 ℃ to grow the first oxide layer with a thickness of 5600 a to 6500 a.
4. The method according to claim 1, wherein in the step of growing a second oxide layer with a predetermined thickness on the inner wall of the second trench by thermal oxidation, the thickness of the second oxide layer is 400 a to 600 a.
5. The process of claim 1, wherein the P-type doped polysilicon and the N-type doped polysilicon are sequentially deposited in the second trench and planarized by CMP, the P-type doped polysilicon being boron doped polysiliconWherein the doping concentration of boron is 10 17 atoms/cm 3 ~10 21 atoms/cm 3 。
6. The method of claim 1, wherein the P-type doped polysilicon and the N-type doped polysilicon are sequentially deposited in the second trench and planarized by CMP, and the thickness of the N-type doped polysilicon deposited is 1.2 μm to 1.4 μm.
7. The method of claim 1, wherein the step of doping the wells followed by a high temperature anneal to obtain SGT devices with high breakdown voltages comprises annealing at a temperature of 800 ℃ to 1000 ℃.
8. An SGT device manufactured by the process of any one of claims 1 to 7.
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| CN106024892A (en) * | 2016-05-26 | 2016-10-12 | 东南大学 | Hole current shunting type power transistor with high avalanche tolerance and preparation method thereof |
| US9812564B1 (en) * | 2016-08-25 | 2017-11-07 | Silicongear Corporation | Split-gate MOSFET |
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