CN114784093A - Method for improving withstand voltage of SGT MOSFET, SGT MOSFET device and manufacturing method - Google Patents
Method for improving withstand voltage of SGT MOSFET, SGT MOSFET device and manufacturing method Download PDFInfo
- Publication number
- CN114784093A CN114784093A CN202210566172.XA CN202210566172A CN114784093A CN 114784093 A CN114784093 A CN 114784093A CN 202210566172 A CN202210566172 A CN 202210566172A CN 114784093 A CN114784093 A CN 114784093A
- Authority
- CN
- China
- Prior art keywords
- electric field
- boron
- sgt
- sgt mosfet
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000005684 electric field Effects 0.000 claims abstract description 104
- 239000000463 material Substances 0.000 claims description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 229920005591 polysilicon Polymers 0.000 claims description 37
- 239000000126 substance Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 16
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000009826 distribution Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for improving the withstand voltage of an SGT MOSFET, an SGT MOSFET device and a manufacturing method. According to the technical scheme, the third electric field peak is introduced, the peak improves a sunken electric field between the first electric field peak and the second electric field peak, the area of the electric field intensity integrated along with the distance is increased, and the voltage endurance capacity of the device is improved.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a method for improving the withstand voltage of an SGT MOSFET (metal-oxide-semiconductor field effect transistor), an SGT MOSFET device, a method for manufacturing a P-junction region and a method for manufacturing the SGT MOSFET device.
Background
An SGT (Shielded Gate Transistor) MOSFET is a new type of power semiconductor device. The SGT process is simpler than a common trench and has less switching loss. In addition, the SGT is 3-5 times deeper than the conventional trench process, and more epitaxial volume can be used to block the voltage, which also makes the internal resistance of the SGT more than 2 times lower than that of the conventional MOSFET.
A conventional SGT (Split-Gate-Trench) MOSFET structure and electric field distribution are shown in fig. 1, an N + semiconductor substrate is arranged on a metal layer 1 on the back of the conventional SGT structure, an N-epitaxial layer 3 is formed on the surface of the N + semiconductor substrate, such as a silicon substrate 2, a Trench is formed in the N-epitaxial layer 3, and a Gate structure is formed in the Trench and includes an oxide layer 4, source polysilicon 5, an IPO oxide layer 6, Gate polysilicon 7, a dielectric layer 8 and Gate oxide 13; the P-well region 11 is formed in the surface region of the N-epitaxial layer 3, and the N-epitaxial layer 3 at the bottom of the P-well region 11 is used as a drift region; n + source regions 10 are formed on the surface of P-well regions 11.
The SGT (Split-Gate-Trench) MOSFET structure introduces horizontal depletion based on vertical depletion of the conventional Trench MOSFET due to its charge-coupled effect, thereby obtaining a higher device Breakdown Voltage (BV). This allows the use of a more concentrated N-epitaxial layer 3 at the same Breakdown Voltage (BV) and thus a reduction of the on-resistance (Rdson). However, in the conventional SGT MOSFET structure, a first electric field peak is formed at the bottom of the P-well region 11, a second electric field peak is formed at the bottom of the source polysilicon 5, and an electric field between the two peaks is distributed in a concave manner, so that the voltage resistance of the device is limited.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a method for improving the withstand voltage of an SGT MOSFET, which improves the withstand voltage capability of a device by optimizing and improving the electric field distribution of a concave region between a first electric field peak and a second electric field peak.
According to the method for improving the withstand voltage of the SGT MOSFET, a third electric field peak is introduced between a first electric field peak formed at the bottom of a P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of source polysilicon, and the third electric field peak is used for raising an electric field between the first electric field peak and the second electric field peak.
In some embodiments, the third electric field spike is introduced to a lowest electric field strength between the first and second electric field spikes. The third electric field peak is introduced to the lowest part of the electric field intensity, and the voltage-resistant effect is further improved.
Another aspect of the invention herein provides an SGT MOSFET device that includes a P-junction region for forming a third electric field spike formed between a first electric field spike formed at a bottom of a P-well region of the SGT MOSFET and a second electric field spike formed at a bottom of source polysilicon.
In some embodiments, the P-junction region is located at a source polysilicon top region.
The present invention in a third aspect herein provides a method for fabricating a P-junction region, the method comprising the steps of:
the method comprises the following steps: depositing a boron-doped substance;
step two: etching the boron-doped material back to the designated position;
step three: and (4) performing high-temperature rapid annealing to enable boron in the boron-doped substance to be diffused into the Si material on the periphery of the groove to form a P-junction region.
In some embodiments, the step of back etching the boron-doped material to the top 1500 Ǻ -3000 Ǻ of the source polysilicon.
In some embodiments, when boron in the boron-doped material is diffused into the Si material at the periphery of the trench, the diffused boron concentration is greater than the phosphorus concentration of the substrate therein to ensure the formation of a stable and efficient P-junction region.
In some embodiments, the step three anneal temperature is between 800 ℃ and 1000 ℃.
The invention provides a method for manufacturing an SGT MOSFET device, which comprises a P-junction region for forming a third electric field peak between a first electric field peak formed at the bottom of a P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of source polysilicon; the manufacturing method comprises the following steps of manufacturing according to an SGT process until an IPO oxide layer is deposited, and etching back the oxide layer:
the method comprises the following steps: etching back the oxide layer to the lower part of the source polysilicon;
step two: depositing a boron-doped substance;
step three: etching the boron-doped material back to the designated position;
step four: high-temperature rapid annealing is carried out, so that boron in the boron-doped substance is diffused into the Si material at the periphery of the groove to form a P-junction region;
step five: removing boron-doped substances;
and after removing the boron-doped substance, manufacturing gate polysilicon, a dielectric layer, a front metal layer, an N + source region, a P-well region and gate oxide according to an SGT (metal gate oxide semiconductor field effect transistor) process to obtain the SGT MOSFET device.
In some embodiments, the oxide layer is etched back to 1500 Ǻ -2000 Ǻ below the source polysilicon.
In some embodiments, the boron-doped material is etched back to the source polysilicon top regions 1500 Ǻ -3000 Ǻ.
In some embodiments, the annealing temperature is between 800 ℃ and 1000 ℃.
By adopting the technical scheme of the invention, the beneficial effects at least comprise:
1) according to the technical scheme, the third electric field peak is introduced, the concave electric field between the first electric field peak and the second electric field peak is improved through the peak, the area of the electric field intensity integrated along with the distance is increased, and the voltage resistance of the device is improved.
2) The boron-doped substance is etched back to the top 1500 Ǻ -3000 Ǻ of the source polysilicon, because the electric field intensity close to the P-well region is lowest, the third electric field peak of the P-junction region is introduced to be pulled up but cannot be connected with the P-well region (after connection, the threshold value of the device is too large or even cannot be started), so that the electric field distribution of the concave region between the first electric field peak and the second electric field peak is improved more preferably, and the pressure resistance improvement effect is better.
3) The annealing temperature is controlled between 800 ℃ and 1000 ℃, so that under diffusion (the depth of a P-junction region 12 is very shallow and the concentration is very low, the pressure resistance improvement is influenced) or over diffusion (the depth of the P-junction region is too deep, the connection between trenches is caused seriously, and a device cannot be normally started) is effectively prevented.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a diagram of a conventional SGT MOSFET structure and electric field distribution;
FIG. 2 is a diagram illustrating an SGT MOSFET structure and electric field distribution provided by the present invention;
FIGS. 3-8 are step diagrams of a method of fabricating an SGT MOSFET device according to the present invention;
in the drawings: in the drawings: 1-back metal layer, 2-N + substrate, 3-N-epitaxy, 4-oxide layer, 5-source polysilicon, 6-IPO oxide layer, 7-gate polysilicon, 8-dielectric layer, 9-front metal layer, 10-N + source region, 11-P-well region, 12-P-junction region, 13-gate oxide and 14-boron-doped substance.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
As shown in fig. 1, a conventional SGT (Split-Gate-Trench) MOSFET structure and electric field distribution are shown, where an electric field intensity peak 1 is located at the bottom of a P-well region 11, an electric field intensity peak 2 is located at the bottom of source polysilicon 5, and an electric field between the two peaks is in a concave distribution, so that the voltage resistance of a device is limited.
The invention realizes the improvement of the voltage resistance of the device by optimizing and improving the electric field distribution of the depressed area, and the invention introduces a third electric field peak which is positioned between a first electric field peak formed at the bottom of a P-well area of the SGT MOSFET and a second electric field peak formed at the bottom of the source polysilicon, as shown in figure 2. Because the withstand voltage of the SGT device is the integral of the electric field intensity along with the distance, and the third electric field peak is introduced, the sunken electric field between the first electric field peak and the second electric field peak is improved, the area of the electric field intensity along with the distance integral is increased, and the withstand voltage capability of the device is improved.
In this disclosure, the third electric field peak is used for optimizing the sunken electric field between first electric field peak and the second electric field peak, and its position can be according to arbitrary setting, based on SGT device characteristic, is being close to the electric field intensity of P-well region 11 minimum, sets up the third electric field peak and draws high to this electric field intensity minimum here, and withstand voltage promotes effectually.
The SGT MOSFET structure provided by the present invention is exemplarily shown in fig. 2, and is configured to include a back metal layer 1, an N + substrate 2, an N-epi 3, an oxide layer 4, a source polysilicon 5, an IPO oxide layer 6, a gate polysilicon 7, a dielectric layer 8, a front metal layer 9, an N + source region 10, a P-well region 11, a P-junction region 12, and a gate oxide 13; wherein, an N + substrate 2 is arranged on the back metal layer 1, an N-epitaxial layer 3 is formed on the surface of the N + substrate 2 such as a silicon substrate, a groove is formed in the N-epitaxial layer 3, and a grid structure is formed in the groove and comprises an oxide layer 4, a source polysilicon 5, an IPO oxide layer 6, a grid polysilicon 7, a dielectric layer 8 and a grid oxide 13; the P-well region 11 is formed in the surface region of the N-epitaxial layer 3, and the N-epitaxial layer 3 at the bottom of the P-well region 11 is used as a drift region; n + source regions 10 are formed on the surface of P-well regions 11.
In the SGT MOSFET structure, the P-junction region 12 is used to form a third electric field peak for optimizing the recess electric field between the first electric field peak and the second electric field peak, and the position of the P-junction region 12 can be arbitrarily set. Based on SGT device characteristics, the P-junction region 12 is arranged in the top region of the source polysilicon 5 when the electric field intensity near the P-well region 11 is lowest, so that the third electric field peak formed by the P-junction region is used for raising the lowest part of the electric field intensity, and the withstand voltage improvement effect is good.
The P-junction region 12 in the present disclosure is prepared by depositing boron-doped material- > boron-doped material back etching- > high temperature rapid annealing, and specifically comprises the following steps:
the method comprises the following steps: the boron-doped material 14 is deposited by depositing the boron-doped material 14 in a stacked manner in the trench to a thickness to fill the trench to ensure sufficient consumption of the subsequent etch-back, as shown in fig. 4.
Step two: etching back the boron-doped material 14, and etching back the boron-doped material 14 to the designated position, as shown in fig. 5; in this step, the back etching of the boron-doped material 14 is performed by a dry etching method, a wet etching method, CMP or other etching methods capable of back etching the boron-doped material 14 to a specific position.
Step three: high temperature rapid annealing to diffuse boron in the boron-doped material 14 into the Si material at the periphery of the trench to form a P-junction region 12, as shown in FIG. 6; the Boron concentration in the Boron-doped material 14 after diffusion is greater than the phosphorus phoshor of the N-epi 3 here to ensure the formation of an effective P-junction region 12.
In order to prevent the P-junction region 12 from being shallow in depth and low in concentration due to Boron under-diffusion and affecting the pressure resistance improvement effect, or the P-junction region 12 formed from over-diffusion is too deep and severe so that the trenches are connected and the device cannot be normally started, the annealing temperature is controlled to be 800-1000 ℃ in the high-temperature rapid annealing process.
When the boron-doped material 14 is etched back, the designated position is located at any position of the region corresponding to the recessed electric field between the first electric field peak and the second electric field peak, such as any position from the upper dotted line to the lower dotted line in the electric field distribution shown in fig. 1, but cannot be connected with the P-well region 11; the boron-doped material 14 is etched back to 1500 Ǻ -3000 Ǻ of the top of the source polysilicon 5, the electric field intensity of the position close to the P-well region 11 is the lowest, the peak 3 of the P-junction region 12 is introduced to be pulled up, but the position cannot be connected with the P-well region 11 (after connection, the threshold value of the device is too large, even the device cannot be started), so that the voltage resistance improvement effect is better, and certainly, the boron-doped material 14 is etched back to other positions, the concave electric field can be pulled up, and the effect of optimizing the concave electric field is achieved to improve the voltage resistance of the device.
With reference to fig. 3-8, the SGT MOSFET device provided herein is fabricated according to conventional SGT MOSFET processes until the time when the oxide layer 4 is etched back before deposition of the IPO oxide layer 6, the following steps are performed:
the method comprises the following steps: the oxide layer 4 is etched back to 1500 Ǻ -2000 Ǻ or other locations under the source polysilicon 5 as shown in FIG. 3.
Step two: the boron-doped material 14 is deposited by depositing the boron-doped material 14 in a stacked manner within the trench to a thickness to fill the trench, as shown in figure 4.
Step three: etching back the boron-doped material 14, and etching back the boron-doped material 14 to the designated position, as shown in fig. 5; the designated position is located at any position of the region corresponding to the recessed electric field between the first electric field peak and the second electric field peak, such as any position from the upper dotted line to the lower dotted line in the electric field distribution shown in fig. 1, but cannot be connected to the P-well region 11, i.e. the P-junction region 12 cannot be connected to the P-well region 11, otherwise the device cannot be turned on; the boron-doped substance 14 is etched back to 1500 Ǻ -3000 Ǻ at the top of the source polysilicon 5, the electric field intensity at the position close to the P-well region 11 is the lowest, the peak 3 of the P-junction region 12 is introduced to pull up, but the boron-doped substance cannot be connected with the P-well region 11 (after connection, the threshold value of a device is too large, even the device cannot be started), so that the pressure resistance improvement effect is better; in this step, the back etching of the boron-doped material 14 is performed by a dry etching method, a wet etching method, CMP or other etching methods capable of back etching the boron-doped material 14 to a predetermined position.
Step four: performing high-temperature rapid annealing to enable Boron in the Boron-doped substance 14 to diffuse into the Si material on the periphery of the trench to form a P-junction region 12, as shown in FIG. 6; the annealing temperature is controlled between 800 ℃ and 1000 ℃.
Step five: the boron-doped material 14 is removed and the silicon is as shown in fig. 7; the Boron-doped substance 14 contains a certain amount of Boron, and if not removed, the Boron can be continuously diffused in the subsequent process, which is not beneficial to controlling the structure of the device; after the boron-doped material 14 is removed, the gate polysilicon, the dielectric layer, the front metal layer, the N + source region, the P-well region and the gate oxide are fabricated according to the SGT process to obtain the SGT MOSFET device, as shown in fig. 8.
When the boron-doped substance 14 is removed, the wet removal method is adopted, so that the condition that the loss of the side wall of the groove is caused, and the performance of the device is influenced can be effectively avoided.
In the present disclosure, the Boron-doped material 14 is a source of Boron, which is diffused to form the P-junction region 12; the Boron-doped material 14 is configured as borosilicate glass BSG, and the P-junction region 12 is formed on top of the source polysilicon 5 by diffusing the borosilicate glass BSG into Boron Boron impurities, or is configured as polysilicon to replace the borosilicate glass BSG to obtain the P-junction region 12; or other Boron-doped Boron species.
The fabrication according to the conventional SGT MOSFET process in this disclosure may be performed according to the fabrication methods disclosed in prior art SGT devices and methods of fabrication (publication No. CN109935517A, publication No. 2019.06.25) until after the IPO oxide layer 6 is deposited, the oxide layer 4 is etched back, and the boron-doped material is removed. It will of course be appreciated that other conventional SGT MOSFET processes may be used.
According to the technical scheme, the third electric field peak is introduced to improve the recessed electric field between the first electric field peak and the second electric field peak, and compared with a conventional SGT MOSFET, the voltage resistance of a device is obviously improved; the P-junction region 12 of the SGT MOSFET device cannot be connected to the P-well region 11, which would otherwise cause the device to fail to turn on.
The present disclosure has been described in relation to the above embodiments, which are only examples for implementing the present disclosure. It must be noted that the disclosed embodiments do not limit the scope of the disclosure. Rather, variations and modifications may be made without departing from the spirit and scope of the disclosure, which should be determined from the substance of the claims that follow.
Claims (12)
1. A method for improving the withstand voltage of an SGT MOSFET is characterized in that a third electric field spike is introduced between a first electric field spike formed at the bottom of a P-well region of the SGT MOSFET and a second electric field spike formed at the bottom of source polysilicon, and the third electric field spike is used for raising an electric field between the first electric field spike and the second electric field spike.
2. A method of boosting a withstand voltage of an SGT MOSFET as claimed in claim 1, wherein said third electric field spike is introduced to a lowest electric field strength between said first electric field spike and said second electric field spike.
3. An SGT MOSFET device comprising a P-junction region for forming a third electric field spike formed between a first electric field spike formed at a bottom of a P-well region of the SGT MOSFET and a second electric field spike formed at a bottom of source polysilicon.
4. The SGT MOSFET device of claim 3, wherein the P-junction region is located at a source polysilicon top region.
5. A method for fabricating a P-junction region, the method comprising the steps of:
the method comprises the following steps: depositing a boron-doped substance;
step two: etching the boron-doped material back to the designated position;
step three: and high-temperature rapid annealing is carried out, so that boron in the boron-doped substance is diffused into the Si material on the periphery of the groove to form a P-junction region.
6. The method of claim 5 wherein the second boron-doped material is etched back to the source polysilicon tops 1500 Ǻ -3000 Ǻ.
7. The method of claim 5 wherein the boron in the boron-doped material diffuses to the Si material at the periphery of the trench to a boron concentration greater than the phosphorus concentration of the substrate there.
8. The method of claim 5, wherein the step three anneal temperature is between 800 ℃ and 1000 ℃.
9. A manufacturing method of an SGT MOSFET device is characterized in that the SGT MOSFET device manufactured by the manufacturing method comprises a P-junction area, wherein the P-junction area is used for forming a third electric field peak, and the third electric field peak is formed between a first electric field peak formed at the bottom of a P-well area of the SGT MOSFET and a second electric field peak formed at the bottom of source polysilicon; the manufacturing method comprises the following steps of manufacturing according to an SGT process until an IPO oxide layer is deposited, and etching back the oxide layer:
the method comprises the following steps: etching back the oxide layer to the lower part of the source polysilicon;
step two: depositing a boron-doped substance;
step three: etching the boron-doped material back to the designated position;
step four: high-temperature rapid annealing is carried out, so that boron in the boron-doped substance is diffused into the Si material on the periphery of the groove to form a P-junction area;
step five: removing boron-doped substances;
and after removing the boron-doped substance, manufacturing gate polysilicon, a dielectric layer, a front metal layer, an N + source region, a P-well region and gate oxide according to an SGT (standard bulk transistor) process to obtain the SGT MOSFET device.
10. The SGT MOSFET device manufacturing method of claim 9, wherein: the oxide layer is etched back to 1500 Ǻ -2000 Ǻ below the source polysilicon.
11. A method of fabricating an SGT MOSFET device according to claim 9, wherein: the boron-doped material is etched back to the top area 1500 Ǻ -3000 Ǻ of the source polysilicon.
12. The SGT MOSFET device manufacturing method of claim 9, wherein: the annealing temperature is between 800 ℃ and 1000 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210566172.XA CN114784093A (en) | 2022-05-24 | 2022-05-24 | Method for improving withstand voltage of SGT MOSFET, SGT MOSFET device and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210566172.XA CN114784093A (en) | 2022-05-24 | 2022-05-24 | Method for improving withstand voltage of SGT MOSFET, SGT MOSFET device and manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114784093A true CN114784093A (en) | 2022-07-22 |
Family
ID=82408567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210566172.XA Pending CN114784093A (en) | 2022-05-24 | 2022-05-24 | Method for improving withstand voltage of SGT MOSFET, SGT MOSFET device and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114784093A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116581154A (en) * | 2023-07-12 | 2023-08-11 | 江西萨瑞半导体技术有限公司 | SGT device and process method thereof |
-
2022
- 2022-05-24 CN CN202210566172.XA patent/CN114784093A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116581154A (en) * | 2023-07-12 | 2023-08-11 | 江西萨瑞半导体技术有限公司 | SGT device and process method thereof |
| CN116581154B (en) * | 2023-07-12 | 2023-10-10 | 江西萨瑞半导体技术有限公司 | SGT device and process method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7045857B2 (en) | Termination for trench MIS device having implanted drain-drift region | |
| US7326995B2 (en) | Trench MIS device having implanted drain-drift region and thick bottom oxide | |
| KR100759937B1 (en) | A trench mosfet device, and a method of forming such a trench mosfet device | |
| US7323386B2 (en) | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics | |
| US7291884B2 (en) | Trench MIS device having implanted drain-drift region and thick bottom oxide | |
| US7118953B2 (en) | Process of fabricating termination region for trench MIS device | |
| EP1269530A2 (en) | Method of making a trench gate dmos transistor | |
| US20040169220A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN108447911B (en) | Deep and shallow groove semiconductor power device and preparation method thereof | |
| CN210110783U (en) | Integrated high-performance LDMOS structure | |
| CN114784093A (en) | Method for improving withstand voltage of SGT MOSFET, SGT MOSFET device and manufacturing method | |
| CN109979987A (en) | A kind of shield grid power device and manufacturing method | |
| CN107342226B (en) | Manufacturing method of ultra-small unit size longitudinal super junction semiconductor device | |
| CN1536630A (en) | Method for mfg. vertical MOS transistor | |
| CN100508210C (en) | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same | |
| CN112635331B (en) | Preparation method of super junction power device | |
| CN113871481B (en) | Semiconductor power device with silicon carbide super junction | |
| US7091080B2 (en) | Depletion implant for power MOSFET | |
| CN115458591A (en) | SIC semiconductor power device with low on-resistance and low switching loss |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 400000 Room 608, floor 6, No. 39, Yonghe Road, Yuzui Town, Jiangbei District, Chongqing Applicant after: Chongqing Yuntong Technology Co.,Ltd. Address before: 518118 Room 401, building 1, xiehechang District B, No. 5 Baodong Road, xiuxin community, Kengzi street, Pingshan District, Shenzhen, Guangdong Province Applicant before: Shenzhen Yuntong Technology Co.,Ltd. |
|
| CB02 | Change of applicant information |