CN116581034A - Packaging method of semiconductor power module, semiconductor power module and processor - Google Patents
Packaging method of semiconductor power module, semiconductor power module and processor Download PDFInfo
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- CN116581034A CN116581034A CN202310226022.9A CN202310226022A CN116581034A CN 116581034 A CN116581034 A CN 116581034A CN 202310226022 A CN202310226022 A CN 202310226022A CN 116581034 A CN116581034 A CN 116581034A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 238000005245 sintering Methods 0.000 claims abstract description 84
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052709 silver Inorganic materials 0.000 claims abstract description 52
- 239000004332 silver Substances 0.000 claims abstract description 52
- 238000005516 engineering process Methods 0.000 claims abstract description 22
- 229910052802 copper Inorganic materials 0.000 claims description 46
- 239000010949 copper Substances 0.000 claims description 46
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 45
- 238000003466 welding Methods 0.000 claims description 10
- 238000005476 soldering Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 5
- 239000005022 packaging material Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000010137 moulding (plastic) Methods 0.000 claims 2
- 230000017525 heat dissipation Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 8
- 239000002245 particle Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000011148 porous material Substances 0.000 description 5
- 210000003739 neck Anatomy 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000009529 body temperature measurement Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application discloses a packaging method of a semiconductor power module, the semiconductor power module and a processor. The method comprises the following steps: sintering the top of the radiator and the bottom of the substrate by a silver sintering technology; sintering the drain region of the chip and the top of the substrate by a silver sintering technology; sintering the grid resistor, the thermistor and the top of the substrate by a silver sintering technology; and performing plastic packaging treatment on the substrate, the chip, the grid resistor, the thermistor and the radiator to obtain the packaged semiconductor power module. The semiconductor power module provided by the application can reduce the failure risk of the module, reduce the height of the module on the basis of ensuring the creepage distance and the electric gap, reduce the loss and improve the heat dissipation efficiency.
Description
Technical Field
The present application relates to the field of semiconductors, and in particular, to a method for packaging a semiconductor power module, and a processor.
Background
With the continuous development of the electronic industry, the semiconductor power module plays a key role in solving the energy problem, and for high-voltage and high-current AC/DC converters, such as inverters of new energy automobiles, the semiconductor power module can improve the switching frequency of the inverter, reduce the switching loss, reduce the thermal resistance and improve the reliability, thereby realizing the energy saving aim of reducing the power consumption. In the related art, when the semiconductor power module is packaged, the radiator is mainly packaged through solder paste, however, a larger cavity is formed between the radiator and the power module in a welding mode, so that the problem that the radiating efficiency of the semiconductor power module is low and the using power consumption is increased is caused.
Aiming at the problem that a larger cavity is formed between a radiator and a power module when the semiconductor power module is packaged in the related art, no effective solution is proposed at present.
Disclosure of Invention
The application mainly aims to provide a packaging method of a semiconductor power module, the semiconductor power module and a processor, so as to solve the problem that a larger cavity is formed between a radiator and the power module when the semiconductor power module is packaged in the related art.
In order to achieve the above object, according to one aspect of the present application, there is provided a packaging method of a semiconductor power module. The method comprises the following steps: sintering the top of the radiator and the bottom of the substrate by a silver sintering technology; sintering the drain region of the chip and the top of the substrate by a silver sintering technology; sintering the grid resistor, the thermistor and the top of the substrate by a silver sintering technology; and performing plastic packaging treatment on the substrate, the chip, the grid resistor, the thermistor and the radiator to obtain the packaged semiconductor power module.
Optionally, before the plastic packaging process is performed on the substrate, the chip, the gate resistor, the thermistor and the heat sink, the method further includes: welding a copper clip on a substrate, and connecting pins of the copper clip with a source electrode area of a chip; the application frame terminals are connected to the substrate by ultrasonic welding.
Optionally, the plastic packaging process for the substrate, the chip, the gate resistor, the thermistor and the heat sink includes: determining the thickness and width of an unpackaged semiconductor power module; judging whether the thickness is in the thickness range or not, and judging whether the width is in the width range or not; and under the condition that the thickness is in the thickness range and the width is in the width range, carrying out plastic packaging treatment on the non-plastic packaged semiconductor power module through the target plastic packaging material.
Optionally, before the plastic packaging process is performed on the substrate, the chip, the gate resistor, the thermistor and the heat sink, the method further includes: and carrying out wire bonding treatment on the chip, the grid resistor and the thermistor on the substrate according to a preset circuit diagram.
According to another aspect of the present application, a semiconductor power module is provided. Comprising the following steps: the radiator is provided with pin fins below; the base plate covers the upper part of the radiator, wherein the base plate is a metal base plate; a plurality of chips disposed over the substrate, each chip including a source region, a gate region, and a drain region, the drain region of each chip being connected to the substrate; the grid resistors are arranged above the substrate, and each grid resistor is arranged in a first preset range of one chip and is connected with a grid region of the chip; the copper clips are arranged above the substrate and connected with the source electrode area of the chip; the wafer is arranged above the substrate and connected with the substrate.
Optionally, the semiconductor power module further includes a thermistor, and the thermistor is covered on the substrate and is disposed in a second preset range of the preset chip and in a third preset range of the dc terminal.
Optionally, the plurality of copper clips includes two copper clips, each copper clip including a predetermined number of pins, each pin being respectively connected to a source region of one of the chips.
Optionally, a plurality of chips and a plurality of gate resistors are arranged in a symmetrical distribution over the substrate, the gate regions of each of the plurality of chips being connected.
Optionally, the semiconductor power module further includes a plurality of terminals including a dc terminal, an ac terminal, a source terminal, a gate terminal, and a drain terminal, the plurality of terminals being connected to the substrate, a source region of each chip being connected to the source terminal, and a gate region of each chip being connected to the gate terminal.
In order to achieve the above object, according to another aspect of the present application, there is provided a packaging apparatus of a semiconductor power module. The device comprises: a first sintering unit for sintering the top of the heat spreader and the bottom of the substrate by a silver sintering technique; a second sintering unit for sintering the drain region of the chip and the top of the substrate by a silver sintering technique; a third sintering unit for sintering the gate resistor and the thermistor with the top of the substrate by silver sintering technology; and the plastic packaging unit is used for carrying out plastic packaging treatment on the substrate, the chip, the grid resistor, the thermistor and the radiator to obtain the packaged semiconductor power module.
According to the application, the following steps are adopted: sintering the top of the radiator and the bottom of the substrate by a silver sintering technology; sintering the drain region of the chip and the top of the substrate by a silver sintering technology; sintering the grid resistor, the thermistor and the top of the substrate by a silver sintering technology; and the substrate, the chip, the grid resistor, the thermistor and the radiator are subjected to plastic packaging treatment to obtain the packaged semiconductor power module, so that the problem that a large cavity is formed between the radiator and the power module when the semiconductor power module is packaged in the related technology is solved. The substrate and the radiator are packaged by the silver sintering technology, so that the large cavity generated by solder paste during welding is effectively improved, the problem that the large cavity is formed between the radiator and the power module is avoided, the failure risk of the module is reduced, the height of the module is reduced on the basis of ensuring the creepage distance and the electric gap, the loss is reduced, and the radiating efficiency is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
fig. 1 is a flowchart of a packaging method of a semiconductor power module according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a semiconductor power module according to an embodiment of the present application;
fig. 3 is a front view of a heat sink 10 provided according to an embodiment of the present application;
fig. 4 is a side view of a heat sink 10 provided in accordance with an embodiment of the present application;
fig. 5 is a schematic view of a structure of a plurality of copper clips 50 provided according to an embodiment of the present application;
fig. 6 is a schematic diagram of a packaging apparatus for a semiconductor power module according to an embodiment of the present application.
The semiconductor device comprises a 10-radiator, a 20-substrate, a 30-chip, a 40-grid resistor, a 50-copper clamp and a 60-wafer, wherein the substrate is provided with a first electrode and a second electrode;
70-thermistor, 80-DC terminal, 90-AC terminal, 100-source terminal, 110-gate terminal;
120-drain terminal, 101-pin fin, 301-preset chip, 501-pin.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The present application is described below in connection with preferred implementation steps, and fig. 1 is a flowchart of a method for packaging a semiconductor power module according to an embodiment of the present application, as shown in fig. 1, and the method includes the following steps:
in step S101, the top of the heat spreader 10 and the bottom of the substrate 20 are sintered by a silver sintering technique.
Specifically, since a larger void occurs between the heat sink 10 and the power module when the semiconductor power module is formed by soldering, the bottom of the substrate 20 of the semiconductor power module and the top of the heat sink 10 are sintered by adjusting the packaging method and adopting a silver sintering technique instead of soldering.
It should be noted that, the silver sintering technology is also called as low temperature connection technology, the specific operation flow is that firstly, silver paste is printed, then, drying is carried out, the purpose of the silver paste is to volatilize organic components in silver particles, so that the final connection layer only remains pure silver, then, the surface mounting treatment is carried out, the silver paste is used for surface mounting of the part to be sintered, and finally, the part to be sintered is connected together through pressure sintering. Silver sintering technology has the following advantages: the sintering material has the basic components of silver particles, the sintering connecting layer is silver, and the sintering material has excellent electric conductivity and heat conductivity; the typical fatigue effect in the soldering connection layer with the melting point less than 300 ℃ is not generated due to the fact that the melting point of silver is as high as 961 ℃, the reliability is extremely high, and the service life and the power cycle capability of the semiconductor power module are greatly improved; the sintering temperature of the sintering material is similar to that of the traditional soft soldering; the sintered material does not contain lead, and belongs to an environment-friendly material.
The sintering materials used in the silver sintering technology have the basic components of silver particles, and can be classified into silver paste, silver film, silver powder and the like according to different states. Taking silver paste as an example, sintering of nano silver particles can be divided into an initial bonding stage, a sintering neck growing stage, a closed pore spheroidization stage and a shrinking stage. During sintering, silver particles form sintering necks through contact, silver atoms migrate to the sintering neck regions through diffusion, so that the sintering necks are continuously grown, the distance between adjacent silver particles is gradually reduced, and a continuous pore network is formed. As sintering proceeds, the original stable pores become smaller, and the continuous pores become isolated small pores, so that the density and strength of the sintered layer are remarkably increased. In the final stage of sintering, most holes are completely divided, small holes completely disappear, and the volume of large holes becomes smaller until the final density is reached. Thereby avoiding larger cavities between the radiator 10 and the power module, the connecting layer obtained by sintering is of a porous structure, the size of the holes is in the micron and submicron level, and the connecting layer has good heat conduction and electric conduction performance and good heat matching performance. Under the condition that the porosity of the connecting layer is 10%, the electric and heat conducting capacities of the connecting layer can reach 90% of pure silver, and the connecting layer is far higher than that of common soft soldering materials.
In step S102, the drain region of the die 30 and the top of the substrate 20 are sintered by a silver sintering technique.
Specifically, the chip 30 includes a source region as a pole from which a current of the chip 30 flows, a gate region as a pole from which a current of the chip 30 flows, and a drain region that is a switch that controls the chip 30 to be turned on and off. The drain region of the die 30 is sintered with the top of the substrate 20 by a silver sintering technique to place the die 30 in communication with the circuit structure of the semiconductor power module on the substrate 20.
In step S103, the gate resistor 40 and the thermistor 70 are sintered with the top of the substrate 20 by silver sintering technology.
Specifically, the gate resistor 40 is a resistor for increasing the impedance between the gate regions of the chip 30, improving the anti-interference capability of the chip 30, and further suppressing the gate oscillation phenomenon. The thermistor 70 is a resistor for measuring the temperature of the chip 30, and the gate resistor 40 and the thermistor 70 are sintered with the top of the substrate 20 by a silver sintering technique so that the gate resistor 40 and the thermistor 70 are communicated with the circuit structure of the semiconductor power module on the substrate 20.
It should be noted that the gate oscillation is caused by the existence of many resistors, capacitors and inductors in the circuit, and especially the combined action of the capacitors and inductors in the high-frequency alternating current. The gate resistor 40 is added to prevent the co-operation of the capacitor and the inductor, thereby suppressing the gate oscillation phenomenon.
In step S104, the substrate 20, the chip 30, the gate resistor 40, the thermistor 70 and the heat spreader 10 are subjected to plastic packaging, so as to obtain a packaged semiconductor power module.
Specifically, the semiconductor power module of each electronic component is molded by the black encapsulation material, and the pin fin 101 side of the heat spreader 10 is kept outside the plastic package.
According to the packaging method of the semiconductor power module, provided by the embodiment of the application, the top of the radiator 10 and the bottom of the substrate 20 are sintered through a silver sintering technology; sintering the drain region of the die 30 with the top of the substrate 20 by a silver sintering technique; sintering the gate resistor 40 and the thermistor 70 with the top of the substrate 20 by a silver sintering technique; the substrate 20, the chip 30, the grid resistor 40, the thermistor 70 and the radiator 10 are subjected to plastic packaging treatment to obtain a packaged semiconductor power module, so that the problem that a large cavity exists between the radiator 10 and the power module when the semiconductor power module is packaged in the related art is solved. The substrate 20 and the radiator 10 are packaged by the silver sintering technology, so that the large cavity generated by solder paste during welding is effectively improved, the large cavity between the radiator 10 and the power module is avoided, the failure risk of the module is reduced, the height of the module is reduced on the basis of ensuring the creepage distance and the electric gap, the loss is reduced, and the heat dissipation efficiency is improved.
In the method for packaging a semiconductor power module provided by the embodiment of the application, before the substrate 20, the chip 30, the gate resistor 40, the thermistor 70 and the heat sink 10 are subjected to plastic packaging, the method further includes: soldering the copper clip 50 on the substrate 20, and connecting the leads 501 of the copper clip 50 with the source regions of the die 30; the application frame terminals are connected to the substrate 20 by ultrasonic welding.
For example, the copper clip 50 may be two pieces of copper clip 50, each piece of copper clip 50 including eight leads 501, each lead 501 being connected to a source region of one of the chips 30. The terminals of the control chip 30 include a dc terminal 80, an ac terminal 90, a source terminal 100, a gate terminal 110 and a drain terminal 120, the source terminal 100 is connected to the source region of the chip 30, the gate terminal 110 is connected to the gate region of the chip 30, the drain terminal 120 is connected to the drain region of the chip 30, the copper clip 50 is soldered to the substrate 20 by soldering, the lead 501 of the copper clip 50 is burned to the source region of the chip 30 by silver sintering, the terminals of the control chip 30 are connected to the substrate 20 by ultrasonic soldering, and each control terminal is connected to the circuit structure on the substrate 20 by a wire.
It should be noted that, since the thickness of the copper clip 50 is 0.7mm-0.8mm far beyond the diameter (0.4-0.5 mm) of the conventional bonding wire, and the contact area between the copper clip 50 and the chip 30 is at least 5 times that of the bonding wire, the current carrying capacity of the copper clip 50 far exceeds that of the bonding wire, and less heat is generated. But also the parasitic parameters (stray inductances) caused by the copper clip 50 being flatter relative to the bond wire will be somewhat reduced. The copper clip 50 has a larger cross-sectional area and generates less heat when current is conducted. And meanwhile, the reliability is better.
Optionally, in the packaging method of the semiconductor power module provided in the embodiment of the present application, performing plastic packaging processing on the substrate 20, the chip 30, the gate resistor 40, the thermistor 70 and the heat spreader 10 includes: determining the thickness and width of an unpackaged semiconductor power module; judging whether the thickness is in the thickness range or not, and judging whether the width is in the width range or not; and under the condition that the thickness is in the thickness range and the width is in the width range, carrying out plastic packaging treatment on the non-plastic packaged semiconductor power module through the target plastic packaging material.
Specifically, the unpackaged semiconductor power module is limited to a preset thickness range and a preset width range. On the premise of ensuring creepage and electric clearance of the semiconductor power module, the electronic components of the semiconductor power module are connected in a silver sintering mode, and the connection performance and reliability between the semiconductor power module and the radiator 10 can be improved without increasing the width and thickness of the semiconductor power module.
Optionally, in the packaging method of the semiconductor power module provided in the embodiment of the present application, before the plastic packaging process is performed on the substrate 20, the chip 30, the gate resistor 40, the thermistor 70 and the heat spreader 10, the method further includes: the chip 30, the gate resistor 40 and the thermistor 70 are wire-bonded on the substrate 20 according to a predetermined circuit pattern.
Specifically, the wire bonding process refers to connecting the chip 30, the gate resistor 40 and the thermistor 70 in a solid-state circuit on the substrate 20 according to a preset circuit diagram of the semiconductor power module by using a hot press or ultrasonic energy source through wires (gold wires, aluminum wires, etc.).
According to another embodiment of the present application, a semiconductor power module is provided. Fig. 2 is a schematic structural diagram of a semiconductor power module according to an embodiment of the present application, as shown in fig. 2, including:
the radiator 10, there are pin fins below the radiator 10;
specifically, fig. 3 is a front view of a heat sink 10 provided according to an embodiment of the present application, and fig. 4 is a side view of the heat sink 10 provided according to an embodiment of the present application, as shown in fig. 3 and 4, a cylindrical pin fin 101 is disposed under the heat sink 10, and a semiconductor power module is transferred to a coolant through the heat sink with the pin fin 101 under. Thereby radiating, the radiator can be a pin fin radiating structure made of copper, and the structure has higher radiating efficiency compared with the traditional sheet structure.
A substrate 20, wherein the substrate 20 is a metal substrate, and the substrate 20 covers the radiator 10;
specifically, as shown in fig. 2, the substrate 20 may be a copper plate, and the chip 30, the gate resistor 40, the thermistor 70, and the plurality of terminals of the semiconductor power module are connected to each other through the substrate 20.
A plurality of chips 30 disposed over the substrate 20, each chip 30 including a source region, a gate region, and a drain region, the drain region of each chip 30 being connected to the substrate 20;
specifically, as shown in fig. 2, the plurality of chips 30 may be sixteen chips 30, where sixteen chips 30 are arranged above the substrate 30 in a laterally symmetrical manner, and a lower surface of each chip 30, that is, a surface contacting the substrate 20, is a drain region, and an upper surface of each chip 30 includes a source region and a gate region. The chip can be an IGBT or MOSFET type chip, the source electrode area is used as one electrode of the current flowing out of the chip, the grid electrode area is used as one electrode of the current flowing in of the chip, and the grid electrode area is a switch for controlling the on and off of the chip.
A plurality of gate resistors 40 disposed over the substrate 20, each gate resistor 40 being disposed within a first predetermined range of one of the chips 30 and being connected to a gate region of the chip 30;
specifically, as shown in fig. 2, the number of gate resistors 40 may be the same as the number of chips 30, one gate resistor 40 is disposed within a first preset range of each chip 30, and the gate region of each chip 30 is connected to the gate resistor 40 within the first preset range through an aluminum wire. By disposing the gate resistor 40 beside each chip 30, the impedance between the gate regions of different chips 30 can be increased, so as to improve the anti-interference capability of each chip 30 and further inhibit the gate oscillation phenomenon. The first preset range may be within 2mm of the chip 30.
A plurality of copper clips 50 disposed over the substrate 20 and connected to the source regions of the chips 30;
specifically, fig. 5 is a schematic structural diagram of a plurality of copper clips 50 provided according to an embodiment of the present application, as shown in fig. 5, the plurality of copper clips 50 may be two copper clips, each copper clip includes eight pins 501, and each pin 501 is connected to a source region of one chip 30.
The wafer 60 is disposed above the substrate 20 and is connected to the substrate 20.
Specifically, the wafer 60 is a silicon wafer on the substrate 20 that builds a predetermined circuit structure.
In the semiconductor power module provided by the embodiment of the application, the semiconductor power module further includes a thermistor 70, where the thermistor 70 is covered on the substrate 20 and is disposed within a second preset range of the preset chip 301 and a third preset range of the dc terminal 80.
Specifically, the closer the thermistor 70 is to the chip 30, the more accurate the measurement of the junction temperature of the chip 30 is, and the less delay is incurred by the distance transfer effect. The second preset range may be a distance from the preset chip 301 within a range of 5 mm. By arranging the thermistor 70 at a position closer to the preset chip 301, the temperature of the chip 30 can be measured more accurately, and the time delay in temperature measurement is shorter, so that the temperature measurement efficiency is higher. The third preset range may be to set the thermistor 70 within a distance of 2mm from the dc terminal 80. Since the thermistor 70 is disposed near the ac terminal 90 with a more serious disturbance, the thermistor 70 is disposed near the dc terminal 80.
The principle of using the thermistor is to collect voltages at two ends of the resistor and convert the voltages into corresponding temperatures. If the voltage is not obtained, the temperature measurement is not accurate. Because the thermistor is too close to the alternating current terminal and is easy to receive electromagnetic interference, voltage test is deviated, and the thermistor is adjusted from one end close to the alternating current terminal to one end close to the direct current terminal.
Optionally, in the semiconductor power module provided in the embodiment of the present application, the plurality of copper clips 50 includes two copper clips 50, each copper clip 50 includes a predetermined number of pins 501, and each pin 501 is connected to a source region of one chip 30.
Specifically, as shown in fig. 5, the plurality of copper clips 50 may be two copper clips, each including eight leads 501, and each lead 501 is connected to the source region of one chip 30.
It should be noted that, since the thickness of the copper clip 50 is 0.7mm-0.8mm far beyond the diameter (0.4-0.5 mm) of the conventional bonding wire, and the contact area between the copper clip 50 and the chip 30 is at least 5 times that of the bonding wire, the current carrying capacity of the copper clip 50 far exceeds that of the bonding wire, and less heat is generated. But also the parasitic parameters (stray inductances) caused by the copper clip 50 being flatter relative to the bond wire will be somewhat reduced. The cross section area of the copper clamp is larger, and the heating is smaller when the current is conducted. And meanwhile, the reliability is better.
Optionally, in the semiconductor power module provided in the embodiment of the present application, the plurality of chips 30 and the plurality of gate resistors 40 are arranged above the substrate 20 in a symmetrical distribution manner, and gate regions of the respective chips 30 in the plurality of chips 30 are connected.
Specifically, as shown in fig. 2, eight chips 30 of sixteen chips 30 are disposed on the left side of the substrate 20, and the other eight chips 30 are disposed on the right side of the substrate 20, the eight chips 30 on the left side having a substantially completely symmetrical layout with the eight chips 30 on the right side. In each eight chips 30 connected in parallel, four chips 30 are taken as a group to be divided into a left group and a right group, and the parasitic parameter difference of each chip caused by packaging is very small. By the bilateral symmetry layout, all the parallel chips 30 are made more compact, and the electrical performance and heat dissipation capacity of the semiconductor power module are improved. Each gate resistor 40 is disposed within a first predetermined range of the chip 30, and the gate resistors 40 are also disposed on the substrate 20 in a symmetrical layout in order to improve the electrical performance and heat dissipation capability of the semiconductor power module. The gate regions of each of sixteen chips 30 are connected to each other by aluminum wires, the source regions of each of the chips 30 are connected to each other by copper clips 50, and the drain regions of each of the chips 30 are connected to each other by the substrate 20, so that each of the chips 30 is connected in parallel within the semiconductor power module.
Optionally, in the semiconductor power module provided in the embodiment of the present application, the semiconductor power module further includes a plurality of terminals including a dc terminal 80, an ac terminal 90, a source terminal 100, a gate terminal 110 and a drain terminal 120, the plurality of terminals being connected to the substrate 20, a source region of each chip 30 being connected to the source terminal 100, and a gate region of each chip 30 being connected to the gate terminal 110.
Specifically, the semiconductor power module further includes a plurality of control terminals, the various functions of which are implemented through different control terminals, including a direct current terminal 80, an alternating current terminal 90, a source terminal 100, a gate terminal 110, and a drain terminal 120. The control terminals are respectively connected to the substrates 20 so as to be connected to the respective chips 30. The source region of each chip 30 is connected to the source terminal 100 through an aluminum line, and the gate region of each chip 30 is connected to the gate terminal 110 through an aluminum line. The drain region of each chip 30 is connected to a drain terminal 120 through a substrate 20.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
The embodiment of the application also provides a packaging device of the semiconductor power module, and the packaging device of the semiconductor power module can be used for executing the packaging method for the semiconductor power module. The following describes a packaging device of a semiconductor power module provided by an embodiment of the present application.
Fig. 6 is a schematic view of a packaging apparatus of a semiconductor power module according to an embodiment of the present application. As shown in fig. 6, the apparatus includes:
a first sintering unit 601 for sintering the top of the heat spreader and the bottom of the substrate by a silver sintering technique;
a second sintering unit 602 for sintering the drain region of the chip and the top of the substrate by a silver sintering technique;
a third sintering unit 603 for sintering the gate resistor and the thermistor with the top of the substrate by a silver sintering technique;
and the plastic packaging unit 604 is used for carrying out plastic packaging treatment on the substrate, the chip, the grid resistor, the thermistor and the radiator to obtain the packaged semiconductor power module.
According to the packaging device of the semiconductor power module, provided by the embodiment of the application, the top of the radiator and the bottom of the substrate are sintered through the first sintering unit 601; a second sintering unit 602 for sintering the drain region of the chip and the top of the substrate by a silver sintering technique; a third sintering unit 603 for sintering the gate resistor and the thermistor with the top of the substrate by a silver sintering technique; the plastic packaging unit 604 is used for carrying out plastic packaging treatment on a substrate, a chip, a grid resistor, a thermistor and a radiator to obtain a packaged semiconductor power module, solves the problem that a large cavity appears between the radiator and the power module when the semiconductor power module is packaged in the related art, effectively improves the large cavity generated by solder paste during welding by silver sintering technology, further achieves the effects of avoiding the large cavity between the radiator and the power module, reducing the failure risk of the module, reducing the height of the module on the basis of ensuring the creepage distance and the electric gap, reducing the loss and improving the heat dissipation efficiency.
Optionally, in the packaging device of a semiconductor power module provided by the embodiment of the present application, the device further includes: the first connecting unit is used for welding the copper clamp on the substrate and connecting pins of the copper clamp with the source electrode area of the chip; and the second connecting unit is used for connecting the application frame terminal with the substrate in an ultrasonic welding mode.
Optionally, in the packaging apparatus for a semiconductor power module provided in the embodiment of the present application, the plastic packaging unit 604 includes: the determining module is used for determining the thickness and the width of the non-plastic packaged semiconductor power module; the judging module is used for judging whether the thickness is in the thickness range and judging whether the width is in the width range; and the plastic packaging module is used for carrying out plastic packaging treatment on the non-plastic packaged semiconductor power module through the target plastic packaging material under the condition that the thickness is in the thickness range and the width is in the width range.
Optionally, in the packaging device of a semiconductor power module provided by the embodiment of the present application, the device further includes: and the wire bonding unit is used for performing wire bonding treatment on the chip, the grid resistor and the thermistor on the substrate according to a preset circuit diagram.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (11)
1. A method of packaging a semiconductor power module, comprising:
sintering the top of the radiator (10) and the bottom of the substrate (20) by a silver sintering technology;
sintering the drain region of the die (30) with the top of the substrate (20) by silver sintering techniques;
sintering the gate resistor (40) and the thermistor (70) with the top of the substrate (20) by silver sintering technology;
and carrying out plastic packaging treatment on the substrate (20), the chip (30), the grid resistor (40), the thermistor (70) and the radiator (10) to obtain the packaged semiconductor power module.
2. The method of claim 1, wherein prior to subjecting the substrate (20), the chip (30), the gate resistor (40), the thermistor (70), and the heat sink (10) to a plastic molding process, the method further comprises:
soldering a copper clip (50) on the substrate (20) and connecting pins of the copper clip (50) with source regions of the chip (30);
the application frame terminals are connected to the substrate (20) by means of ultrasonic welding.
3. The method of claim 1, wherein the plastic packaging of the substrate (20), the chip (30), the gate resistor (40), the thermistor (70), and the heat sink (10) comprises:
determining the thickness and width of an unpackaged semiconductor power module;
judging whether the thickness is in a thickness range or not, and judging whether the width is in a width range or not;
and under the condition that the thickness is in the thickness range and the width is in the width range, carrying out plastic packaging treatment on the non-plastic packaged semiconductor power module through a target plastic packaging material.
4. The method of claim 1, wherein prior to subjecting the substrate (20), the chip (30), the gate resistor (40), the thermistor (70), and the heat sink (10) to a plastic molding process, the method further comprises: and carrying out wire bonding treatment on the chip (30), the grid resistor (40) and the thermistor (70) on the substrate (20) according to a preset circuit diagram.
5. A semiconductor power module, comprising:
a radiator (10), wherein needle fins are arranged below the radiator (10);
-a substrate (20), the substrate (20) being covered over the heat sink (10), wherein the substrate (20) is a metal substrate;
a plurality of chips (30) disposed over the substrate (20), each chip (30) including a source region, a gate region, and a drain region, the drain region of each chip (30) being connected to the substrate (20);
a plurality of gate resistors (40) disposed over the substrate (20), each gate resistor (40) being disposed within a first predetermined range of one chip (30) and being connected to a gate region of the chip (30);
a plurality of copper clips (50) disposed over the substrate (20) and connected to source regions of the die (30);
and a wafer (60) disposed above the substrate (20) and connected to the substrate (20).
6. The semiconductor power module according to claim 5, further comprising a thermistor (70), the thermistor (70) being overlaid on the substrate (20) and being arranged within a second preset range of a preset chip (301) and within a third preset range of a dc terminal (80).
7. The semiconductor power module of claim 5, wherein the plurality of copper clips (50) comprises two copper clips (50), each copper clip (50) comprising a predetermined number of pins (501), each pin (501) being connected to the source region of one die (30).
8. The semiconductor power module of claim 5, wherein the plurality of chips (30) and the plurality of gate resistors (40) are arranged in a symmetrically distributed manner over the substrate (20), the gate regions of each chip (30) of the plurality of chips (30) being connected.
9. The semiconductor power module of claim 5, further comprising a plurality of terminals including a dc terminal (80), an ac terminal (90), a source terminal (100), a gate terminal (110), and a drain terminal (120), the plurality of terminals being connected to the substrate (20), the source region of each chip (30) being connected to the source terminal (100), the gate region of each chip (30) being connected to the gate terminal (110).
10. A processor, characterized in that the processor is configured to run a program, wherein the program when run performs the method of packaging a semiconductor power module according to any of claims 1 to 4.
11. An electronic device comprising one or more processors and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of packaging a semiconductor power module of any of claims 1-4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310226022.9A CN116581034A (en) | 2023-03-09 | 2023-03-09 | Packaging method of semiconductor power module, semiconductor power module and processor |
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| CN202310226022.9A CN116581034A (en) | 2023-03-09 | 2023-03-09 | Packaging method of semiconductor power module, semiconductor power module and processor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117577610A (en) * | 2024-01-17 | 2024-02-20 | 中国第一汽车股份有限公司 | Power module and signal processing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117577610A (en) * | 2024-01-17 | 2024-02-20 | 中国第一汽车股份有限公司 | Power module and signal processing method |
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