CN116565034A - Back contact battery and preparation method thereof - Google Patents

Back contact battery and preparation method thereof Download PDF

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Publication number
CN116565034A
CN116565034A CN202310459560.2A CN202310459560A CN116565034A CN 116565034 A CN116565034 A CN 116565034A CN 202310459560 A CN202310459560 A CN 202310459560A CN 116565034 A CN116565034 A CN 116565034A
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layer
passivation
film
region
type
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曹建伟
王树林
李鹏飞
王英杰
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Zhejiang Jingsheng Photonics Technology Co ltd
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Zhejiang Qiushi Semiconductor Equipment Co Ltd
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
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Abstract

The invention provides a back contact battery and a preparation method thereof. In the back contact battery, a first passivation contact structure is positioned in an N-type region, a second passivation contact structure is positioned in a P-type region, and the first passivation contact structure and the second passivation contact structure are not overlapped in a transverse direction; while the presence of the insulating layer may in turn space apart the first and second passivation contact structures in the longitudinal direction; the insulating layer and the insulating anti-reflection layer are connected with each other to form an L-shaped structure, and the joint of the insulating layer and the insulating anti-reflection layer can effectively separate the first passivation contact structure from the second passivation contact structure, so that the triple effects effectively avoid direct contact of PN junctions and effectively reduce the risk of electric leakage; in addition, the existence of the isolation groove also avoids the direct contact between the first TCO layer and the second passivation contact structure, and can effectively reduce the risk of electric leakage; in addition, the back contact battery also has excellent conversion efficiency.

Description

Back contact battery and preparation method thereof
Technical Field
The invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to a back contact cell and a preparation method thereof.
Background
The conversion efficiency of the crystalline silicon solar cell is higher and higher as the BSF and PERC are developed to PERC+ through continuous iterative upgrade of technology, the current PERC+ mass production efficiency reaches about 23.45%, the theoretical limit efficiency is already close to 24.5%, the subsequent efficiency lifting difficulty is increased, and the lifting space is limited. TOPCon cells, HJT cells, back contact cells, etc. have now become new trends in crystalline silicon solar cells, and are the leading edge for international research and industrialization today.
The back contact cell is a crystalline silicon solar cell with an emitter electrode and a base electrode of the cell both positioned on the back of the cell. The back contact battery has no shielding of a metal grid line electrode on the front surface, so that the light absorption efficiency is increased, and the short-circuit current is greatly improved; meanwhile, the back contact battery adopts amorphous silicon or microcrystalline silicon and the doping mode thereof to passivate the surface of the battery, so that the open-circuit voltage is improved, the conversion efficiency of the back contact battery is effectively increased by the factors, and the back contact battery has good development prospect.
But the back contact battery still has the following problems: (1) The back contact battery is characterized in that the whole PN junction is concentrated on the back surface, the doped semiconductor layer of the P region and the doped semiconductor layer of the N region are easy to contact each other, so that the electric leakage problem can be generated, in the related art, only a laser etching method is adopted to open a slot between the P region and the N region, and the two doped semiconductor layers with opposite conductivity types are isolated, so that the electric leakage problem can not be completely solved; (2) In the back contact battery in the related art, the metal gate line electrode is directly contacted with the silicon substrate, so that the contact resistance of a contact area of the metal gate line electrode is increased, meanwhile, the carrier recombination of the contact area is serious, and the improvement of the conversion efficiency of the battery is limited; (3) The back of the back contact battery in the related art is only passivated by an antireflection film, so that the passivation effect is limited, and the conversion efficiency of the battery cannot be effectively improved.
Therefore, the research on the back contact battery in the related art is insufficient, and deep research is needed, so that the back contact battery and the preparation method thereof are designed, and the conversion efficiency can be effectively improved while the problem of electric leakage is solved.
Disclosure of Invention
The present invention has been made based on the findings and knowledge of the inventors regarding the following facts and problems: the back contact battery in the related art has the problem of electric leakage, the conversion efficiency cannot be further improved, further improvement is needed, and the back contact battery and the preparation method thereof are designed, so that the conversion efficiency can be effectively improved while the problem of electric leakage is solved.
The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, embodiments of the present invention provide a back contact battery and a method of manufacturing the same.
The embodiment of the invention provides a back contact battery, which comprises: the back surface of the silicon substrate comprises N-type regions and P-type regions which are adjacently and alternately arranged; the N-type region is provided with a first passivation contact structure, the first passivation contact structure comprises a first passivation layer and an N-type doped semiconductor layer which are sequentially stacked, a first TCO layer is arranged in a partial region of the surface of the N-type doped semiconductor layer, and an insulating anti-reflection layer is arranged in the rest region of the surface of the N-type doped semiconductor layer; the P-type region is provided with a second passivation contact structure, the second passivation contact structure comprises a second passivation layer and a P-type doped semiconductor layer which are sequentially stacked, and a second TCO layer is arranged on the surface of the P-type doped semiconductor layer; an insulating layer is longitudinally arranged at the junction position of the P-type region and the N-type region, and the insulating layer and the insulating anti-reflection layer are connected with each other to separate the first passivation contact structure from the second passivation contact structure; an isolation groove is arranged among the first TCO layer, the insulating anti-reflection layer, the insulating layer, the second passivation contact structure and the second TCO layer; the first TCO layer surface is provided with a first metal gate line electrode, and the second TCO layer surface is provided with a second metal gate line electrode.
The back contact battery provided by the embodiment of the invention has the following advantages and technical effects:
(1) In the back contact battery provided by the embodiment of the invention, the first passivation contact structure is positioned in the N-type region, the second passivation contact structure is positioned in the P-type region, and the first passivation contact structure and the second passivation contact structure are not overlapped in a staggered manner in the transverse direction, so that the direct contact of PN junctions is avoided, and the risk of electric leakage is greatly reduced;
(2) In the back contact battery provided by the embodiment of the invention, the first passivation contact structure and the second passivation contact structure are separated by the insulating layer in the longitudinal direction, so that the direct contact of PN junctions is further avoided, and the electric leakage condition of the battery is effectively improved;
(3) In the back contact battery provided by the embodiment of the invention, the insulating layer and the insulating anti-reflection layer are connected with each other, and the first passivation contact structure and the second passivation contact structure can be effectively blocked at the joint of the insulating layer and the insulating anti-reflection layer, so that the first passivation contact structure and the second passivation contact structure are effectively separated, the direct contact of PN junctions is further avoided, and the electric leakage condition of the battery is effectively improved;
(4) In the back contact battery provided by the embodiment of the invention, the existence of the isolation groove also avoids the direct contact between the first TCO layer and the second passivation contact structure, so that the electric leakage condition of the battery is effectively improved;
(5) In the back contact battery provided by the embodiment of the invention, the first passivation contact structure and the second passivation contact structure have excellent passivation effect on the silicon substrate, and meanwhile, the insulating anti-reflection layer also has passivation effect, so that the open circuit voltage of the battery can be obviously improved, and the conversion efficiency of the battery is further improved;
(6) In the back contact battery provided by the embodiment of the invention, the efficiency of refracting light into the silicon substrate can be improved through the antireflection effect of the first TCO layer, the insulating antireflection layer and the second TCO layer, so that the conversion efficiency of the battery can be improved;
(7) In the back contact battery provided by the embodiment of the invention, the first passivation contact structure prevents the first metal gate line electrode from being in direct contact with the silicon substrate, and the second passivation contact structure prevents the second metal gate line electrode from being in direct contact with the silicon substrate, so that the metal contact resistance can be effectively reduced, and the battery efficiency is further improved.
In some embodiments, the first passivation layer is silicon oxide and the N-doped semiconductor layer is N-doped polysilicon; the second passivation layer adopts intrinsic hydrogenated amorphous silicon and/or intrinsic hydrogenated microcrystalline silicon, and the P-type doped semiconductor layer adopts P-type doped hydrogenated amorphous silicon and/or P-type doped hydrogenated microcrystalline silicon.
In some embodiments, the insulating anti-reflective layer is silicon nitride.
In some embodiments, the thickness of the insulating anti-reflective layer is 60-110nm.
In some embodiments, the insulating layer is silicon oxide.
In some embodiments, the insulating layer has a width of
In some embodiments, the front surface of the silicon substrate is sequentially laminated with a front surface passivation film and a front surface antireflection film.
In some embodiments, where the back contact cell is an N-type cell, the width of the P-type region is greater than the width of the N-type region; or, in the case that the back contact battery is a P-type battery, the width of the P-type region is smaller than the width of the N-type region.
The embodiment of the invention also provides a preparation method of the back contact battery, which comprises the following steps:
(1) Cleaning the silicon substrate;
(2) Preparing a first passivation film on the back surface of the silicon substrate;
(3) Preparing an N-type doped semiconductor precursor on the surface of the first passivation film;
(4) Preparing an insulating anti-reflection film on the surface of the N-type doped semiconductor precursor;
(5) Removing the insulating anti-reflection film in the P-type region by a laser grooving method;
(6) Removing the N-type doped semiconductor precursor in the P-type region by adopting a chemical etching method to form a P-region slot;
(7) Annealing the silicon substrate to enable the inner side face of the groove of the P region to grow an insulating film, and simultaneously converting the N-type doped semiconductor precursor in the N-type region into an N-type doped semiconductor layer;
(8) Removing the first passivation film in other areas in the grooves of the P area by adopting a laser etching method under the condition that the insulating film and the first passivation film in the area longitudinally corresponding to the insulating film are reserved, so as to obtain the insulating layer and the first passivation layer;
(9) Preparing a second passivation film on the back surface of the silicon substrate; preparing a P-type doped semiconductor film on the surface of the second passivation film;
(10) Removing the second passivation film and the P-type doped semiconductor film in a partial region of the N-type region by adopting a laser etching method to form an N-region slot;
(11) Removing the insulating anti-reflection film in the N region slot by adopting a chemical etching method to obtain the insulating anti-reflection layer;
(12) Preparing a TCO film on the back surface of the silicon substrate;
(13) Removing the TCO film and the second passivation contact structure between the N region groove and the P type region by adopting a laser etching method to form the isolation groove, the first TCO layer and the second TCO layer;
(14) And preparing the first metal gate line electrode on the surface of the first TCO layer in the n-region slot, and preparing the second metal gate line electrode on the surface of the second TCO layer in the p-region slot to obtain the back contact battery.
The preparation method of the back contact battery provided by the embodiment of the invention has the following advantages and technical effects:
(1) The preparation method provided by the embodiment of the invention has reasonable step arrangement, is simple and easy to operate, and is suitable for mass production popularization;
(2) The preparation method provided by the embodiment of the invention not only can solve the problem of electric leakage of the back contact battery, but also can effectively improve the conversion efficiency of the battery.
In some embodiments, in step (1), a texture is prepared on the back and/or front side of the silicon substrate before the cleaning process is performed.
In some embodiments, in step (2), the front passivation film is simultaneously prepared on the front side of the silicon substrate; and/or, in the step (4), preparing the front-side antireflection film on the front side of the silicon substrate at the same time.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 7 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 9 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 10 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 11 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 12 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 13 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
fig. 14 is a schematic flow chart of a method for manufacturing a back contact battery according to an embodiment of the present invention;
reference numerals illustrate:
1-a silicon substrate; a 2-N type region; a 3-P type region; 4-a first passivation layer; a 5-N type doped semiconductor layer; 6-a first TCO layer; 7-an insulating anti-reflection layer; 8-a second passivation layer; a 9-P type doped semiconductor layer; 10-a second TCO layer; 11-an insulating layer; 12-isolation grooves; 13-a first metal gate line electrode; 14-a second metal gate line electrode; 15-front passivation film; 16-front side antireflection film; 17-a first passivation film; an 18-N doped semiconductor precursor; 19-an insulating antireflection film; slotting in a 20-P region; 21-an insulating film; 22-a second passivation film; a 23-P type doped semiconductor film; slotting in a 24-N region; 25-TCO film; 26-suede.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
An embodiment of the present invention provides a back contact battery, as shown in fig. 14, including: a silicon substrate 1, the back surface of the silicon substrate 1 comprises N-type regions 2 and P-type regions 3 which are adjacently and alternately arranged; the N-type region 2 is provided with a first passivation contact structure, the first passivation contact structure comprises a first passivation layer 4 and an N-type doped semiconductor layer 5,N which are sequentially stacked, a first TCO layer 6 is arranged in a partial region of the surface of the N-type doped semiconductor layer 5, and an insulating anti-reflection layer 7 is arranged in the rest region of the surface of the N-type doped semiconductor layer 5; the P-type region 3 is provided with a second passivation contact structure, the second passivation contact structure comprises a second passivation layer 8 and a P-type doped semiconductor layer 9,P which are sequentially stacked, and a second TCO layer 10 is arranged on the surface of the P-type doped semiconductor layer 9; an insulating layer 11 is longitudinally arranged at the junction position between the P-type region 3 and the N-type region 2, and the insulating layer 11 and the insulating anti-reflection layer 7 are connected with each other to separate the first passivation contact structure from the second passivation contact structure; an isolation groove 12 is arranged among the first TCO layer 6, the insulating anti-reflection layer 7, the insulating layer 11, the second passivation contact structure and the second TCO layer 10; the first TCO layer 6 is provided with a first metal gate electrode 13 on its surface and the second TCO layer 10 is provided with a second metal gate electrode 14 on its surface.
In the back contact battery provided by the embodiment of the invention, the first passivation contact structure is positioned in the N-type region, the second passivation contact structure is positioned in the P-type region, and the first passivation contact structure and the second passivation contact structure are not overlapped in a staggered manner in the transverse direction; at the same time, the presence of the insulating layer may in turn space apart the first and second passivation contact structures in the longitudinal direction; in addition, the insulating layer and the insulating anti-reflection layer are connected with each other to form an L-shaped structure, and the joint of the insulating layer and the insulating anti-reflection layer can effectively separate the first passivation contact structure from the second passivation contact structure, so that the triple effects effectively avoid direct contact of PN junctions and effectively reduce the risk of electric leakage; in addition, the existence of the isolation groove also avoids the direct contact between the first TCO layer and the second passivation contact structure, and the risk of electric leakage can be effectively reduced.
According to the back contact battery provided by the embodiment of the invention, through the combined action of the insulating layer 11, the insulating anti-reflection layer 7 and the isolation groove 12, carriers in the N-type doped semiconductor layer 5 are prevented from entering the P-type doped semiconductor layer 9 through the second passivation layer 8 by tunneling effect, and meanwhile, carriers in the P-type doped semiconductor layer 9 can be prevented from entering the N-type doped semiconductor layer 5 through the first passivation layer 4 by tunneling effect, that is, the carriers collected by the N-type doped semiconductor layer 5 and the carriers collected by the P-type doped semiconductor layer 9 with opposite conductivity types can be prevented from being compounded, so that electric leakage is prevented from being generated at a transverse interface and a longitudinal interface of the N-type doped semiconductor layer 5 and the P-type doped semiconductor layer 9.
In the back contact battery provided by the embodiment of the invention, the first passivation contact structure and the heterojunction passivation contact structure have excellent passivation effect on the silicon substrate, and meanwhile, the insulating anti-reflection layer also has passivation effect, so that the open-circuit voltage of the battery can be improved, and the conversion efficiency of the battery is further improved. In addition, through the antireflection effect of the first TCO layer, the insulating antireflection layer and the second TCO layer, the efficiency of light refraction into the silicon substrate can be improved, and the conversion efficiency of the battery can be improved. In addition, the existence of the first passivation contact structure avoids the direct contact between the first metal gate line electrode and the silicon substrate, and the existence of the second passivation contact structure avoids the direct contact between the second metal gate line electrode and the silicon substrate, so that the metal contact resistance can be effectively reduced, and the conversion efficiency of the battery is further improved.
The back contact battery of the embodiment of the invention can be designed into an N-type battery structure or a P-type battery structure, and the conductivity type of the silicon substrate and the widths of the P-type region and the N-type region can be selected according to the actual design type of the battery. For example, in the case where the back contact cell is an N-type cell, the silicon substrate is selected to be an N-type silicon wafer, and the width of the P-type region is larger than the width of the N-type region. On the contrary, when the back contact battery is a P-type battery, the silicon substrate is a P-type silicon wafer, and the width of the P-type region is smaller than that of the N-type region. Preferably, the back contact battery is an N-type battery, and the conversion efficiency of the N-type battery is higher than that of the P-type battery.
In the back contact battery of the embodiment of the present invention, the silicon substrate 1 may have a polished front surface and/or a polished back surface, or may have a textured front surface and/or a textured back surface. Preferably, the front and/or back of the silicon substrate 1 is textured, because the textured has a better light trapping effect and a larger specific surface area than the polished surface, which is advantageous for improving the conversion efficiency of the back contact cell.
In some embodiments, the first passivation layer 4 may be silicon oxide (tunnel oxide), and the N-type doped semiconductor layer may be doped polysilicon.
In some embodiments, the second passivation layer 8 may employ at least one of intrinsic amorphous silicon, intrinsic microcrystalline silicon, intrinsic hydrogenated amorphous silicon, and intrinsic hydrogenated microcrystalline silicon, and the P-type doped semiconductor layer 9 may employ at least one of doped amorphous silicon layer, doped microcrystalline silicon, doped hydrogenated amorphous silicon, and doped hydrogenated microcrystalline silicon. Preferably, the second passivation layer 8 is intrinsic hydrogenated amorphous silicon and/or intrinsic hydrogenated microcrystalline silicon, and the P-type doped semiconductor layer 9 is doped hydrogenated amorphous silicon and/or doped hydrogenated microcrystalline silicon, because hydrogen ions can passivate dangling bonds in the crystalline silicon material, which helps to reduce the carrier recombination rate at the interface of the silicon substrate and the second passivation layer, thereby improving the conversion efficiency of the battery.
The back contact battery according to the embodiment of the present invention is not particularly limited in the type of insulating material used for the insulating layer 11, and any material having insulating properties may be used as long as it can perform an insulating function, and for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like may be used.
The insulating layer 11 may be a single-layer insulating structure made of one or more insulating materials, or a multi-layer insulating structure made of a plurality of insulating materials. In order to reduce the cost and increase the efficiency, only a single-layer insulating structure is arranged.
In addition, the thickness of the insulating layer 11 and the width of the insulating layer 11 may be set according to actual needs as long as the insulating layer 11 can be made to space the first passivation contact structure and the second passivation contact structure from each other in the longitudinal direction. For example, the insulating layer 11 has a width ofThe insulating layer can be effectively ensured to have good insulating property. When the width of the insulating layer 11 is too small, carriers easily pass through; when the width of the insulating layer 11 is too large, the insulating property of the insulating layer 11 is not further improved, which is disadvantageous in cost reduction and efficiency improvement.
In the back contact cell of the embodiment of the invention, the first TCO layer 6 and the second TCO layer 10 are both transparent conductive oxides, have light transmittance, are favorable for refracting light into a silicon substrate, and improve the utilization rate of the light, thereby improving the conversion efficiency of the cell. However, since the first TCO layer 6 and the second TCO layer 10 have conductivity, they cannot be connected to each other, and the first TCO layer 6 and the second passivation contact structure cannot be brought into contact, but the isolation groove 12 needs to be provided for spacing, otherwise a short circuit problem occurs.
In the back contact cell of the embodiment of the invention, a first TCO layer 6 is arranged in a partial area of the surface of the N-type doped semiconductor layer 5, and an insulating anti-reflection layer 7 is arranged in the remaining area of the surface of the N-type doped semiconductor layer 5. The insulating anti-reflection layer 7 is made of insulating materials, and is used for preventing the first passivation contact structure from contacting with the second passivation contact structure in the transverse direction, so that electric leakage is prevented; meanwhile, the reflection reducing effect is achieved, the light utilization rate is improved, and the conversion efficiency of the battery is improved. Preferably, the insulating anti-reflection layer 7 may be made of silicon nitride and/or silicon oxynitride.
In some embodiments, the front surface of the silicon substrate 1 is sequentially provided with the front surface passivation film 15 and the front surface antireflection film 16 in a stacked manner, so that the front surface of the silicon substrate 1 can be passivated, the recombination rate of carriers at the front surface is reduced, and the conversion efficiency of the battery is further improved. In addition, the front antireflection film 16 can also play a role in antireflection, which is beneficial to improving the utilization rate of light rays and further improving the conversion efficiency of the battery.
In some embodiments, the front passivation film 15 may employ silicon oxide and/or aluminum oxide, or the like. The front side antireflection film 16 may be silicon nitride.
The embodiment of the invention also provides a preparation method of the back contact battery, as shown in figures 1-14, comprising the following steps:
(1) Cleaning the silicon substrate 1;
(2) Preparing a first passivation film 17 on the back surface of the silicon substrate 1;
(3) Preparing an N-type doped semiconductor precursor 18 on the surface of the first passivation film 17;
(4) Preparing an insulating anti-reflection film 19 on the surface of the N-type doped semiconductor precursor 18;
(5) Removing the insulating anti-reflection film 19 in the P-type region 3 by a laser grooving method;
(6) Removing the N-type doped semiconductor precursor 18 in the P-type region 3 by adopting a chemical etching method to form a P-region slot 20;
(7) Annealing the silicon substrate 1 to grow an insulating film 21 on the inner side surface of the P-region trench 20, and simultaneously converting the N-type doped semiconductor precursor 18 in the N-type region 2 into the N-type doped semiconductor layer 5;
(8) Under the condition that the insulating film 21 and the first passivation film 17 in the area longitudinally corresponding to the insulating film 21 are reserved, removing the first passivation film 17 in other areas in the grooves 20 of the P area by adopting a laser etching method to obtain the insulating layer 11 and the first passivation layer 4; the insulating film 21 and the first passivation film 17 in the region corresponding to the longitudinal direction of the insulating film 21 together constitute the insulating layer 11.
(9) Preparing a second passivation film 22 on the back surface of the silicon substrate 1; preparing a P-type doped semiconductor film 23 on the surface of the second passivation film 22;
(10) Removing the second passivation film 22 and the P-type doped semiconductor film 23 in a part of the N-type region 2 by adopting a laser etching method to form an N-region slot 24;
(11) Removing the insulating anti-reflection film 19 in the N region slot 24 by adopting a chemical etching method to obtain an insulating anti-reflection layer 7; the insulating antireflection film 19 disposed in the remaining region except the N-region slit 24 in the N-type region is the insulating antireflection layer 7.
(12) Preparing a TCO film 25 on the back surface of the silicon substrate 1; the whole surfaces of the N-type region and the P-type region are covered by the TCO film 25;
(13) Removing the TCO film 25 and the second passivation contact structure between the N-region groove 24 and the P-type region 3 by adopting a laser etching method to form an isolation groove 12, a second passivation layer 8, a P-type doped semiconductor layer 9, a first TCO layer 6 and a second TCO layer 10; the remaining part of the second passivation film 22 after the isolation trench 12 is removed is the second passivation layer 8, the remaining part of the P-type doped semiconductor film 23 after the isolation trench 12 is removed is the P-type doped semiconductor layer 9, and the TCO film 25 is cut off by the isolation trench 12, and is divided into the first TCO layer 6 and the second TCO layer 10.
(14) A first metal gate electrode 13 is prepared on the surface of the first TCO layer 6 in the n-region trench 24, and a second metal gate electrode 14 is prepared on the surface of the second TCO layer 10 in the p-region trench 20, resulting in the back contact cell of the embodiments of the present invention.
The preparation method of the back contact battery provided by the embodiment of the invention has the advantages of reasonable step arrangement, simplicity and easiness in operation, and is suitable for mass production popularization; the problem of electric leakage of the back contact battery can be solved, and the conversion efficiency of the battery can be effectively improved.
In some embodiments, in step (1), the silicon substrate has a resistivity of 0.5 to 2 Ω and a thickness of 120 to 200 μm.
In some embodiments, in step (1), the cleaning treatment comprises an acid wash treatment, a water wash treatment. This helps to form a hydrophobic surface, facilitating subsequent fabrication of other layers of structure on the silicon substrate.
In some embodiments, in step (1), a texture surface 26 is prepared on the back and/or front side of the silicon substrate 1 before the cleaning process is performed.
In some embodiments, step (1) is performed with a NaOH solution or KOH solution having a volume concentration of 0.8-1.2%.
In some embodiments, in step (2), the first passivation layer 4 is deposited using a tube or chain oxidation apparatus.
In some embodiments, in step (2), the thickness of the first passivation layer 4 <
In some embodiments, in step (2), a front passivation film 15 is simultaneously prepared on the front surface of the silicon substrate 1; and/or, in the step (4), the front-side antireflection film 16 is simultaneously prepared on the front side of the silicon substrate 1.
In some embodiments, in the step (3), an N-type doped semiconductor film may also be directly deposited, and accordingly, in the step (4), an insulating anti-reflective film 19 is prepared on the surface of the N-type doped semiconductor film; in the step (6), removing the N-type doped semiconductor film in the P-type region 3 by adopting a chemical etching method to form a P-region slot 20; in step (7), the silicon substrate 1 is annealed to grow an insulating film 21 on the inner side surface of the P-region trench 20. Compared with the method that the N-type doped semiconductor film is directly deposited in the step (3), the N-type doped semiconductor precursor 18 is deposited first and then is converted into the N-type doped semiconductor layer 5,N by annealing treatment in the step (7), so that the conductivity effect of the N-type doped semiconductor layer 5 is better.
In some embodiments, in step (3), the N-doped semiconductor precursor 18 is deposited using a PECVD or LPCVD process.
In some embodiments, in step (3), the doping concentration is > 5×10 20 atoms/cm 3 The thickness of the N-type doped semiconductor precursor 18 is 20-70nm.
In some embodiments, in step (4), the thickness of the insulating anti-reflective film 19 is 60-110nm.
In some embodiments, in step (6), the first passivation layer 4 and the silicon substrate 1 are protected with an etch protectant to prevent damage to the first passivation layer 4 and the silicon substrate 1 while etching the N-doped semiconductor precursor 18.
In some embodiments, in step (7), the temperature of the annealing treatment is 850-950 ℃.
In some embodiments, in step (9), the thickness of the second passivation film 8 <The doping concentration is more than 5 multiplied by 10 20 atoms/cm 3 。
In some embodiments, in step (9), the thickness of the P-type doped semiconductor film 9 is 20-70nm, the doping concentration is > 5×10 20 atoms/cm 3 。
In some embodiments, in step (11), the etching is performed with HF acid at a concentration of 5-30% by volume.
In some embodiments, in step (12), the TCO film 25 is deposited using PVD or RPD methods.
In some embodiments, in step (12), the thickness of the TCO film 25 is 60-100nm.
In some embodiments, in step (14), the first metal gate line electrode employs a low work function metal, such as silver; the second metal gate line electrode employs a high work function metal, such as aluminum.
The present invention will be described in detail with reference to the following examples and drawings.
Example 1
A back contact battery, as shown in fig. 14, comprising: a silicon substrate 1, the back surface of the silicon substrate 1 comprises N-type regions 2 and P-type regions 3 which are adjacently and alternately arranged; the N-type region 2 is provided with a first passivation contact structure comprising a first passivation layer 4 (silicon oxide SiO 2 ) And an N-type doped semiconductor layer 5 (phosphorus doped polysilicon (N) poly-Si), wherein a first TCO layer 6 is arranged on a partial area of the surface of the N-type doped semiconductor layer 5 (phosphorus doped polysilicon (N) poly-Si), and an insulating anti-reflection layer 7 (silicon nitride SiN) is arranged on the rest area of the surface of the N-type doped semiconductor layer 5 (phosphorus doped polysilicon (N) poly-Si) x ) The method comprises the steps of carrying out a first treatment on the surface of the The P-type region 3 is provided with a second passivation contact structure, the second passivation contact structure comprises a second passivation layer 8 (intrinsic hydrogenated amorphous silicon a-Si-H) and a P-type doped semiconductor layer 9 (boron doped hydrogenated amorphous silicon (P) a-Si-H), which are sequentially stacked, and a second TCO layer 10 is arranged on the surface of the P-type doped semiconductor layer 9 (boron doped hydrogenated amorphous silicon (P) a-Si-H); in the P-type region 3 and the N-type regionAn insulating layer 11 (silicon oxide SiO) is longitudinally arranged at the boundary position of the domain 2 x ) Insulating layer 11 (silicon oxide SiO) 2 ) And an insulating antireflection layer 7 (silicon nitride SiN) x ) Interconnecting, spacing the first passivation contact structure and the second passivation contact structure; a first TCO layer 6, an insulating anti-reflection layer 7 (silicon nitride SiN x ) Insulating layer 11 (SiO) 2 ) An isolation trench 12 is provided between the second passivation contact structure and the second TCO layer 10; the first TCO layer 6 is provided with a first metal gate electrode 13 (Ag) on its surface and the second TCO layer 10 is provided with a second metal gate electrode 14 (Al) on its surface.
The preparation method of the back contact battery of the embodiment comprises the following steps:
(1) Selecting an N-type silicon wafer with resistivity of 0.5-2 omega and thickness of 150 mu m as a silicon substrate 1, preparing a suede 26 on the back and front surfaces of the silicon substrate 1 by using NaOH solution with volume concentration of 1.0%, washing with HF+HCL acid and deionized water, and forming a hydrophobic surface, wherein the obtained structure is shown in figure 1;
(2) A layer of silicon substrate 1 with thickness is grown on the back surface after the velvet manufacturing is completed by adopting tubular oxidation equipmentSiO of (2) 2 As the first passivation film 17, a layer of a thickness +.>SiO of (2) 2 As the front passivation film 15, the structure obtained is shown in fig. 2;
(3) Growing a layer of phosphorus doped amorphous silicon (N) a-Si as an N doped semiconductor precursor 18 on the back surface by adopting a PECVD machine, wherein the phosphorus doping concentration is 6 multiplied by 10 20 atoms/cm 3 The thickness of the phosphorus doped amorphous silicon (n) a-Si is 50nm, and SiH is used as doping gas 4 、PH 3 、H 2 The resulting structure is shown in FIG. 3;
(4) Depositing a layer of silicon nitride (SiN) with thickness of 80nm on the back surface by adopting a PECVD machine x ) As the insulating antireflection film 19, a layer of silicon nitride (SiN) having a thickness of 80nm was deposited on the front surface x ) As the front surface antireflection film 16, the reaction gas is SiH 4 、NH 3 The resulting structure is shown in FIG. 4;
(5) Grooving the back surface by a laser grooving method, removing a part of the insulating antireflection film 19, and making a P-type region 3 (also called a P-type contact region), wherein the grooving pattern is designed according to the design, and the obtained structure is shown in fig. 5;
(6) Etching the N-doped semiconductor precursor 18 (phosphorus doped amorphous silicon (N) a-Si) in the P-type region 3 with a trench base while etching the first passivation layer 4 (silicon oxide SiO) with an etch protectant 2 ) And the silicon substrate 1 is protected, a deposition space, namely a P region slot 20, is formed in the P region 3, the width of the P region 3 is required to be larger than that of the N region 2 (also called an N contact region), and the obtained structure is shown in figure 6;
(7) High temperature annealing at 920 deg.c to grow one layer of 5nm width silicon oxide SiO on the inner side of the slot 20 2 As the insulating film 21, a PN junction is partitioned to reduce generation of leakage current, while the deposited N-type doped semiconductor precursor 18 (phosphorus doped amorphous silicon (N) a-Si) is converted into the N-type doped semiconductor layer 5 (phosphorus doped polysilicon (N) poly-Si), and phosphorus atoms are activated, the resulting structure is shown in fig. 7;
(8) An insulating film 21 (silicon oxide SiO) on the inner side of the trench 20 in the reserved P region 2 ) And an insulating film 21 (silicon oxide SiO) 2 ) A first passivation film 17 (silicon oxide SiO) 2 ) In the case of (1), the first passivation film 17 (silicon oxide SiO) in other regions of the surface of the P region trench 20 is removed by laser etching 2 ) Then the surface of the P-type region 3 is cleaned by adopting diluted HF solution, the laser pattern is consistent with the step (5), and an insulating layer 11 (silicon oxide SiO) is formed 2 ) The resulting structure is shown in fig. 8;
(9) A layer of intrinsic hydrogenated amorphous silicon a-Si-H is sequentially deposited on the back surface by a PECVD machine to serve as a second passivation film 22, and the thickness of the second passivation film 22 (the intrinsic hydrogenated amorphous silicon a-Si-H) is as followsDepositing a layer of boronThe doped hydrogenated amorphous silicon (P) a-Si-H was used as the P-type doped semiconductor film 23, the thickness of the P-type doped semiconductor film 23 (boron doped hydrogenated amorphous silicon (P) a-Si-H) was 50nm, and the boron doping concentration was 6X 10 20 atoms/cm 3 The resulting structure is shown in fig. 9;
(10) The second passivation film 22 (boron doped hydrogenated amorphous silicon (P) a-Si-H) and the P-doped semiconductor film 23 (intrinsic hydrogenated amorphous silicon a-Si-H) in the N-type region 2 are removed by laser etching to form N-region trench 24, and insulating antireflection film 19 (silicon nitride SiN) x ) Exposing, and etching the pattern according to the design, wherein the obtained structure is shown in figure 10;
(11) The back surface is etched by a chain device to remove the exposed insulating anti-reflection film 19 (SiN nitride) x ) The etching solution was an HF solution having a volume concentration of 15%, and an insulating antireflection film 19 (silicon nitride SiN) was formed in the remaining region x ) Namely, the insulating antireflection layer 7, the resulting structure is shown in fig. 11;
(12) Depositing a layer of TCO film 25 on the back surface by adopting a PVD machine table and using ZnO, wherein the thickness of the TCO film 25 is 80nm, and the obtained structure is shown in figure 12;
(13) The laser etching method is adopted again to process, a part of TCO film 25 at the contact position of N-type region 2 and P-type region 3, second passivation film 22 (intrinsic hydrogenated amorphous silicon a-Si-H) and P-type doped semiconductor film 23 (boron doped hydrogenated amorphous silicon (P) a-Si-H) are removed, isolation groove 12 is formed, PN region is isolated, electric leakage is prevented, the pattern of laser processing is determined according to the design, the rest of second passivation film 22 (intrinsic hydrogenated amorphous silicon a-Si-H) after isolation groove 12 is removed is second passivation layer 8, the rest of P-type doped semiconductor film 23 (boron doped hydrogenated amorphous silicon (P) a-Si-H) after isolation groove 12 is removed is P-type doped semiconductor layer 9, TCO film 25 is separated into first TCO layer 6 and second TCO layer 10 after isolation groove 12 is removed, and the obtained structure is shown in figure 13;
(14) Silver paste is printed on the surface of the first TCO layer 6 in the N-region trench 24, aluminum paste is printed on the surface of the second TCO layer 10 in the P-region trench 20, then the mixture is sintered, the first metal gate electrode 13 (Ag) is formed in the N region 2, the second metal gate electrode 14 (Al) is formed in the P region 5, and the obtained structure is shown in FIG. 14.
For purposes of this disclosure, the terms "one embodiment," "some embodiments," "example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (11)

1. A back contact battery, comprising: the back surface of the silicon substrate comprises N-type regions and P-type regions which are adjacently and alternately arranged; the N-type region is provided with a first passivation contact structure, the first passivation contact structure comprises a first passivation layer and an N-type doped semiconductor layer which are sequentially stacked, a first TCO layer is arranged in a partial region of the surface of the N-type doped semiconductor layer, and an insulating anti-reflection layer is arranged in the rest region of the surface of the N-type doped semiconductor layer; the P-type region is provided with a second passivation contact structure, the second passivation contact structure comprises a second passivation layer and a P-type doped semiconductor layer which are sequentially stacked, and a second TCO layer is arranged on the surface of the P-type doped semiconductor layer; an insulating layer is longitudinally arranged at the junction position of the P-type region and the N-type region, and the insulating layer and the insulating anti-reflection layer are connected with each other to separate the first passivation contact structure from the second passivation contact structure; an isolation groove is arranged among the first TCO layer, the insulating anti-reflection layer, the insulating layer, the second passivation contact structure and the second TCO layer; the first TCO layer surface is provided with a first metal gate line electrode, and the second TCO layer surface is provided with a second metal gate line electrode.
2. The back contact battery of claim 1, wherein the first passivation layer is silicon oxide and the N-doped semiconductor layer is N-doped polysilicon; the second passivation layer adopts intrinsic hydrogenated amorphous silicon and/or intrinsic hydrogenated microcrystalline silicon, and the P-type doped semiconductor layer adopts P-type doped hydrogenated amorphous silicon and/or P-type doped hydrogenated microcrystalline silicon.
3. The back contact cell of claim 1 or 2, wherein the insulating anti-reflective layer is silicon nitride.
4. A back contact cell according to claim 3, wherein the thickness of the insulating anti-reflective layer is 60-110nm.
5. The back contact battery of claim 1 or 2, wherein the insulating layer is silicon oxide.
6. The back contact battery of claim 5, wherein the insulating layer has a width of
7. The back contact battery of claim 1 or 2, wherein the front surface of the silicon substrate is sequentially laminated with a front passivation film and a front antireflection film.
8. The back contact battery of claim 1, wherein in the case of an N-type battery, the P-type region has a width greater than the width of the N-type region; or, in the case that the back contact battery is a P-type battery, the width of the P-type region is smaller than the width of the N-type region.
9. The method of manufacturing a back contact battery according to any one of claims 1 to 8, comprising the steps of:
(1) Cleaning the silicon substrate;
(2) Preparing a first passivation film on the back surface of the silicon substrate;
(3) Preparing an N-type doped semiconductor precursor on the surface of the first passivation film;
(4) Preparing an insulating anti-reflection film on the surface of the N-type doped semiconductor precursor;
(5) Removing the insulating anti-reflection film in the P-type region by a laser grooving method;
(6) Removing the N-type doped semiconductor precursor in the P-type region by adopting a chemical etching method to form a P-region slot;
(7) Annealing the silicon substrate to enable the inner side face of the groove of the P region to grow an insulating film, and simultaneously converting the N-type doped semiconductor precursor in the N-type region into an N-type doped semiconductor layer;
(8) Removing the first passivation film in other areas in the grooves of the P area by adopting a laser etching method under the condition that the insulating film and the first passivation film in the area longitudinally corresponding to the insulating film are reserved, so as to obtain the insulating layer and the first passivation layer;
(9) Preparing a second passivation film on the back surface of the silicon substrate; preparing a P-type doped semiconductor film on the surface of the second passivation film;
(10) Removing the second passivation film and the P-type doped semiconductor film in a partial region of the N-type region by adopting a laser etching method to form an N-region slot;
(11) Removing the insulating anti-reflection film in the N region slot by adopting a chemical etching method to obtain the insulating anti-reflection layer;
(12) Preparing a TCO film on the back surface of the silicon substrate;
(13) Removing the TCO film and the second passivation contact structure between the N region groove and the P type region by adopting a laser etching method to form the isolation groove, the first TCO layer and the second TCO layer;
(14) And preparing the first metal gate line electrode on the surface of the first TCO layer in the n-region slot, and preparing the second metal gate line electrode on the surface of the second TCO layer in the p-region slot to obtain the back contact battery.
10. The method of claim 9, wherein in step (1), a textured surface is formed on the back surface and/or the front surface of the silicon substrate before the cleaning treatment.
11. The method of manufacturing a back contact battery according to claim 9, wherein in step (2), the front passivation film is simultaneously manufactured on the front surface of the silicon substrate; and/or, in the step (4), preparing the front-side antireflection film on the front side of the silicon substrate at the same time.
CN202310459560.2A 2023-04-24 2023-04-24 Back contact battery and preparation method thereof Pending CN116565034A (en)

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