CN116564963A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN116564963A
CN116564963A CN202210108860.1A CN202210108860A CN116564963A CN 116564963 A CN116564963 A CN 116564963A CN 202210108860 A CN202210108860 A CN 202210108860A CN 116564963 A CN116564963 A CN 116564963A
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China
Prior art keywords
initial
fin
fins
region
forming
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CN202210108860.1A
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Chinese (zh)
Inventor
张静
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Priority to CN202210108860.1A priority Critical patent/CN116564963A/en
Publication of CN116564963A publication Critical patent/CN116564963A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and method of forming the same, wherein the method comprises: forming a substrate, wherein the substrate comprises a first region and a second region, the first region is provided with a plurality of initial first fins, the second region is provided with a plurality of initial second fins, and the width of the initial second fins is smaller than that of the initial first fins; forming an isolation layer on the surface of the substrate, wherein the surface of the isolation layer is lower than the top surface of the initial first fin and the top surface of the initial second fin; after the isolation layer is formed, a plurality of initial first fins and a plurality of initial second fins are etched by adopting a wet etching process, and a plurality of first fins and a plurality of second fins are formed, wherein the etching rate of the wet etching process on the material of the initial first fins is larger than that on the material of the initial second fins. Thus, the performance of the semiconductor structure can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the increase in the integration level of semiconductor devices, the critical dimensions of transistors are continually shrinking. However, as the transistor size is rapidly reduced, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gates of Fin Field effect transistors (Fin Field-Effect Transistor, finFETs) are in a fork-like 3D architecture resembling a fish Fin. The channel of the FinFET protrudes out of the surface of the substrate to form a fin portion, and the grid electrode covers the top surface and the side wall of the fin portion, so that inversion layers are formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin portion. This design can increase the control of the gate over the channel region, thereby well suppressing the short channel effect of the transistor.
However, the performance of existing semiconductor structures remains to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: the substrate comprises a first region and a second region, wherein the first region is provided with a plurality of first fins, and the second region is provided with a plurality of second fins; and the surface of the isolation layer is lower than the top surfaces of the first fins and the second fins, and the width of the first fins on the isolation layer is smaller than that of the first fins in the isolation layer.
Optionally, the difference between the width of the first fin on the isolation layer and the width of the second fin on the isolation layer is 1 angstrom to 60 angstrom.
Optionally, the material of the first fin includes silicon, and the material of the second fin includes silicon germanium.
Optionally, the bottom surface of the second fin is lower than the surface of the isolation layer, and the width of the second fin in the isolation layer is smaller than the width of the first fin in the isolation layer.
Optionally, the method further comprises: and the top surface of the isolation fin is lower than or flush with the surface of the isolation layer.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: forming a substrate, wherein the substrate comprises a first region and a second region, the first region is provided with a plurality of initial first fins, the second region is provided with a plurality of initial second fins, and the width of the initial second fins is smaller than that of the initial first fins; forming an isolation layer on the surface of the substrate, wherein the surface of the isolation layer is lower than the top surface of the initial first fin and the top surface of the initial second fin; after the isolation layer is formed, a plurality of initial first fins and a plurality of initial second fins are etched by adopting a wet etching process, and a plurality of first fins and a plurality of second fins are formed, wherein the etching rate of the wet etching process on the material of the initial first fins is larger than that on the material of the initial second fins.
Optionally, an etching selectivity of the etching solution of the wet etching process to the material of the initial first fin and the material of the initial second fin is greater than 1 and less than or equal to 10.
Optionally, the etching selectivity ratio of the etching solution of the wet etching process to the (100) crystal face and the (111) crystal face of the material of the initial first fin is in a range of 1-2.
Optionally, the material of the initial first fin includes silicon, the material of the initial second fin includes silicon germanium, and the etching solution in the wet etching process is a mixed solution, and the mixed solution includes an alkaline solution, hypochlorite and phosphate.
Optionally, the alkaline solution comprises tetrabutylammonium hydroxide or tetramethylammonium hydroxide.
Optionally, an etching selectivity ratio of the etching solution of the wet etching process to the material of the initial first fin and the material of the isolation layer is above 4.
Optionally, the etching duration of the wet etching process is 10 seconds to 300 seconds.
Optionally, the difference between the width of the initial first fin and the width of the initial second fin ranges from 1 angstrom to 50 angstrom.
Optionally, the method further comprises: and forming a protective film on the surface of the initial second fin before forming the isolation layer.
Optionally, the method of forming the substrate, the plurality of initial first fins, and the plurality of initial second fins includes: providing an initial substrate; forming a second fin material layer in the initial substrate over the second region; after forming the second fin material layer, forming a plurality of fin mask structures which are mutually separated on the first region and the second region; and etching the initial substrate and the second fin material layer by adopting a dry etching process and taking the fin mask structure as a mask.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the method for forming the semiconductor structure, the isolation layer is formed on the surface of the substrate, the surface of the isolation layer is lower than the top surface of the initial first fins and the top surface of the initial second fins, then the wet etching process is adopted to etch the initial first fins and the initial second fins (exposed on the isolation layer), and in the wet etching process, the etching rate of the material of the initial first fins is higher than that of the material of the initial second fins, so that the width difference between the effective width of the initial first fins and the effective width of the initial second fins can be reduced, and the first fins and the second fins with the effective widths being closer to each other are formed. Thereby, the performance of the semiconductor structure is improved.
Drawings
FIGS. 1-2 are schematic cross-sectional views of steps in a method for forming a semiconductor structure;
fig. 3 to 6 are schematic cross-sectional views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, existing semiconductor structures have poor performance. The following description is analyzed in connection with a semiconductor structure.
Fig. 1 to 2 are schematic cross-sectional views illustrating steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, and the substrate 100 includes a first region S1 and a second region S2.
With continued reference to fig. 1, the substrate 100 of the second region S2 is etched, an opening (not shown) is formed in the second region S2, and a second fin material layer 110 is formed in the opening.
Referring to fig. 2, a plurality of fin mask structures (not shown) are formed on the first region S1 and the second region S2 separately from each other; the substrate 100 and the second fin material layer 110 are etched using the fin mask structures as masks, to form a substrate 101, a plurality of first fins 121 located on the first region S1, and a plurality of second fins 122 located on the second region S2.
However, in the above method, the material of the substrate 100 is silicon, the material of the second fin material layer 110 is silicon germanium, and the more reactive silicon germanium is generally more reactive etched than silicon, so that critical dimensions of the first fin 121 and the second fin 122 generate serious Loading (Loading), and the width K1 (shown in fig. 2) of the first fin 121 is far greater than the width K2 (shown in fig. 2) of the second fin 122, which results in failing to meet the device performance requirement, resulting in poor performance of the semiconductor structure.
In order to solve the above-mentioned technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, in which a substrate is formed, the substrate includes a first region and a second region, the first region has a plurality of initial first fins, the second region has a plurality of initial second fins, the width of the initial second fins is smaller than the width of the initial first fins, then an isolation layer is formed on the surface of the substrate, the surface of the isolation layer is lower than the top surface of the initial first fins and the top surface of the initial second fins, and after the isolation layer is formed, a wet etching process is used to etch the plurality of initial first fins and the plurality of initial second fins to form a plurality of first fins and a plurality of second fins, and the etching rate of the wet etching process to the material of the initial first fins is greater than the etching rate to the material of the initial second fins, so that the performance of the semiconductor structure can be improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 6 are schematic cross-sectional views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the invention.
First, a substrate is formed, the substrate comprising a first region having a plurality of initial first fins thereon and a second region having a plurality of initial second fins thereon, the initial second fins having a width smaller than the width of the initial first fins. For specific steps of forming the substrate, the initial first fin, and the initial second fin, refer to fig. 3 and 4.
Referring to fig. 3, an initial substrate 200 is provided, and the initial substrate 200 includes a first region I and a second region II.
The material of the initial substrate 200 includes a semiconductor material.
Specifically, the material of the substrate 200 includes silicon.
In this embodiment, the initial substrate 200 on the first region I provides material for the subsequent formation of initial first fins.
With continued reference to fig. 3, a second fin material layer 210 is formed in the initial substrate 200 over the second region II.
In this embodiment, the second fin material layer 210 provides material for subsequent formation of initial second fins.
In this embodiment, the material of the second fin material layer 210 is different from the material of the initial substrate 200.
In this embodiment, the material of the second fin material layer 210 includes silicon germanium.
In this embodiment, the method for forming the second fin material layer 210 in the initial substrate 200 on the second region II includes: forming a first mask layer (not shown) on the surface of the initial substrate 200, the first mask layer exposing the surface of the initial substrate 200 on the second region II; etching the exposed initial substrate 200 with the first mask layer as a mask until a fin material opening (not shown) is formed in the initial substrate 200 over the second region II; the second fin material layer 210 is formed within the fin material opening.
The process of forming the second fin material layer 210 includes a deposition process, an epitaxial process, and the like.
In this embodiment, the first mask layer is removed after the fin material opening is formed and before the fin mask structure is subsequently formed.
Referring to fig. 4, after the second fin material layer 210 is formed, a plurality of fin mask structures (not shown) are formed on the first region I and the second region II, which are separated from each other; and etching the initial substrate 200 and the second fin material layer 210 by adopting a dry etching process and taking the fin mask structures as masks to form a substrate 220, a plurality of initial first fins 231 and a plurality of initial second fins 232.
Specifically, the substrate 220 includes a first region I and a second region II, where the first region I has a plurality of initial first fins 231 thereon, and the second region II has a plurality of initial second fins 232 thereon, and a width W2 of the initial second fins 232 is smaller than a width W1 of the initial first fins 231.
In this embodiment, the method for forming a plurality of fin mask structures on the first region I and the second region II, which are separated from each other, includes: after forming the second fin material layer 210, a fin mask structure material layer (not shown) is formed on the surface of the initial substrate 200 and the surface of the second fin material layer 210; forming a fin mask structure photoetching pattern layer (not shown) on the surface of the fin mask structure material layer; and etching the fin mask structure material layer by taking the fin mask structure photoetching pattern layer as a mask until the surface of the initial substrate 200 and the surface of the second fin material layer 210 are exposed.
In some other embodiments, the fin mask structures are formed using a self-aligned dual imaging process or a self-aligned multiple imaging process.
In this embodiment, since the materials of the initial substrate 200 and the second fin material layer 210 on the first region I and the second region II are etched by the same dry etching process, the process complexity is low, the generated unstable factors are few, and the process stability is good.
It will be appreciated that a dry etch process is easier and faster to etch different materials simultaneously at a closer etch rate than a wet etch process, conveniently in the same process step, while forming several initial first fins 231 and several initial second fins 232. However, since the material of the initial substrate 200 is different from the material of the second fin material layer 210, the dry etching process still has a difference in etching rate of the material of the initial substrate 200 and the material of the second fin material layer 210, resulting in a load between the critical dimension of the initial first fin 231 and the critical dimension of the initial second fin 232.
In this embodiment, the material of the initial first fin 231 includes silicon, and the material of the initial second fin 232 includes silicon germanium. Accordingly, the width W2 of the initial second fin 232 is smaller than the width W1 of the initial first fin 231.
In the present embodiment, the difference between the width W1 and the width W2 ranges from 1 angstrom to 50 angstrom.
If the difference between the width W1 and the width W2 is too large, more exposed initial first fins 231 need to be etched in the subsequent wet etching process, so that more adjustment is performed on the width of the exposed initial first fins 231, thereby affecting the efficiency. Therefore, the difference between the width W1 of the initial first fin 231 and the width W2 of the initial second fin 232 is in the range of 1 angstrom to 50 angstrom, so that the difficulty and time of the subsequent wet etching process performed on the exposed initial first fin 231 and initial second fin 232 can be reduced, and the first fin and the second fin meeting the expected width difference can be formed more efficiently.
In this embodiment, the step of the dry etching process is adopted to etch the initial substrate 200 and the second fin material layer 210, so as to better increase the process stability and improve the efficiency.
In other embodiments, the initial substrate and the second fin material layer may also be etched using 2 or more steps of the dry etching process.
In this embodiment, the dry etching process includes a plasma etching process and the like.
In this embodiment, the initial substrate 200 and the second fin material layer 210 are etched with the fin mask structures as masks, and in the process of forming the substrate 220, the initial first fins 231 and the initial second fins 232, the isolation fins 233 between the initial second fins 232 and the substrate 220 are also formed.
The isolation fin 233 is of the same material as the substrate 220.
In some other embodiments, the etching process may be stopped when the initial substrate and the second fin material layer are etched by using the fin mask structures as masks by a dry etching process: exposing the initial substrate surface under the second fin material layer. Accordingly, the isolation fin between the initial second fin and the substrate is not formed.
In the present embodiment, after forming the plurality of initial first fins 231 and the plurality of initial second fins 232, wet cleaning is performed on etching byproducts (polymers) remained on the surfaces of the substrate 220, the plurality of initial first fins 231 and the plurality of initial second fins 232.
In this embodiment, after the wet cleaning, a protective film (not shown) is formed on the surfaces of the plurality of initial second fins 232.
Forming the protective film can reserve etched materials for a subsequent wet etching process of etching the plurality of initial first fins 231 and the plurality of initial second fins 232, and thus further slow down the etching of the initial second fins 232, thereby enabling the reduction of the width difference between the width of the exposed initial first fins 231 and the width of the exposed initial second fins 232 while not changing the width W2 of the initial second fins 232 or less changing the width W2 of the initial second fins 232. Therefore, the width difference between the effective width of the formed first fin (namely the width of the exposed first fin) and the effective width of the formed second fin (namely the width of the exposed second fin) is reduced, and meanwhile, the effective width of the first fin and the effective width of the second fin can be enabled to be closer to the expected width, so that the performance of the semiconductor structure is further improved.
In this embodiment, the material of the protective film is the same as that of the initial first fin 231, so that the protective film on the surface of the initial second fin 232 exposed subsequently can be directly consumed in the subsequent wet etching process, thereby further improving the efficiency.
Specifically, the material of the protective film includes silicon.
In this embodiment, the film thickness of the protective film is 50 angstrom or less.
The thickness of the protective film is too thick, which makes it difficult to directly consume the protective film in the subsequent wet etching process, so that, on one hand, the adjustment of the effective width of the initial first fin 231 is easily affected for consuming the protective film, and on the other hand, the exposed second fin surface is easily affected by the residual protective film. Therefore, the protective film with proper film thickness is adopted, namely, the film thickness of the protective film is less than 50 angstroms, so that the effective width of the first fin and the effective width of the second fin can be better close to the expected width, and the performance of the semiconductor structure can be better improved.
Referring to fig. 5, an isolation layer (STI) 240 is formed on the surface of the substrate 220, and the surface of the isolation layer 240 is lower than the top surface of the initial first fin 231 and the top surface of the initial second fin 232.
In this embodiment, the surface of the isolation layer 240 is higher than the bottom surface of the initial second fin 232. To better ensure insulation between the semiconductor devices. Accordingly, the top surface of the isolation fin 233 is lower than the surface of the isolation layer 240.
In some other embodiments, the surface of the isolation layer is flush with the contact surface of the initial second fin and the isolation fin (i.e., the bottom surface of the initial second fin and the top surface of the isolation fin).
In this embodiment, the material of the isolation layer 240 is a dielectric material.
In this embodiment, the dielectric material comprises silicon oxide.
In this embodiment, the method for forming the isolation layer 240 includes: depositing a layer of isolation material (not shown) on the substrate 220 surface, the initial first plurality of fins 231 surfaces, and the initial second plurality of fins 232 surfaces, the isolation material layer surface being higher than the initial first plurality of fins 231 surfaces and the initial second plurality of fins 232 surfaces; planarizing the isolation material layer until top surfaces of the initial first fins 231 and the initial second fins 232 are exposed; after planarizing the isolation material layer, the isolation material layer is etched back until the isolation layer 240 is formed.
In this embodiment, the process of depositing the isolation material layer includes a Flowable Chemical Vapor Deposition (FCVD), the process of planarizing the isolation material layer includes a Chemical Mechanical Polishing (CMP), and after planarizing the isolation material layer, the process of etching back the isolation material layer includes at least one of a dry etching process and a wet etching process.
Referring to fig. 6, after the isolation layer 240 is formed, a wet etching process is used to etch the plurality of initial first fins 231 and the plurality of initial second fins 232 to form the plurality of first fins 251 and the plurality of second fins 252, where an etching rate of the material of the initial first fins 231 is greater than an etching rate of the material of the initial second fins 232.
It should be appreciated that the width W3 of the first fin 251 on the isolation layer 240 is the effective width of the first fin 251, and the width W4 of the second fin 252 on the isolation layer 240 is the effective width of the second fin 252.
Since the spacer 240 is formed on the surface of the substrate 220, the surface of the spacer 240 is lower than the top surfaces of the initial first fins 231 and the initial second fins 232, and then the initial first fins 231 and the initial second fins 232 (exposed on the spacer 240) are etched using a wet etching process, and the etching rate of the material of the initial first fins 231 is greater than that of the material of the initial second fins 232 in the wet etching process, the width difference between the effective width of the initial first fins 231 and the effective width of the initial second fins 232 can be reduced, and thus, the first fins 251 and the second fins 252 having the effective widths closer to each other are formed. Thereby, the performance of the semiconductor structure is improved.
In this embodiment, the etching selectivity ratio of the etching solution of the wet etching process to the material of the initial first fin 231 and the material 232 of the initial second fin is greater than 1 and less than or equal to 10. Therefore, the wet etching process is not easy to etch the initial first fin 231 too quickly, so that the effective width of the first fin 251 can be better trimmed to balance the difference between the effective width of the first fin 251 and the effective width of the second fin 252.
Preferably, the wet etching process has an etching selectivity ratio of 3 for the material of the initial first fin 231 and the material 232 of the initial second fin.
In this embodiment, the etching selectivity ratio of the etching solution of the wet etching process to the (100) crystal plane and the (111) crystal plane of the material of the initial first fin 231 is in the range of 1-2. Accordingly, the wet etching process is less prone to deterioration of the surface roughness of the initial first fin 231 when the exposed initial first fin 231 is etched, and thus the surface roughness of the formed first fin 251 is small (the surface is smoother).
It should be appreciated that, in this embodiment, the protection film is formed, so the wet etching process etches and consumes the protection film before etching the initial second fin 232.
In this embodiment, the etching solution in the wet etching process is a mixed solution, and the mixed solution includes an alkaline solution and an additive.
Specifically, the additive comprises: hypochlorite and phosphate.
The alkaline solution in the mixed solution has a large etching selectivity to the material of the initial first fin 231 and the material of the initial second fin 232. Typically, the alkaline solution has a material etch selectivity ratio of greater than 100 or greater than 1000 for the initial first fin 231 material and the initial second fin 232 material. The etching selectivity ratio of the alkaline solution to the material of the initial first fin 231 and to the material of the initial second fin 232 may be reduced by the additives (i.e., the hypochlorite and the phosphate) in the mixed solution, and the etching selectivity ratio of greater than 1 and less than or equal to 10 may be achieved. In addition, the additives (i.e., the hypochlorite and the phosphate) can be effectively attached to the (100) crystal plane and the (110) crystal plane of the material of the initial first fin 231 by chemical reaction or physical action, and thus, the etching rate of the (100) crystal plane and the (110) crystal plane of the material of the initial first fin 231 can be also slowed down so that the etching selectivity ratio of the etching liquid of the wet etching process to the (100) crystal plane and the (111) crystal plane of the material of the initial first fin 231 is in a suitable range (the etching selectivity ratio range is 1 to 2).
In this embodiment, the alkaline solution includes an organic base such as tetrabutylammonium hydroxide or tetramethylammonium hydroxide.
Preferably, the content of the additive in the mixed solution is less than 1wt%.
In this embodiment, the etching selectivity ratio of the etching solution of the wet etching process to the material of the initial first fin 231 and the material of the isolation layer 240 is above 4.
Specifically, the wet etching process has a loss to the isolation layer 240 of less than 1.3 a/min.
In this embodiment, the etching duration of the wet etching process is 10 seconds to 300 seconds.
In this embodiment, an in-situ wet clean step is performed prior to etching the initial first fins 231 and the initial second fins 232 in the wet etch process.
The in-situ wet cleaning step is used to remove the oxide film on the surfaces of the initial first fins 231 and the initial second fins 232.
The oxide film is oxidized before the wet etching process due to the precursor process or exposure of the initial first fins 231 and the initial second fins 232 to air.
In this embodiment, the cleaning solution used in the in-situ wet cleaning step includes hydrogen fluoride, and the duration of the in-situ wet cleaning step is less than 10 minutes.
In some other embodiments, the in situ wet cleaning step is not performed.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to fig. 6, which includes: a substrate 220, the substrate 220 comprising a first region I having a plurality of first fins 251 thereon and a second region II having a plurality of second fins 252 thereon; an isolation layer 240 located on a surface of the substrate 220, wherein a surface of the isolation layer 240 is lower than a top surface of the first fin 251 and a top surface of the second fin 252, and a width W3 of the first fin 251 on the isolation layer 240 is smaller than a width W1 of the first fin 251 in the isolation layer 240.
In this embodiment, the difference between the width W3 of the first fin 251 on the isolation layer 240 and the width W4 of the second fin 252 on the isolation layer 240 is 1 angstrom to 60 angstrom.
In this embodiment, the bottom surface of the second fin 252 is lower than the surface of the isolation layer 240, so as to better ensure insulation between the semiconductor devices.
In this embodiment, the width W2 of the second fin 252 in the isolation layer 240 is smaller than the width W1 of the first fin 251 in the isolation layer 240.
In this embodiment, the semiconductor structure further includes: isolation fin 233 between the second fin 252 and the substrate 220. Accordingly, the top surface of the isolation fin 233 is lower than the surface of the isolation layer 240. In some other embodiments, the top surface of the isolation fin is flush with the isolation layer surface.
The material of the substrate 220 includes a semiconductor material. Specifically, the material of the substrate 220 includes silicon.
In this embodiment, the material of the first fin 251 is the same as the material of the substrate 220, and the material of the first fin 251 includes silicon.
In this embodiment, the material of the second fin 252 is different from the material of the first fin 251, and the material of the second fin 252 includes silicon germanium.
In this embodiment, the material of the isolation layer 240 is a dielectric material. Specifically, the dielectric material includes silicon oxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A semiconductor structure, comprising:
the substrate comprises a first region and a second region, wherein the first region is provided with a plurality of first fins, and the second region is provided with a plurality of second fins;
and the surface of the isolation layer is lower than the top surfaces of the first fins and the second fins, and the width of the first fins on the isolation layer is smaller than that of the first fins in the isolation layer.
2. The semiconductor structure of claim 1, wherein a difference between a width of a first fin on the spacer and a width of a second fin on the spacer is between 1 angstrom and 60 angstrom.
3. The semiconductor structure of claim 1, wherein a material of the first fin comprises silicon and a material of the second fin comprises silicon germanium.
4. The semiconductor structure of claim 1, wherein a bottom surface of the second fin is lower than a surface of the isolation layer, and a width of the second fin in the isolation layer is less than a width of the first fin in the isolation layer.
5. The semiconductor structure of claim 1, further comprising: and the top surface of the isolation fin is lower than or flush with the surface of the isolation layer.
6. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate comprises a first region and a second region, the first region is provided with a plurality of initial first fins, the second region is provided with a plurality of initial second fins, and the width of the initial second fins is smaller than that of the initial first fins;
forming an isolation layer on the surface of the substrate, wherein the surface of the isolation layer is lower than the top surface of the initial first fin and the top surface of the initial second fin;
after the isolation layer is formed, a plurality of initial first fins and a plurality of initial second fins are etched by adopting a wet etching process, and a plurality of first fins and a plurality of second fins are formed, wherein the etching rate of the wet etching process on the material of the initial first fins is larger than that on the material of the initial second fins.
7. The method of claim 6, wherein an etching selectivity of the etching solution of the wet etching process to the material of the initial first fin and the material of the initial second fin is greater than 1 and less than or equal to 10.
8. The method of claim 7, wherein the etching solution of the wet etching process has an etching selectivity ratio of (100) and (111) planes to the material of the initial first fin in a range of 1 to 2.
9. The method of claim 8, wherein the material of the initial first fin comprises silicon, the material of the initial second fin comprises silicon germanium, and the etching solution in the wet etching process is a mixed solution comprising an alkaline solution, a hypochlorite salt, and a phosphate salt.
10. The method of forming a semiconductor structure of claim 9, wherein the alkaline solution comprises tetrabutylammonium hydroxide or tetramethylammonium hydroxide.
11. The method of claim 6, wherein an etch selectivity ratio of an etching solution of the wet etching process to a material of the initial first fin and a material of the isolation layer is above 4.
12. The method of forming a semiconductor structure of claim 6, wherein the wet etching process has an etching duration of 10 seconds to 300 seconds.
13. The method of forming a semiconductor structure of claim 6, wherein a difference between a width of the initial first fin and a width of the initial second fin ranges from 1 angstrom to 50 angstrom.
14. The method of forming a semiconductor structure of claim 6, further comprising: and forming a protective film on the surface of the initial second fin before forming the isolation layer.
15. The method of forming a semiconductor structure of claim 6, wherein the method of forming a substrate, a plurality of initial first fins, and a plurality of initial second fins comprises: providing an initial substrate; forming a second fin material layer in the initial substrate over the second region; after forming the second fin material layer, forming a plurality of fin mask structures which are mutually separated on the first region and the second region; and etching the initial substrate and the second fin material layer by adopting a dry etching process and taking the fin mask structure as a mask.
CN202210108860.1A 2022-01-28 2022-01-28 Semiconductor structure and forming method thereof Pending CN116564963A (en)

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Applications Claiming Priority (1)

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CN116564963A true CN116564963A (en) 2023-08-08

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