CN116559636A

CN116559636A - Circuit and method for realizing multiple parallel testing of wafer test signal output in asynchronous mode

Info

Publication number: CN116559636A
Application number: CN202310567198.0A
Authority: CN
Inventors: 徐凯; 刘华忠
Original assignee: Dongguan Lixintai Semiconductor Co ltd
Current assignee: Dongguan Lixintai Semiconductor Co ltd
Priority date: 2023-05-19
Filing date: 2023-05-19
Publication date: 2023-08-08

Abstract

The invention relates to the technical field of chip test, and discloses a circuit and a method for realizing multiple parallel testing by unsynchronized output of wafer test signals, wherein the circuit comprises two chip connection pins and eight data grabbing channels G6K-2F-connected with the chip connection pins, corresponding connection G6K-2F-is carried out, G6K-2F-is connected with an EPF10K50EQC240-1, a stable power supply is arranged on VCC of the EPF10K50EQC240 through 0.1uf, the EPF10K50EQC240-1 is connected with 2 LT1528 chips respectively, the circuit is powered by two power supplies with power input pins from 5 LT (voltage of the input pins) and reduced to 4.2V and 3.3V respectively, and meanwhile, the voltage reduced by the 1528 chips is matched with 33uf to carry out stable voltage.

Description

Circuit and method for realizing multiple parallel testing of wafer test signal output in asynchronous mode

Technical Field

The invention relates to the technical field of chip testing, in particular to a circuit and a method for realizing multiple parallel testing by asynchronous wafer test signal output.

Background

In the digital chip test, the digital chip test refers to various tests performed on the digital chip, including a functional test, a performance test, a security test, etc., to ensure that the digital chip can meet the expected functional and performance requirements and ensure the security thereof.

Digital chip testing is typically accomplished by specialized test equipment that is capable of performing various tests on the digital chip and generating test reports to prove the performance and security of the digital chip, while performing digital chip testing, it is necessary to follow the relevant test specifications and standards to ensure the accuracy and reliability of the test results, while at the same time, it is necessary to record and track the test process to ensure the reliability of the test results. The present invention relates generally to data transmission interaction detection between chips, in which a test system controls communication between chips to be tested, for digital signal test transmission, the chips to be tested often need to be prepared first, otherwise when the test system initiates a signal request, the response time sequence of the chips to be tested is different, so when a plurality of simultaneous tests are performed, the test system will have time difference between the fastest and slowest chips to be tested when capturing data,

at present, the prior test system has technical limitations, and whether a plurality of chips to be tested are qualified or not cannot be judged at the same time. At present, a plurality of simultaneous tests are generally tested one by one in series, so that the test efficiency is low, and the test cost is greatly increased. Therefore, a circuit and a method for synchronously testing chips are needed to realize multiple parallel testing, so that the testing efficiency is improved.

Disclosure of Invention

In order to overcome the above-mentioned drawbacks of the prior art, the present invention provides a circuit and a method for implementing multiple parallel testing without synchronizing the output of wafer test signals, so as to solve the above-mentioned problems in the prior art.

The invention provides the following technical scheme: a circuit and a method for realizing a plurality of parallel testing by asynchronous wafer test signal output comprise the following contents:

the circuit comprises two chip connection pins and eight data grabbing channels G6K-2F-connected with the chip connection pins, corresponding connection G6K-2F-is carried out, G6K-2F-is connected with an EPF10K50EQC240-1, meanwhile, a stable power supply is arranged on VCC of the EPF10K50EQC240 through 0.1uf, the EPF10K50EQC240-1 is respectively connected with 2 LT1528 chips after being connected, a 5V power supply with a power supply input pin is adopted, two power supplies with 2 LT1528 chips respectively reduced to 4.2V and 3.3V are used for supplying power to the circuit, meanwhile, voltage after the LT1528 chips are reduced is stabilized through collocating 33uf, the number of output signal ports of the chip to be tested is determined through being equipped at the same time, determining the number of channels which need to capture signals in the same test, distributing the output signals of each chip to be tested to the channels of the parallel test circuit, making marking signals, sampling the signals output by the test output ports and the corresponding marks according to the preset sampling frequency by a signal clock in each test output port, storing the obtained results in a storage area one by one, reading the data stored by each chip to be tested after the chips to be tested receive response signals, and sending the data captured by all the chips to be tested to a test system for processing according to the corresponding marking channels by a plurality of G6K-2F-Y of the data capture channels;

the signal processing realizes signal grabbing through an EPF10K50EQC240-1 integrated circuit and an EPC2LC20 chip, the integrated circuit is provided with a plurality of channels for selection, when a plurality of integrated circuits are tested simultaneously, the total number of output signals to be grabbed is considered, the total number of the output signals is distributed to the channels of the signal processing circuit, when the test is carried out, the signals of the chip to be tested are transmitted to the processing circuit, the data are grabbed and stored in the processing circuit, and the data are fed back to the test system after the grabbing is finished;

in the circuit diagram, 8 DUTs are designed to be tested simultaneously, and when each DUT works normally, the corresponding signal indicator lamp is lightened to indicate that the corresponding DUT is connected normally, and when the connection is abnormal, the DUT indicator lamp of the corresponding station is not lightened to indicate that the connection is abnormal;

in this circuit, signals of two output pins DIN and CLK are required to be captured, and the CLK and DIN pins of the chip to be tested are respectively led to IO channels of the integrated circuit through the relay: DUT1 (28-29 pins), DUT2 (30-31 pins), DUT3 (33-34 pins), DUT4 (35-36 pins), DUT5 (38-39 pins), DUT6 (40-41 pins), DUT7 (43-44 pins), DUT8 (45-46 pins); when the digital signal is required to be grabbed, the integrated circuit is cut through the relay to start grabbing the signal of the chip to be detected, and when the grabbing function is not required, only the corresponding relay is required to be disconnected, so that the testing of other projects of the chip is not influenced

After receiving the response signal of the last chip to be tested, the integrated circuit processes the internal data, and synchronously sends the signal to the test system for judging the result through channels from 61 pins to 108 pins according to the corresponding relation of the test of a plurality of DUTs.

A method for detecting a plurality of parallel test circuits by asynchronous wafer test signal output,

the number and the processing process of the output signals are grabbed and analyzed, in the practical application process, different numbers of DUTs and different numbers of pins can be realized by writing corresponding programs into EPC2LC20, the circuit and the test thought are that the chips to be tested with unsynchronized output signals are connected and analyzed through the circuit, the data of the chips to be tested are stored in an integrated circuit according to the preset sampling frequency, after the data are grabbed completely, the data of each chip to be tested are synchronously sent out through other channels and fed back to a test system, so that the current simultaneous testing of a plurality of DUTs is achieved, the test time is reduced, and the test efficiency is provided;

judging whether the chip is good or not, wherein the digital signal code is: "80805AA52E"; when the tested chip is ready to start transmitting data signals, the circuit grabs the data according to a fixed rate, stores the grabbed data into an EPF10K50EQC240-1 chip storage area, analyzes the signals stored in the EPF10K50EQC240-1 chip storage area when the 8 chip data to be tested are all transmitted, and can obtain corresponding digital signal codes according to the storage area corresponding to each DUT; the signals corresponding to 8 DUTs are: DUT1-80805AA52E; DUT2-80803EC22E; DUT3-80805AA52E; DUT4-80805AA52E; DUT5-80805AA52E; DUT6-80805AA52E; DUT7-80805AA52E; DUT8-80805AA52E; at this time, the test system sends a request instruction to the EPF10K50EQC240-1 chip, which means that data can be transmitted to the test system, and after receiving the instruction, the EPF10K50EQC240-1 chip sends the captured data signal to the test system at the same time sequence according to the corresponding DUT channel;

after the test system receives the digital signals, the signals of each DUT are compared with the data signals of the good chips, the DUT with the received signal of '80805 AA 52E' is judged to be good (PASS), and the other DUTs with the received signal of '80805 AA 52E' are not judged to be bad (FAIL). As an example, DUT2 is defective and other DUTs are consistent in comparison results, all being defective. The test system will remove the chip DUT2, and the scheme is that the test system only needs to compare the digital signals sent by the EPF10K50EQC240-1 chip to judge whether the digital signals sent by the tested chip are synchronous or not without attention.

The circuit captures the data at a fixed rate, which must be greater than or equal to the rate at which the chip sends the data.

The invention has the technical effects and advantages that:

1. the circuit can be compatible with testing of various digital chips, and corresponding channels are distributed according to output signals of different digital products, so that data of different digital chips are grabbed for analysis and calculation, the testing environment of a testing system is well matched, the testing speed is improved, and the testing cost is reduced.

2. The test system of the invention can judge whether the digital signals sent by the EPF10K50EQC240-1 chip are synchronous or not by comparing the digital signals sent by the tested chip, and does not need to pay attention to whether the digital signals sent by the tested chip are synchronous, thus saving the time of repeated power-on and power-off in the serial test compared with the traditional test scheme, saving the time of serial grabbing the signals of each chip, and improving the efficiency by times compared with the multi-DUT test _。

3. The invention greatly shortens the test time, improves the test efficiency and reduces the chip development cost by testing 8DUT or 16DUT and above.

Drawings

Fig. 1 is a schematic diagram of the overall structure of the present invention.

Fig. 2 is a pin header connection intent of the chip connection pin header of the present invention.

FIG. 3 is a schematic diagram of the chip grabbing channel G6K-2F-Y connection according to the present invention.

FIG. 4 is a schematic diagram of the connection of the EPF10K50EQC240-1 chip of the present invention.

Fig. 5 is a schematic diagram of EPC2LC20 connection according to the present invention.

Fig. 6 is a schematic diagram of a LT1528 buck connection according to the present invention.

Fig. 7 is a schematic diagram of signal indicator lamp connection according to the present invention.

FIG. 8 is a schematic diagram of a self-powered connection of the present invention.

Fig. 9 is a schematic diagram of pin header connection of the signal output pin header of the present invention.

Fig. 10 is a schematic diagram of a detection flow of the present invention.

FIG. 11 is a schematic diagram of an 8DUT simultaneous test of the present invention.

Fig. 12 is a schematic diagram of the overall circuit components of the present invention.

Fig. 13 is a schematic circuit structure of the present invention.

Detailed Description

The embodiments of the present invention will be described more fully with reference to the accompanying drawings, and the configurations of the structures described in the following embodiments are merely illustrative, and the wafer test signal output asynchronous implementation of the present invention is not limited to the structures described in the following embodiments, but all other embodiments obtained by a person skilled in the art without any inventive effort are within the scope of the present invention.

Referring to fig. 1-5, the present invention provides a wafer test signal output asynchronous implementation of a plurality of parallel test circuits, including the following:

after the test system receives the digital signals, the signals of each DUT are compared with the data signals of the good chips, the DUT with the received signal of '80805 AA 52E' is judged to be good (PASS), and the other DUTs with the received signal of '80805 AA 52E' are not judged to be bad (FAIL). As an example, DUT2 is defective and other DUTs are consistent in comparison results, all being defective. The test system can remove the chip of the DUT2, the test system only needs to compare the digital signals sent by the chip of the EPF10K50EQC240-1, whether the digital signals sent by the chip to be tested are synchronous or not is judged without paying attention, compared with the traditional test scheme, the time of repeating power-on and power-off in the serial test is saved, the time of serially grabbing each chip signal is also saved, compared with the multi-DUT test, the efficiency is doubled, compared with the multi-DUT test, the test system only needs to compare the digital signals sent by the chip of the EPF10K50EQC240-1, whether the digital signals sent by the chip to be tested are synchronous or not is judged without attention, compared with the traditional test scheme, the time of repeatedly powering on and powering off in the serial test is saved, the time of serially grabbing each chip signal is also saved, and compared with the multi-DUT test, the efficiency is doubled.

The last points to be described are: first, in the description of the present application, it should be noted that, unless otherwise specified and defined, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be mechanical or electrical, or may be a direct connection between two elements, and "upper," "lower," "left," "right," etc. are merely used to indicate relative positional relationships, which may be changed when the absolute position of the object being described is changed;

secondly: in the drawings of the disclosed embodiments, only the structures related to the embodiments of the present disclosure are referred to, and other structures can refer to the common design, so that the same embodiment and different embodiments of the present disclosure can be combined with each other under the condition of no conflict;

finally: the foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. The wafer test signal output is asynchronous to realize a plurality of parallel test circuits, and is characterized by comprising the following contents:

through simultaneous testing of 8DUT designs, when each DUT works normally, the corresponding signal indicator lamp is lightened to indicate that the corresponding DUT is normally connected, and when the connection is abnormal, the DUT indicator lamp of the corresponding station is not lightened to indicate that the connection is abnormal;

in this circuit, signals of two output pins DIN and CLK are required to be captured, and the CLK and DIN pins of the chip to be tested are respectively led to IO channels of the integrated circuit through the relay: DUT1 (28-29 pins), DUT2 (30-31 pins), DUT3 (33-34 pins), DUT4 (35-36 pins), DUT5 (38-39 pins), DUT6 (40-41 pins), DUT7 (43-44 pins), DUT8 (45-46 pins); when the digital signal is required to be grabbed, the integrated circuit is cut through the relay to start grabbing the chip signal to be detected, and when the grabbing function is not required, the corresponding relay is only required to be disconnected, so that the testing of other projects of the chip is not influenced.

2. The method for detecting a plurality of parallel test circuits with asynchronous wafer test signal output according to claim 1, comprising the following steps:

after the test system receives the digital signals, the signals of each DUT are compared with the data signals of the good chips, the DUT with the received signal of '80805 AA 52E' is judged to be good (PASS), and the other DUTs with the received signal of '80805 AA 52E' are not judged to be bad (FAIL). As an example, DUT2 is defective and other DUTs are consistent in comparison results, all being defective. The test system removes the chip from DUT 2.

3. The method for implementing multiple parallel testing circuits and signals without synchronizing wafer test signal output according to claim 2, wherein: the circuit captures the data at a fixed rate, which must be greater than or equal to the rate at which the chip sends the data.