CN116544323A - Preparation method of LED chip and LED chip - Google Patents
Preparation method of LED chip and LED chip Download PDFInfo
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- CN116544323A CN116544323A CN202310819925.8A CN202310819925A CN116544323A CN 116544323 A CN116544323 A CN 116544323A CN 202310819925 A CN202310819925 A CN 202310819925A CN 116544323 A CN116544323 A CN 116544323A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a preparation method of an LED chip and the LED chip, wherein the preparation method comprises the following steps: growing an epitaxial layer on the temporary substrate to obtain a temporary wafer; coating photoresist on the surface of the epitaxial layer and preparing a plurality of through holes extending to the surface of the temporary wafer on the photoresist; evaporating an ohmic contact metal layer and a sacrificial layer in the through hole, evaporating a dielectric film layer on the surface of the temporary wafer after photoresist removal and cleaning, and performing thermal annealing treatment to enable a crack to be generated in the interface area between the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer; and completely dissolving the sacrificial layer covered by the dielectric layer through the crack by the etching liquid, and finally respectively preparing an N electrode and a P electrode at two ends of the temporary wafer to obtain a target wafer, and cutting the target wafer to obtain the LED chip. Through the application, the etching liquid reacts with the sacrificial layer through the crack, so that the sacrificial layer is completely removed, and the voltage of the prepared LED chip is reduced.
Description
Technical Field
The invention relates to the technical field of LED chip preparation, in particular to a preparation method of an LED chip and the LED chip.
Background
In recent years, the LED chip is widely applied to the fields of illumination and display by virtue of high efficiency, energy conservation, environmental protection and the like, and the LED chip with a vertical film structure comprises an ODR reflector which is a metal reflecting layer; the dielectric film layer on the ODR reflector is SiO 2 Or MgF 2 And a transparent film having a low refractive index and being insulating.
At present, a mode of preparing a conductive through hole on a dielectric film layer mainly comprises the steps of carrying out primary photoetching on the surface of a wafer to form a sacrificial layer cylindrical graph, wherein the sacrificial layer can be made of materials such as photoresist, then evaporating the dielectric film layer on the surface of the wafer, covering the sacrificial layer by the dielectric film, placing the whole wafer in corrosive liquid, corroding the sacrificial layer, removing the dielectric film layer on the sacrificial layer to form the through hole, filling an ohmic contact metal layer in the through hole through secondary photoetching, and realizing electric connection between the upper layer and the lower layer of the dielectric film layer through the ohmic contact metal layer in the through hole.
However, after the sacrificial layer pattern is covered by the dielectric film layer, photoresist removing liquid or etching liquid is difficult to penetrate through the dielectric film layer to chemically react with the photoresist or the sacrificial layer, so that stripping failure can be caused, or residues of the photoresist or the sacrificial layer in the conductive through hole are not completely removed, thereby affecting ohmic contact between the metal reflecting layer and the semiconductor, and causing the LED chip to have abnormally high voltage; in addition, at present, the ohmic contact layer is prepared by two times of photoetching, the problem of overlay deviation is easy to occur in the two times of photoetching, and the deviation is easy to occur with a through hole in the process of preparing the ohmic contact layer, so that the product characteristics are affected.
Disclosure of Invention
Based on the above, the invention aims to provide a preparation method of an LED chip and the LED chip so as to solve the problems in the prior art.
In one aspect, the invention provides a method for manufacturing an LED chip, comprising the steps of:
step one, providing a temporary substrate, and growing an epitaxial layer on the temporary substrate to obtain a temporary wafer;
coating photoresist on the surface of the epitaxial layer, performing photoetching operation on the photoresist, and removing part of the photoresist to form a plurality of through holes extending to the surface of the temporary wafer;
sequentially evaporating an ohmic contact metal layer and a sacrificial layer on the surface of the residual photoresist and in the through hole, stripping and removing the photoresist and the ohmic contact metal layer and the sacrificial layer on the surface of the photoresist, and reserving the ohmic contact metal layer and the sacrificial layer in the through hole;
evaporating a dielectric film layer on the surface of the temporary wafer after the step three, and performing thermal annealing treatment to enable a crack to be generated in a boundary area between the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer;
step five, carrying out infiltration etching on the temporary wafer after the step four so that etching liquid penetrates through the cracks to remove the sacrificial layer, sequentially preparing a metal reflecting layer and a metal bonding layer on the surface of the temporary wafer from which the sacrificial layer is removed, and bonding the metal bonding layer onto a permanent substrate;
and step six, removing the temporary substrate and part of the epitaxial layer, preparing an N electrode on the surface of the wafer from which part of the epitaxial layer is removed, preparing a P electrode on the surface of the permanent substrate to obtain a target wafer, and cutting the target wafer to obtain the LED chip.
The beneficial effects of the invention are as follows: the invention provides a preparation method of an LED chip, wherein a dielectric film layer is evaporated on the surface of a temporary wafer after the third step, and thermal annealing treatment is carried out, in the annealing process, an ohmic contact metal layer covered by the dielectric film layer and a sacrificial layer have thermal expansion and contraction effects, so that a crack is generated in a junction area between the dielectric film layer covered above the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer, the temporary wafer with the crack is immersed into etching liquid for etching, the etching liquid reacts with the sacrificial layer through the crack, the sacrificial layer is dissolved, the dielectric film cap layer covered on the surface of the ohmic contact metal layer is removed along with the sacrificial layer after the sacrificial layer is dissolved, thereby forming a conductive through hole in the dielectric film layer, an ohmic contact metal layer is arranged in the conductive through hole, and the ohmic contact metal layer on the dielectric film layer is used for realizing ohmic contact between a metal reflecting layer and a semiconductor, so that the prepared LED chip voltage is reduced.
Preferably, in the first step, the epitaxial layer includes an N-type GaAs buffer layer, an N-type GaInP corrosion stop layer, an N-type GaAs ohmic contact layer, an N-type AlGaInP roughened layer, an N-type AlGaInP current spreading layer, an N-type AlGaInP confinement layer, an active layer, a P-type AlGaInP confinement layer, and a P-type GaP window layer, which are sequentially grown on the temporary substrate.
Preferably, before the fourth step, the preparation method further comprises: calculating the thickness of the dielectric film layer, wherein the calculation formula of the thickness of the dielectric film layer is as follows:
d=(2k+1)λ/4n，
wherein d is the thickness of the dielectric film, k is an integer greater than or equal to zero, lambda is the wavelength of light emitted by the LED chip, and n is the refractive index of the dielectric film.
Preferably, the sum of the thicknesses of the ohmic contact metal layer and the sacrificial layer is not smaller than the thickness of the dielectric film layer.
Preferably, in the fifth step, the sacrificial layer is a Ti layer, and a hydrofluoric acid solution is used to etch the sacrificial layer.
Preferably, in the fifth step, bonding the metal bonding layer to the permanent substrate specifically includes:
evaporating a first metal bonding layer on the metal reflecting layer;
evaporating a second metal bonding layer on the permanent substrate;
and bonding the first metal bonding layer and the second metal bonding layer under heating and pressure so that the first metal bonding layer and the second metal bonding layer are combined to bond the metal bonding layer to a permanent substrate.
Preferably, in the sixth step, the preparing the N electrode on the wafer surface from which the portion of the epitaxial layer is removed specifically includes:
sequentially removing the temporary substrate, the N-type GaAs buffer layer and the N-type GaInP corrosion stop layer to expose the N-type GaAs ohmic contact layer;
and preparing an N-type GaAs ohmic contact layer pattern through photoetching and wet etching, and carrying out photoetching, evaporation, stripping and annealing process treatment on the N-type GaAs ohmic contact layer pattern to form an N electrode on the N-type GaAs ohmic contact layer pattern and expose part of the N-type AlGaInP roughened layer.
Preferably, the preparation method further comprises: and coarsening the exposed surface of the N-type AlGaInP coarsening layer, performing dry etching from the surface of the N-type AlGaInP coarsening layer along a reserved cutting path until the P-type GaP window layer is etched, depositing a protective layer on the coarsened surface and the side surface of the temporary wafer subjected to dry etching, and performing photoetching and etching to expose the N electrode.
Preferably, in the sixth step, the preparing a P electrode on the surface of the permanent substrate includes: and carrying out grinding thinning treatment on the permanent substrate, and evaporating a P electrode layer on the thinned surface.
The invention also provides an LED chip which is prepared by adopting the preparation method of any one of the LED chips.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a flow chart of a preparation method of an LED chip provided by the invention;
FIG. 2 is a schematic diagram of a temporary wafer;
FIG. 3 is a flow chart of preparing conductive vias on a dielectric film;
FIG. 4 is an enlarged schematic view of part of the portion A in FIG. 3 (e);
fig. 5 is a schematic diagram of a target wafer structure according to the present invention.
Description of main reference numerals:
10. a temporary substrate; 11. an N-type GaAs buffer layer; 12. an N-type GaInP corrosion stop layer; 13. an N-type GaAs ohmic contact layer; 14. an N-type AlGaInP roughened layer; 15. an N-type AlGaInP current spreading layer; 16. an N-type AlGaInP confining layer; 17. an active layer; 18. a P-type AlGaInP confinement layer; 19. a P-type GaP window layer; 20. a photoresist; 21. a through hole; 22. ohmic contact metal layer; 23. a sacrificial layer; 24. a dielectric film layer; 25. cracking; 26. a metal reflective layer; 27. a metal bonding layer; 28. a permanent substrate; 29. an N electrode; 30. a P electrode; 31. an N-type GaAs ohmic contact layer pattern; 32. and (3) a protective layer.
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, a method for manufacturing an LED chip according to a first embodiment of the present invention is shown, and includes the following steps:
step one, providing a temporary substrate, and growing an epitaxial layer on the temporary substrate to obtain a temporary wafer;
it should be noted that in this embodiment, the substrate may be a sapphire substrate or an SiO substrate 2 In this embodiment, as shown in fig. 2, gaAs is selected as the temporary substrate 10, and an epitaxial layer is deposited in a Metal-organic vapor deposition (MOCVD) device, optionally, in this embodiment, the epitaxial layer includes an N-type GaAs buffer layer 11, an N-type GaInP corrosion stop layer 12, an N-type GaAs ohmic contact layer 13, an N-type AlGaInP roughened layer 14, an N-type AlGaInP current spreading layer 15, an N-type AlGaInP limiting layer 16, an active layer 17, a P-type AlGaInP limiting layer 18, a P-type GaP window layer 19, optionally, the thickness of the P-type GaP window layer 19 is 0.1um-10um, preferably, the thickness of the P-type GaP window layer 19 is 1um-3um, and the doping concentration of the bulk layers in the P-type GaP window layer 19 is 1e+18 ms/cm 3 The doping concentration of the surface layer in the P-type GaP window layer 19 is 1E+19 atoms/cm 3 As described above, mg doping can be used, for example, to form a metal-semiconductor ohmic contact. The components of the N-type AlGaInP roughened layer 14, the N-type AlGaInP current spreading layer 15, the N-type AlGaInP confining layer 16, and the P-type AlGaInP confining layer 18 can be adjusted as needed.
Coating photoresist on the surface of the epitaxial layer, performing photoetching operation on the photoresist, and removing part of the photoresist to form a plurality of through holes extending to the surface of the temporary wafer;
optionally, as shown in fig. 3, a flow chart of preparing a conductive via on a dielectric film layer in the present application is shown; as shown in fig. 3 (a), a photoresist 20 is spin-coated on the surface of the epitaxial layer, optionally, in this embodiment, a negative photoresist is selected as the photoresist, and then a photolithography process is performed on the surface of the photoresist, so as to remove a portion of the photoresist to form a plurality of through holes 21 extending to the surface of the temporary wafer.
Sequentially evaporating an ohmic contact metal layer and a sacrificial layer on the surface of the residual photoresist and in the through hole, stripping and removing the photoresist and the ohmic contact metal layer and the sacrificial layer on the surface of the photoresist, and reserving the ohmic contact metal layer and the sacrificial layer in the through hole;
optionally, as shown in (b) in fig. 3, the surface of the temporary wafer is sequentially evaporated with an ohmic contact metal layer 22 and a sacrificial layer 23, and in this embodiment, the ohmic contact metal layer 22 may be an AuZn layer, and the sacrificial layer 23 may be a Ti layer; after evaporation, the surface of the residual photoresist and the bottom surface of the through hole 21 are covered with an ohmic contact metal layer 22 and a sacrificial layer 23; and then stripping and removing the residual photoresist and the AuZn layer and the Ti layer on the photoresist surface by using a Lift-off process, and only retaining the AuZn layer and the Ti layer in the through hole to form a plurality of conductive cylinders, wherein the obtained temporary wafer is shown in (c) of fig. 3.
Evaporating a dielectric film layer on the surface of the temporary wafer after the step three, and performing thermal annealing treatment to enable a crack to be generated in a boundary area between the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer;
after a plurality of conductive cylinders are prepared on the surface of the temporary wafer, a dielectric film layer 24 is evaporated on the surface, and the dielectric film layer mainly adopts MgF 2 Dielectric film or SiO 2 Dielectric film layer due to MgF 2 Refractive index ratio SiO of (2) 2 Lower, so that the reflectance of the ODR mirror is higher, therefore, in the present embodiment, mgF is used 2 As a dielectric film layer, the ODR mirror is a metal reflective layer. Vapor deposition of MgF 2 The temporary wafer after the dielectric film is shown in fig. 3 (d). For vapor deposition of MgF 2 The temporary wafer after the dielectric film layer is subjected to thermal annealing treatment, and ohmic contact metal layer 22 and P-type GaP window layer 19 are fused to form ohmic contact through the thermal annealing treatment, and on the other hand, in the annealing process, the ohmic contact metal layer and the sacrificial layer covered by the dielectric film layer have thermal expansion and contraction effects, so that the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary waferThe boundary area between the dielectric layers is cracked 25 due to the stress action, in order to increase the stress action of the boundary area between the dielectric layer covering the sacrificial layer and the dielectric layer covering the temporary wafer surface, the probability of crack generation is increased, and optionally, the sum of the thicknesses of the ohmic contact metal layer and the sacrificial layer is not smaller than the thickness of the dielectric layer, and optionally, in this embodiment, the sum of the thicknesses of the ohmic contact metal layer and the sacrificial layer is equal to the thickness of the dielectric layer, as shown in (e) of fig. 3 and fig. 4.
Step five, carrying out infiltration etching on the temporary wafer after the step four so that etching liquid penetrates through the cracks to remove the sacrificial layer, sequentially preparing a metal reflecting layer and a metal bonding layer on the surface of the temporary wafer from which the sacrificial layer is removed, and bonding the metal bonding layer onto a permanent substrate;
the temporary wafer with cracks enters etching liquid, the etching liquid penetrates through the dielectric film layer through the cracks 25 and reacts with the sacrificial layer covered by the dielectric film layer to remove the sacrificial layer, optionally, in the embodiment, the sacrificial layer adopts a Ti layer, the etching liquid adopts hydrofluoric acid solution, after the sacrificial layer is dissolved by the etching liquid, the dielectric film layer covered on the original sacrificial layer becomes a suspended dielectric film cap, and due to the existence of the cracks and the dissolution of the sacrificial layer, the dielectric film cap naturally falls off when ultrasonic cleaning is carried out, so that a conductive through hole is formed on the dielectric film layer, an ohmic contact metal layer is arranged in the conductive through hole, and ohmic contact is realized between the metal reflecting layer and the semiconductor through the conductive through hole on the dielectric film layer, as shown in (f) in fig. 3, so that the voltage of the prepared LED chip is reduced.
Further, in this embodiment, the metal reflective layer 26 is evaporated on the surface of the prepared dielectric film layer to serve as an ODR mirror, and the metal reflective layer may be an Au layer or an Ag layer, alternatively, in this embodiment, the metal reflective layer is an Au layer, the metal reflective layer 26 is electrically connected to the P-type GaP window layer 19 through an ohmic contact metal layer in a conductive via hole to form a current injection channel, and then a metal bonding layer 27 is sequentially prepared on the surface of the metal reflective layer 26, and the metal bonding layer 27 is bonded to the permanent substrate 28, which is a conductive permanent substrate.
Optionally, in this embodiment, the step of bonding the metal bonding layer 27 to the permanent substrate 28 includes first selecting a P-type low-resistance silicon wafer as the permanent substrate, and evaporating the first metal bonding layer on the metal reflective layer 26; and evaporating a second metal bonding layer on one end surface of the permanent substrate, and then carrying out heating and pressurizing bonding on the first metal bonding layer and the second metal bonding layer so that the first metal bonding layer and the second metal bonding layer are mutually diffusion-bonded to bond the metal bonding layer to the permanent substrate.
And step six, removing the temporary substrate and part of the epitaxial layer, preparing an N electrode on the surface of the wafer from which part of the epitaxial layer is removed, preparing a P electrode on the surface of the permanent substrate to obtain a target wafer, and cutting the target wafer to obtain the LED chip.
Optionally, in the implementation, after the bonding of the permanent substrate is completed, sequentially removing the temporary substrate 10, the N-type GaAs buffer layer 11, and the N-type GaInP corrosion stop layer 12 at the end of the temporary wafer far from the permanent substrate to expose the N-type GaAs ohmic contact layer; then preparing an N-type GaAs ohmic contact layer pattern 31 by photoetching and wet etching, forming an N electrode 29 on the N-type GaAs ohmic contact layer pattern 31 by photoetching, vapor deposition, stripping and annealing processes, exposing an N-type AlGaInP roughened layer in a non-N electrode area on the surface of the temporary wafer after the N electrode is prepared, roughening the exposed surface of the N-type AlGaInP roughened layer, performing dry etching from the surface of the N-type AlGaInP roughened layer along a reserved cutting path until the P-type GaP window layer is etched, and depositing a protective layer 32 on the roughened surface and the side surface of the temporary wafer after the dry etching, as shown in FIG. 5, optionally, in the embodiment, adopting Si as the protective layer 3 N 4 As a protective layer; and then photoetching and etching partial areas of the protective layer to expose the N electrode.
Further, a P electrode is prepared on the surface of the permanent substrate, optionally, the permanent substrate is firstly polished and thinned, and the P electrode 30 is prepared by vapor deposition and annealing on the surface of the polished and thinned permanent substrate, so as to obtain a target wafer, as shown in fig. 5. The N electrode and the P electrode are respectively positioned at two ends of the target wafer. And finally, performing procedures of tangent, back cutting and splitting on the target wafer, and cutting the target wafer into discrete LED chips to obtain the LED chips.
According to the preparation method of the LED chip, firstly, an epitaxial layer is prepared on a temporary substrate to obtain a temporary wafer, then photoresist is coated on the surface of the temporary wafer far away from the temporary substrate, photoetching operation is carried out on the photoresist, and part of the photoresist is removed to form a plurality of through holes extending to the surface of the temporary wafer; then sequentially evaporating an ohmic contact metal layer and a sacrificial layer on the surface of the temporary wafer, and removing the residual photoresist and the ohmic contact metal layer and the sacrificial layer on the surface of the residual photoresist; forming a plurality of conductive cylinders containing ohmic contact metal layers and sacrificial layers, evaporating dielectric film layers on the surfaces of the wafers, performing thermal annealing treatment to enable the evaporated dielectric film layers to expand thermally and contract cold in the thermal annealing process, generating stress on the junction area between the dielectric film layers covered on the upper sides of the sacrificial layers and the dielectric film layers covered on the surfaces of the temporary wafers, generating cracks due to the stress effect, then immersing and etching the temporary wafers in etching solution, completely dissolving the sacrificial layers through the reaction of the etching solution, naturally falling the dielectric film layers covered on the sacrificial layers, forming conductive through holes on the dielectric film layers, arranging ohmic contact metal layers in the conductive through holes, realizing ohmic contact between the metal reflecting layers and the semiconductors through the ohmic contact metal layers on the dielectric film layers, and sequentially preparing a metal reflecting layer, a metal bonding layer and a permanent substrate on the surfaces of the temporary wafers after removing the sacrificial layers; removing the temporary substrate and part of the epitaxial layer, preparing an N electrode on the surface of the temporary wafer from which the part of the epitaxial layer is removed, preparing a P electrode on the surface of the permanent substrate to obtain a target wafer, and cutting the target wafer to obtain the LED chip. Furthermore, the ohmic contact metal layer can be formed by one-time photoetching, so that the self-alignment of the ohmic contact metal layer and the conductive through hole is realized, the occurrence of offset is prevented, and the product characteristic is improved.
Example two
The manufacturing method of the LED chip in the present embodiment is different from that in the first embodiment in that:
in the implementation, before evaporating the dielectric film layer on the surface of the temporary wafer, the method further comprises the following steps: calculating the thickness of a dielectric film layer, wherein the calculation formula of the thickness of the dielectric film layer is as follows:
d=(2k+1)λ/4n，
wherein d is the thickness of the dielectric film, k is an integer greater than or equal to zero, lambda is the wavelength of light emitted by the LED chip, and n is the refractive index of the dielectric film;
optionally, in this embodiment, the LED chip is a red light chip, and the dielectric film layer is MgF 2 In the embodiment, k is 1, wherein the wavelength λ of red light is 630nm and MgF 2 The refractive index n=1.38 of the dielectric film layer is calculated to be 3424 a.
Example III
The manufacturing method of the LED chip in the present embodiment is different from that in the first embodiment in that:
evaporating a dielectric film layer on the surface of the temporary wafer after the step three, and performing thermal annealing treatment to enable a crack to be generated in a boundary area between the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer;
in a specific implementation, in order to increase the stress effect of the interface area between the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer, the probability of generating cracks is increased, optionally, the sum of the thicknesses of the ohmic contact metal layer and the sacrificial layer is greater than the thickness of the dielectric film layer, and optionally, in this embodiment, the thickness of the ohmic contact metal layer is the same as the thickness of the dielectric film layer.
Example IV
The embodiment provides an LED chip, which is prepared by using the preparation method of any one of the first to third embodiments.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it is possible for a person skilled in the art to make several variants and modifications without departing from the inventive concept, which fall within the scope of protection of the present invention, which is therefore subject to the appended claims.
Claims (10)
1. The preparation method of the LED chip is characterized by comprising the following steps of:
step one, providing a temporary substrate, and growing an epitaxial layer on the temporary substrate to obtain a temporary wafer;
coating photoresist on the surface of the epitaxial layer, performing photoetching operation on the photoresist, and removing part of the photoresist to form a plurality of through holes extending to the surface of the temporary wafer;
sequentially evaporating an ohmic contact metal layer and a sacrificial layer on the surface of the residual photoresist and in the through hole, stripping and removing the photoresist and the ohmic contact metal layer and the sacrificial layer on the surface of the photoresist, and reserving the ohmic contact metal layer and the sacrificial layer in the through hole;
evaporating a dielectric film layer on the surface of the temporary wafer after the step three, and performing thermal annealing treatment to enable a crack to be generated in a boundary area between the dielectric film layer covered on the sacrificial layer and the dielectric film layer covered on the surface of the temporary wafer;
step five, carrying out infiltration etching on the temporary wafer after the step four so that etching liquid penetrates through the cracks to remove the sacrificial layer, sequentially preparing a metal reflecting layer and a metal bonding layer on the surface of the temporary wafer from which the sacrificial layer is removed, and bonding the metal bonding layer onto a permanent substrate;
and step six, removing the temporary substrate and part of the epitaxial layer, preparing an N electrode on the surface of the wafer from which part of the epitaxial layer is removed, preparing a P electrode on the surface of the permanent substrate to obtain a target wafer, and cutting the target wafer to obtain the LED chip.
2. The method of manufacturing an LED chip of claim 1, wherein in the first step, the epitaxial layer comprises an N-type GaAs buffer layer, an N-type GaInP corrosion stop layer, an N-type GaAs ohmic contact layer, an N-type AlGaInP roughened layer, an N-type AlGaInP current spreading layer, an N-type AlGaInP confinement layer, an active layer, a P-type AlGaInP confinement layer, and a P-type GaP window layer grown on the temporary substrate in this order.
3. The method of manufacturing an LED chip of claim 1, further comprising, prior to step four: calculating the thickness of the dielectric film layer, wherein the calculation formula of the thickness of the dielectric film layer is as follows:
d=(2k+1)λ/4n，
wherein d is the thickness of the dielectric film, k is an integer greater than or equal to zero, lambda is the wavelength of light emitted by the LED chip, and n is the refractive index of the dielectric film.
4. The method of manufacturing an LED chip of claim 1, wherein the sum of the thicknesses of said ohmic contact metal layer and said sacrificial layer is not less than the thickness of said dielectric film layer.
5. The method of manufacturing an LED chip of claim 1, wherein in the fifth step, the sacrificial layer is a Ti layer, and the sacrificial layer is etched with a hydrofluoric acid solution.
6. The method of manufacturing an LED chip of claim 1, wherein in said step five, bonding said metal bonding layer to a permanent substrate comprises:
evaporating a first metal bonding layer on the metal reflecting layer;
evaporating a second metal bonding layer on the permanent substrate;
and bonding the first metal bonding layer and the second metal bonding layer under heating and pressure so that the first metal bonding layer and the second metal bonding layer are combined to bond the metal bonding layer to a permanent substrate.
7. The method of manufacturing an LED chip of claim 2, wherein in the sixth step, the step of manufacturing an N electrode on the wafer surface from which the portion of the epitaxial layer is removed specifically comprises:
sequentially removing the temporary substrate, the N-type GaAs buffer layer and the N-type GaInP corrosion stop layer to expose the N-type GaAs ohmic contact layer;
and preparing an N-type GaAs ohmic contact layer pattern through photoetching and wet etching, and carrying out photoetching, evaporation, stripping and annealing process treatment on the N-type GaAs ohmic contact layer pattern to form an N electrode on the N-type GaAs ohmic contact layer pattern and expose part of the N-type AlGaInP roughened layer.
8. The method of manufacturing an LED chip of claim 7, further comprising: and coarsening the exposed surface of the N-type AlGaInP coarsening layer, performing dry etching from the surface of the N-type AlGaInP coarsening layer along a reserved cutting path until the P-type GaP window layer is etched, depositing a protective layer on the coarsened surface and the side surface of the temporary wafer subjected to dry etching, and performing photoetching and etching to expose the N electrode.
9. The method of manufacturing an LED chip of claim 1, wherein in said step six, said manufacturing a P electrode on said permanent substrate surface comprises: and carrying out grinding thinning treatment on the permanent substrate, and evaporating a P electrode layer on the thinned surface.
10. An LED chip, characterized in that it is prepared by the method for preparing an LED chip according to any one of claims 1 to 9.
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