CN104681678B - The light emitting diode and its manufacture method of a kind of double mirror structure - Google Patents
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Abstract
The light emitting diode and its manufacture method of a kind of double mirror structure, belong to photoelectron technical field, after bonded layer epitaxial wafer and permanent substrate are bonded together, temporary base, transition zone and cutoff layer are removed, patterned N GaAs ohmic contact layers, expansion electrode is produced；Feature is to make the SiO with some through holes in the P GaP current extendings side of epitaxial layer2Conductive aperture layer, is then deposited specular layer；SiO is made successively on N AlGaInP roughened layers2Deielectric-coating, specular layer and the main electrode being made up of barrier layer and bonding wire layer.Product of the present invention, from luminous zone effusion, while foring schottky junction due to the making of deielectric-coating below main electrode, so as to reduce the invalid injection of electric current, effectively lifts the light extraction efficiency of light emitting diode by multiple reflections, refraction.
Description
Technical field
The invention belongs to the manufacturing technology neck of photoelectron technical field, more particularly to AlGaInP quaternary series LED
Domain.
Background technology
Quaternary system AlGaInP is a kind of semi-conducting material with direct broad-band gap, is widely used to a variety of photoelectricity
The preparation of sub- device.Because material emission wave band can be with the feux rouges of covering visible light to yellow green wave band, the visible ray being thus made
High brightness LED is received significant attention.Quaternary system AlGaInP feux rouges high brightness LED has been largely used to open air
Many aspects such as display, traffic lights, auto lamp.Relative to the AlGaInP LED chips of ordinary construction, high brightness AlGaInP cores
Piece realizes that substrate is replaced using bonding technology, uses the silicon substrate of good in thermal property（The thermal conductivity of silicon is about 1.5W/K.cm）Instead of
Gallium arsenide substrate（The thermal conductivity of GaAs is about 0.8W/K.cm）, chip is with more low-heat resistance, and heat dispersion is more preferable, favorably
In raising reliability.In order to overcome light to reduce efficiency of light extraction in the total reflection of chip Yu encapsulating material interface, also in chip
Make some surface texture structures.In addition, plating reflecting layer on P-GaP, go out than growing DBR speculums in common feux rouges epitaxial layer
Light efficiency is higher.Reflecting layer is made up of the deielectric-coating and metal level of low-refraction, and deielectric-coating produces conduction by photoetching process
Hole, specular layer is by conductive hole with P-GaP formation electrical contacts.Traditional reflection layer structure is individual layer, is in epitaxial structure
P faces produce the speculum of high reflectance, but because N surface currents extend the poor reason of effect, N faces need to set larger
Electrode carries out auxiliary current extension, will certainly cause shading, electrode can absorb a part of light simultaneously, cause light extraction efficiency inclined
It is low.
The content of the invention
The present invention is directed to propose making the double mirror structure high brightness LED in reflecting layer in N faces and P faces.
The light emitting diode of double mirror structure of the present invention is included in the permanent substrate set gradually on back electrode, metallic bond
Close layer, P faces reflecting layer, epitaxial layer, N faces reflecting layer and main electrode；
It is active that the epitaxial layer includes P-GaP current extendings, cushion, P-AlGaInP limiting layers, MQW MQWs
Layer, N-AlGaInP limiting layers, N-AlGaInP current extendings, N-AlGaInP roughened layers and patterned N-GaAs ohm connect
Contact layer；
Expansion electrode layer is electrically connected with N-GaAs ohmic contact layers；
It is characterized in：It is some that P faces reflecting layer includes having for the P-GaP current extendings side for being arranged on epitaxial layer
The SiO of through hole2Conductive aperture layer, in the through hole and SiO2Evaporation has specular layer between conductive aperture layer and metal bonding layer；
N faces reflecting layer includes the SiO being arranged on the N-AlGaInP roughened layers of epitaxial layer2Deielectric-coating, in SiO2It is situated between
Specular layer is provided with above plasma membrane, specular layer is electrically connected with expansion electrode formation；
The main electrode is made up of barrier layer and bonding wire layer, and barrier layer is arranged on above specular layer, and bonding wire layer is arranged on resistance
Above barrier.
Due to above structure, so can ensure would not N faces electricity from the light that active area is sent for light emitting diode of the present invention
Pole absorbs, and is come back to by the reflection in N faces reflecting layer in semiconductor, is escaped by multiple reflections, refraction from luminous zone, simultaneously
Due to the making of deielectric-coating below main electrode, schottky junction is formd, so as to reduce the invalid injection of electric current, is effectively carried
The light extraction efficiency of light emitting diode is risen.
In addition, the minute surface layer material in the reflecting layer of P faces of the present invention can be at least any one in Au, Ag or Al
Kind, thickness is 100~300nm.The material can ensure that speculum has high reflectivity, and the thickness ensures the flatness on surface, mistake
Thickness influence flatness, and then influence reflectivity.
Specular layer in the reflecting layer of the N faces be in Au, Ag or Al at least any one, thickness is 100~300nm；
The material can ensure that speculum has high reflectivity, and the thickness ensures the flatness on surface, blocked up influence flatness, and then influences
Reflectivity.
Barrier layer in the electrode reflecting layer of N faces be in Ti, Pt at least any one, thickness is 50~100nm.The material
There is good stability in high temperature, stop levels material counterdiffusion, the thickness can ensure the reliability of electrode, blocked up influence
Electrode bonding wire.
The thickness of the patterned N-GaAs ohmic contact layers is 40~80nm, and doped chemical is Si, and doping concentration is 8
×1018cm-3More than.The doping ensures that N-GaAs forms good electrical contact with electrode, and the thickness does not result in N-GaAs's
Extinction.
The thickness of the P-GaP current extendings is 2~5 μ nm, and doped chemical is Mg, and doping concentration is 7 × 1018cm-3
More than.The doping ensures that P-GaP forms good electrical contact with specular layer, and the thickness ensures good extending transversely of electric current.
The present invention is another object is that propose the manufacture method of above structure diodes.
The inventive method comprises the following steps：
1）Epitaxial growth transition zone, cutoff layer, N-GaAs ohmic contact layers, N-AlGaInP successively on a temporary base
Roughened layer, N-AlGaInP current extendings, N-AlGaInP limiting layers, MQW multiple quantum well active layers, P-AlGaInP limiting layers,
Cushion, P-GaP current extendings, form epitaxial wafer；
2）P faces reflecting layer and bonded layer are made successively on the P-GaP current extendings 111 of epitaxial wafer；
3）Another bonded layer is made on permanent substrate；
4）Bonded layer on bonded layer and permanent substrate on epitaxial wafer is relative, and be bonded together；
5）Temporary base, transition zone and cutoff layer are removed, exposes N-GaAs ohmic contact layers；
6）Produce patterned N-GaAs ohmic contact layers；
7）Expansion electrode is made on patterned N-GaAs ohmic contact layers；
8）The main electrode being connected with expansion electrode is made on expansion electrode；
9）Back electrode is made at the back side of permanent substrate；
It is characterized in：
In the step 2）In, make the SiO with some through holes in the P-GaP current extendings side of epitaxial layer2Lead
Electric aperture layer, in SiO2In the through hole of conductive aperture layer and SiO2Specular layer is deposited in conductive aperture layer, key is then made on specular layer again
Close layer；
In the step 8）In, make SiO on N-AlGaInP roughened layers2Deielectric-coating, in SiO2Made above deielectric-coating
Specular layer, makes the main electrode being made up of barrier layer and bonding wire layer above specular layer.
The advantage of this technique：
1st, the SiO with optimal optical thickness is deposited using PECVD2Film, recycles gold-tinted, etch process to produce
SiO2Conductive aperture layer, specular layer is produced by electron beam evaporation plating mode, and manufacture craft is simple.The comprehensive reflecting layer produced
With high reflectivity.
2nd, it is bonded by the way of metal bonding, technique is simple, high yield rate.
3rd, graphical N-GaAs ohmic contact layers are first made, then make expansion electrode, it is ensured that expansion electrode is enveloped
N-GaAs, it is ensured that N-GaAs integrality, so as to ensure electrical reliability.
4th, after expansion electrode makes, SiO is produced using PECVD below main electrode2Deielectric-coating, then peeled off by negtive photoresist
Mode makes specular layer, barrier layer and main electrode, and N faces reflecting layer is completely covered in main electrode, it is ensured that the integrality in reflecting layer.
5th, present invention process is simple, reasonable, and low manufacture cost, the percentage of A-class goods is high, and product stability is good.
Brief description of the drawings
Fig. 1 be manufacturing process in epitaxial wafer structural representation.
Fig. 2 be manufacturing process in permanent substrate structural representation.
Fig. 3 is the structural representation of finished product of the present invention.
Fig. 4 bows to schematic diagram for Fig. 3's.
Embodiment
First, manufacturing step of the present invention is as follows：
1st, as shown in figure 1, growing transition zone 102, N- successively on an interim GaAs substrates 101 using MOCVD device
GaInP cutoff layers 103, N-GaAs ohmic contact layers 104, N-AlGaInP roughened layers 105, N-AlGaInP current extendings 106,
N-AlGaInP limiting layers 107, MQW multiple quantum well active layers 108, P-AlGaInP limiting layers 109, cushion 110, P-GaP electricity
Flow extension layer 111.
The wherein preferred thickness 60nm of N-GaAs ohmic contact layers 104, the impurity element of incorporation is Si, doping concentration 8 ×
1018cm-3More than, to ensure that there is good electrical contact in N faces.
The preferred thickness 3000nm of P-GaP current extendings 111, the impurity element of incorporation is Mg, doping concentration 7 ×
1018cm-3More than, to ensure that there is good electrical contact in P faces.
2nd, P-GaP current extendings 111 are cleaned using 511 cleaning fluids, 100nm is deposited on P-GaP current extendings 111
SiO2Deielectric-coating, by spin coating positive photoresist, mask pattern is made through overexposure, development, it is 10 to recycle volume ratio：1
NH4F：H2O mixed solutions, in SiO2Medium holes are etched in conductive aperture layer 112.
3rd, using electron beam evaporation plating mode, in SiO2In the medium holes of conductive aperture layer 112 and SiO2In conductive aperture layer 112 first
Al layer of the thickness for 200nm AuZn and 300nm is made afterwards, and the AuZn/Al together form specular layer 113.By SiO2It is conductive
Aperture layer 112 together constitutes P faces reflecting layer with AuZn/Al specular layers 113.
Again by 460 DEG C of annealing 20min, make SiO2AuZn is with P-GaP current extendings in the medium holes of conductive aperture layer 112
111 form good electrical contact.
4th, electron beam evaporation plating mode is used to make Au of the thickness for 2000nm as metal bonding layer on specular layer 113
114。
5th, make as shown in Fig. 2 using electron beam evaporation plating mode to make thickness on permanent Si substrates 201 for 2000nm Au
For metal bonding layer 202.
6th, as shown in figure 3, the product that product and step 5 that step 4 is made are made is immersed in acetone soln, and will bonding
Layer 114 and bonded layer 202 are relative, carry out ultrasonic cleaning 10min, under the conditions of 350 DEG C, under the effect of 6000kg external force, pass through
Both are bonded to together by 10min.
7th, first the GaAs substrates 101 of the semi-products after bonding are removed to remaining about 20 μ m-thicks using mechanical lapping mode,
It is again 1 with volume ratio：7 NH4OH: H2O2Solution reaction 10min, chemical attack is stopped on GaInP cutoff layers 103.
8th, by the spin coating positive photoresist on N-GaAs ohmic contact layers 104, after photoetching development, then it is 1 to immerse volume ratio：
2：2 H3PO4：H2O2：H2O mixed solutions, etch patterned N-GaAs ohmic contact layers 104.
9th, volume ratio is used for 1：1：7 H3PO4：H2SO4：CH3COOH mixed solutions wet method is in patterned N-GaAs Europe
Make N-AlGaInP roughened layers 105 in the periphery of nurse contact layer 104.
10th, the mode evaporation thickness of hot evaporation is used on patterned N-GaAs ohmic contact layers 104 for 200nm's
Expansion electrode 204 is etched using golden etching solution after AuGe alloy materials, then by gluing, photoetching, the technique such as development.Pass through
360 DEG C of nitrogen atmosphere annealing furnaces carry out annealing 20min processing, expansion electrode 204 and N-GaAs ohmic contact layers 104 is formed good
Good electrical contact.
11st, reflecting layer and main electrode are made：
Semi-products immersion acetone soln is cleaned by ultrasonic 10min, then passes through plasma enhanced chemical vapor deposition method
（PECVD）, in the SiO that 100nm is deposited on N-AlGaInP roughened layers 1052Film, deielectric-coating figure is made by photolithographic procedures
Shape, it is 10 to recycle volume ratio：1 NH4F：H2O mixed solutions are by the SiO of luminous region2Etch away, photoresist removed,
SiO is formed with this2Deielectric-coating 205.
Using photolithographic procedures, spin coating negative photoresist, photoetching, develop, be spin-dried for, plasma gluing then being carried out, using electricity
The mode of the cold steaming of beamlet, in SiO2The surface of deielectric-coating 205 forms the Al specular layers 206 that thickness is 200nm, then in Al specular layers
80nm Ti or Pt barrier layers 207 and 3 μm of Au bonding wires layer 208 are produced on 206.And by Al specular layers 206 with extension electricity
Pole 204 forms electrical connection.
SiO above2Media coating 205 forms master with Al specular layers formation reflecting layer, barrier layer 207 with bonding wire layer 208
Electrode.
12nd, the mode of electron beam hot evaporation is used to distinguish Ti of the evaporation thickness for 50nm at the back side of Si substrates 201, thickness is
50nm Pt and thickness is Ti/Pt/Au back electrodes 203 in 100nm Au, i.e. Fig. 2 and Fig. 3, that is, completes the making of device.
2nd, the product structure feature being made：
As shown in Figure 3,4, permanent substrate 201, metal bonding layer 202, specular layer are disposed with back electrode 203
113、SiO2Conductive aperture layer 112, P-GaP current extendings 111, cushion 110, P-AlGaInP limiting layers 109, MQW Multiple-quantums
Trap active layer 108, N-AlGaInP limiting layers 107, N-AlGaInP current extendings 106, N-AlGaInP roughened layers 105 and figure
The N-GaAs ohmic contact layers 104 of shape.
SiO is provided with N-AlGaInP roughened layers 1052Deielectric-coating 205, in SiO2Deielectric-coating 205 has been sequentially arranged above
Specular layer 206, barrier layer 207 and bonding wire layer 208.Al specular layers 206 are electrically connected with the formation of expansion electrode 204.
When making in addition, the media coating SiO in P faces reflecting layer and N faces reflecting layer2Thickness can be designed to optimal optics
Thickness.
The present invention is due to double mirror structure, it is ensured that the light sent from active area would not N faces electrode absorb,
Come back in semiconductor, by multiple reflections, reflected from luminous zone effusion, while in main electricity by the reflection in N faces reflecting layer
Due to the making of deielectric-coating below pole, schottky junction is formd, so as to reduce the invalid injection of electric current, hair is effectively improved
The light extraction efficiency of optical diode.
Claims (3)
1. the manufacture method of the light emitting diode of double mirror structure, the light emitting diode of the double mirror structure is included in the back of the body
Permanent substrate, metal bonding layer, P faces reflecting layer, epitaxial layer, N faces reflecting layer and the main electrode set gradually on electrode；
The epitaxial layer includes P-GaP current extendings, cushion, P-AlGaInP limiting layers, MQW multiple quantum well active layers, N-
AlGaInP limiting layers, N-AlGaInP current extendings, N-AlGaInP roughened layers and patterned N-GaAs ohmic contact layers；
Expansion electrode layer is electrically connected with N-GaAs ohmic contact layers；
P faces reflecting layer includes being arranged on the SiO with some through holes of the P-GaP current extendings side of epitaxial layer2It is conductive
Aperture layer, in the through hole and SiO2Evaporation has specular layer between conductive aperture layer and metal bonding layer；
N faces reflecting layer includes the SiO being arranged on the N-AlGaInP roughened layers of epitaxial layer2Deielectric-coating, in SiO2Deielectric-coating
Top is provided with specular layer, and specular layer is electrically connected with expansion electrode formation；
The main electrode is made up of barrier layer and bonding wire layer, and barrier layer is arranged on above specular layer, and bonding wire layer is arranged on barrier layer
Top；The manufacture method of the light emitting diode of the double mirror structure comprises the following steps：
1）Epitaxial growth transition zone, cutoff layer, N-GaAs ohmic contact layers, the N-AlGaInP roughening successively on a temporary base
Layer, N-AlGaInP current extendings, N-AlGaInP limiting layers, MQW multiple quantum well active layers, P-AlGaInP limiting layers, buffering
Layer, P-GaP current extendings, form epitaxial wafer；
2）P faces reflecting layer and bonded layer are made successively on the P-GaP current extendings of epitaxial wafer；
3）Another bonded layer is made on permanent substrate；
4）Bonded layer on bonded layer and permanent substrate on epitaxial wafer is relative, and be bonded together；
5）Temporary base, transition zone and cutoff layer are removed, exposes N-GaAs ohmic contact layers；
6）Produce patterned N-GaAs ohmic contact layers；
7）Expansion electrode is made on patterned N-GaAs ohmic contact layers；
8）The main electrode being connected with expansion electrode is made on expansion electrode；
9）Back electrode is made at the back side of permanent substrate；
It is characterized in that：
In the step 2）In, make the SiO with some through holes in the P-GaP current extendings side of epitaxial layer2Conductive hole
Layer, in SiO2In the through hole of conductive aperture layer and SiO2Specular layer is deposited in conductive aperture layer, bonding is then made on specular layer again
Layer；
In the step 5）In, first the temporary base of the semi-products after bonding is removed to remaining 20 μm using mechanical lapping mode
Thickness, then with volume ratio be 1：7 NH4OH: H2O2Solution reaction 10min, chemical attack is stopped on cutoff layer；
In the step 6）In, volume ratio is used for 1：1：7 H3PO4：H2SO4：CH3COOH mixed solution wet methods are patterned
Make N-AlGaInP roughened layers in N-GaAs ohmic contact layers periphery；
In the step 7）In, used on patterned N-GaAs ohmic contact layers the mode evaporation thickness of hot evaporation for
Expansion electrode is etched using golden etching solution after 200nm AuGe alloy materials, then by gluing, photoetching, developing process；Pass through
360 DEG C of nitrogen atmosphere annealing furnaces carry out annealing 20min processing, expansion electrode is formed good electricity with N-GaAs ohmic contact layers
Learn contact；
In the step 8）In, semi-products immersion acetone soln is cleaned by ultrasonic 10min, then passes through plasma enhanced chemical
Vapour deposition process, in the SiO that 100nm is deposited on N-AlGaInP roughened layers2Film, deielectric-coating figure is made by photolithographic procedures
Shape, it is 10 to recycle volume ratio：1 NH4F：H2O mixed solutions are by the SiO of luminous region2Etch away, photoresist removed,
SiO is formed with this2Deielectric-coating；
Using photolithographic procedures, spin coating negative photoresist, photoetching, develop, be spin-dried for, plasma gluing then being carried out, using electron beam
The mode of cold steaming, in SiO2Deielectric-coating surface forms thickness and is 200nm Al specular layers, then produces 80nm on Al specular layers
Ti or Pt barrier layers and 3 μm of Au bonding wires layer；And electrically connect Al specular layers with expansion electrode formation；SiO above2It is situated between
Plasma membrane layer forms main electrode with Al specular layers formation reflecting layer, barrier layer with bonding wire layer.
2. the manufacture method of the light emitting diode of double mirror structure according to claim 1, it is characterised in that the figure
The thickness of the N-GaAs ohmic contact layers of change is 40~80nm, and doped chemical is Si, and doping concentration is 8 × 1018cm-3More than.
3. the manufacture method of the light emitting diode of double mirror structure according to claim 1, it is characterised in that the P-GaP
The thickness of current extending is 2~5 μ nm, and doped chemical is Mg, and doping concentration is 7 × 1018cm-3More than.
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| CN113990995B (en) * | 2021-12-27 | 2022-03-29 | 南昌凯捷半导体科技有限公司 | Mini/micro LED with Ag reflector and manufacturing method thereof |
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| CN101901862A (en) * | 2009-05-27 | 2010-12-01 | 日立电线株式会社 | Semiconductor light emitting element |
| CN101971368A (en) * | 2008-03-13 | 2011-02-09 | 昭和电工株式会社 | Semiconductor light-emitting device and method for manufacturing the same |
| CN104300059A (en) * | 2014-10-14 | 2015-01-21 | 扬州乾照光电有限公司 | Light-emitting diode with distributed electric conducting hole structure and manufacturing method thereof |
| CN204441317U (en) * | 2015-02-06 | 2015-07-01 | 扬州乾照光电有限公司 | A kind of light-emitting diode of double mirror structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101971368A (en) * | 2008-03-13 | 2011-02-09 | 昭和电工株式会社 | Semiconductor light-emitting device and method for manufacturing the same |
| CN101901862A (en) * | 2009-05-27 | 2010-12-01 | 日立电线株式会社 | Semiconductor light emitting element |
| CN104300059A (en) * | 2014-10-14 | 2015-01-21 | 扬州乾照光电有限公司 | Light-emitting diode with distributed electric conducting hole structure and manufacturing method thereof |
| CN204441317U (en) * | 2015-02-06 | 2015-07-01 | 扬州乾照光电有限公司 | A kind of light-emitting diode of double mirror structure |
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