CN116525582A - 电子封装件及其基板结构 - Google Patents
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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Abstract
本发明涉及一种电子封装件及其基板结构,包括基板结构以及设于该基板结构上的电子元件与被动元件,其中,于该基板结构的基板本体的表面上定义有相互分离的置晶区与功能区,以令布线层于该置晶区内布设宽度较小的线形导电迹线,且于该功能区内布设宽度较大并电性连接该线形导电迹线的片形线路,以减少该基板本体表面上的金属面积,避免应力集中于该置晶区内而发生翘曲问题。
Description
技术领域
本发明有关一种半导体装置,尤指一种可降低翘曲程度的电子封装件及其基板结构。
背景技术
随着电子产业的发达,现今的电子产品已趋向轻薄短小与功能多样化的方向设计,半导体封装技术亦随的开发出不同的封装型态。为满足半导体装置的高集成度(Integration)以及微型化(Miniaturization)需求,除传统打线式(Wire bonding)的半导体封装技术外,业界主要经由覆晶(Flip chip)方式,以提升半导体装置的布线密度。
图1A为现有覆晶式半导体封装件1的剖视示意图。如图1A所示,先将一半导体芯片11经由多个焊锡凸块13结合至一封装基板10的电性接触垫10a上,再回焊该焊锡凸块13。接着,形成底胶14于该半导体芯片11与该封装基板10之间,以包覆该些焊锡凸块13。
于该封装基板10上通常会配置至少一被动元件15,且该被动元件15会经由该封装基板10的单一片形线路100电性连接该半导体芯片11的多个焊锡凸块13(或如图1B所示的多个电性接触垫10a)。由于该被动元件15与该半导体芯片11之间的电性需求,故需采用宽度较宽的片形线路100作为电流路径,否则该被动元件15(例如电容)将无法达到预期功能。
然而,现有半导体封装件1中,该封装基板10的片形线路100为大面积金属结构,其于温度循环(temperature cycle)或应力变化时,如通过回焊炉或经历落摔等制程等测试时,该封装基板10容易因表面各区域热膨胀系数(Coefficient of thermal expansion,简称CTE)差异(Mismatch)而应力分布不均,导致发生翘曲(warpage),而此翘曲情况,容易造成该多个焊锡凸块13与该封装基板10分离(甚至于发生该焊锡凸块13断裂),致使该半导体芯片11与该封装基板10之间的电性连接失效(如断路),导致产品作废,产品良率下跌。
因此,如何克服上述现有技术的问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷,本发明提供一种电子封装件及其基板结构,可避免应力集中于置晶区内而发生翘曲问题。
本发明的基板结构,包括:基板本体,其表面定义有相互分离的置晶区与功能区;以及布线层,包含布设于该置晶区内的多个线形导电迹线及布设于该功能区内并电性连接该多个线形导电迹线的多个片形线路,其中,各该线形导电迹线的宽度小于各该片形线路的宽度。
本发明亦提供一种电子封装件,包括:如前述的基板结构;电子元件,其设于该置晶区上并电性连接该多个线形导电迹线;以及被动元件,其设于该功能区上并电性连接该多个片形线路。
前述的电子封装件中,该电子元件经由多个导电凸块电性连接该多个线形导电迹线。
前述的电子封装件及其基板结构中,该基板本体的厚度小于500微米。例如,该基板本体的厚度为300微米。
前述的电子封装件及其基板结构中,该多个片形线路的其中一者连接该多个线形导电迹线的其中至少二者。
前述的电子封装件及其基板结构中,该布线层为该基板本体的最外层线路层。
前述的电子封装件及其基板结构中,该多个线形导电迹线仅位于该置晶区内而未形成于该置晶区外。
前述的电子封装件及其基板结构中,该多个线形导电迹线的其中一端形成有位于该置晶区内的多个电性连接垫,而另一端连接该多个片形线路。例如,各该线形导电迹线的宽度小于或等于各该电性连接垫的宽度,且各该电性连接垫的宽度小于各该片形线路的宽度。另,该电子元件电性连接该多个电性连接垫。
前述的电子封装件及其基板结构中,该线形导电迹线经由辅助线路连接该片形线路,且该辅助线路布设于该置晶区外与该功能区外。例如,该辅助线路的宽度等于或小于该线形导电迹线的宽度。
由上可知,本发明的电子封装件及其基板结构中,主要经由将该置晶区内的线路设计成线宽较小的线形导电迹线,以减少该基板本体表面上的金属面积,故相比于现有技术,该电子封装件于温度循环或应力变化时,可避免应力集中于该置晶区内,防止该基板结构发生翘曲过大的情况,进而避免该导电凸块因无法承受应力集中而断裂的问题。
附图说明
图1A为现有半导体封装件的剖视示意图。
图1B为现有半导体封装件的上视示意图。
图2A为本发明的基板结构的上视示意图。
图2B为图2A的另一实施例的上视示意图。
图2C为图2A的其它实施例的上视示意图。
图3A为本发明的电子封装件的剖视示意图。
图3B为本发明的电子封装件的上视示意图。
主要组件符号说明
1 半导体封装件
10 封装基板
10a,20a 电性接触垫
100,200 片形线路
11 半导体芯片
13 焊锡凸块
14,24 底胶
15,25 被动元件
2 基板结构
2a 布线层
20 基板本体
201,203 线形导电迹线
202 辅助线路
21 电子元件
21a 作用面
21b 非作用面
23 导电凸块
3 电子封装件
A 置晶区
B 功能区
d0,d1,d2,d3 宽度
t 厚度。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“下”、“内”、“外”、及“一”等的用语,亦仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当亦视为本发明可实施的范畴。
图2A为本发明的基板结构2的上视示意图。如图2A所示,所述的基板结构2包括一基板本体20,以及形成于该基板本体20上的布线层2a。
所述的基板本体20于其表面上定义有相互分离的一置晶区A与一功能区B。
于本实施例中,该基板本体20如具有核心层与线路层的封装基板(substrate)或无核心层(coreless)的线路结构,其包含至少一介电层(图略)及结合于该介电层内并电性连接该布线层2a的线路层(图略)。例如,以线路重布层(redistribution layer,简称RDL)的制作方式形成该线路层与该布线层2a,其中,形成该线路层与该布线层2a的材料为铜,且形成该介电层的材料为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材。
再者,该基板本体20的厚度t小于500微米(μm),其较佳为300微米。
所述的布线层2a为该基板本体20的最外层线路层,其包含多个布设于该置晶区A内的线形导电迹线201及多个布设于该置晶区A外并连接该线形导电迹线201的片形线路200,以令各该片形线路200延伸至该功能区B内,其中,各该线形导电迹线201的宽度d1小于各该片形线路200的宽度d0(即d1<d0)。
于本实施例中,该多个片形线路200的其中单一者连接该多个线形导电迹线201的其中至少二者。例如,单一该片形线路200的其中一端的边缘连接多条该线形导电迹线201,亦即构成一对多的配置关系。
再者,各该线形导电迹线201的其中一端形成有位于该置晶区A内的电性连接垫20a,而另一端连接该片形线路200。例如,该线形导电迹线201的宽度d1小于或等于该电性连接垫20a的宽度d3,且该电性连接垫20a的宽度d3小于该片形线路200的宽度d0(即d1≦d3<d0)。应可理解地,若该线形导电迹线201的宽度d1等于该电性连接垫20a的宽度d3,则应用于封装制程时,可采用凸块线路直接连接(bump on trace,BOT)方式。
另外,该线形导电迹线201的另一端直接连接该片形线路200,即该片形线路200形成于该功能区B内并延伸至该置晶区A边缘;或者,如图2B所示,该线形导电迹线201的另一端经由一布设于该置晶区A外与该功能区B外的辅助线路202间接连接该片形线路200,即该辅助线路202形成于该片形线路200与该置晶区A之间,其中,该辅助线路202的宽度d2等于或小于该线形导电迹线201的宽度d1(即d2≦d1≦d3<d0)。
因此,于后续应用中,如图3A及图3B所示的电子封装件3,可设置至少一电子元件21于该基板结构20的置晶区A上,且配置至少一被动元件25于该基板结构20的功能区B上,以令该电子元件21经由该布线层2a(包含有该电性连接垫20a、该线形导电迹线201与该片形线路200)电性连接该被动元件25。
于本实施例中,该电子元件21为如半导体芯片的主动元件。例如,该电子元件21具有相对的作用面21a与非作用面21b,且该作用面21a具有多个电极垫,使该电子元件21以覆晶方式经由多个含有焊锡材料的导电凸块23电性连接该多个电性连接垫20a,再以底胶24包覆该些导电凸块23;或者,该电子元件21亦可经由多个焊线(图略)以打线方式电性连接该多个电性连接垫20a;亦或,该电子元件21可直接接触该多个电性连接垫20a。然而,有关该电子元件21电性连接该多个电性连接垫20a的方式不限于上述。
再者,该被动元件25例如电阻、电容或电感,其电性连接该片形线路200。
因此,本发明的电子封装件3经由该基板结构2的布线层2a的设计,将该置晶区A内的线路设计成线宽较小的线形导电迹线201,而于该置晶区A外的线路设计成至少部分为线宽较大的片形线路200,以减少该基板本体20的表面上的金属面积(尤其是位于该电子元件21下方所对应的铜面积量),故相比于现有技术,该电子封装件3于温度循环(temperaturecycle)或应力变化时,如回焊该导电凸块23时,能有效分散该基板结构2的应力,以避免应力集中于该布线层2a,进而避免该基板结构2发生翘曲过大的情况。
进一步,本发明的基板结构2能避免该多个导电凸块23与该基板结构2(或该电子元件21)因翘曲而发生分离(甚至于该导电凸块23因无法承受应力集中而断裂)的问题,故本发明的电子封装件3有利于提升该电子元件21与该基板结构2之间的电性连接的可靠度,因而能增加生产良率。
再者,经由该基板结构2的布线层2a的设计,该基板本体20于其厚度t小于500微米时能避免发生翘曲的问题,使该基板结构2不仅能符合薄化需求,且同时能达到防止翘曲的需求,尤其是当该基板本体20的厚度t为300微米时,更能体现薄化需求及达到防止翘曲的需求。反之,若无该布线层2a的设计,该基板本体20于其厚度t小于500微米时,将容易发生翘曲,尤其是当为了满足薄化需求而使其厚度t为300微米时,翘曲程度将更明显。
另外,基于该被动元件25与该电子元件21之间的电性需求,只要能使该被动元件15达到所预期的功能(如电容),该布线层2a的电流路径的设计可依需求变化。例如,如图2B所示的增设该辅助线路202;或者,如图2C所示,单一该片形线路200连接单一该线形导电迹线203。
综上所述,本发明的电子封装件及其基板结构,经由将该置晶区内的线路设计成线宽较小的线形导电迹线,而于该置晶区外的线路设计成线宽较宽的片形线路,以减少该基板本体的表面上的金属面积,使该电子封装件能有效分散该基板结构的应力,避免该基板结构发生翘曲的情况,故本发明能避免该些导电凸块发生脱离(peeling)的问题,以利于提升该电子元件与该基板结构之间的电性连接的可靠度,进而能提高生产良率。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (22)
1.一种基板结构,包括:
基板本体,其表面定义有相互分离的置晶区与功能区;以及
布线层,其包含布设于该置晶区内的多个线形导电迹线及布设于该功能区内并电性连接该多个线形导电迹线的多个片形线路,其中,各该线形导电迹线的宽度小于各该片形线路的宽度。
2.如权利要求1所述的基板结构,其中,该基板本体的厚度小于500微米。
3.如权利要求2所述的基板结构,其中,该基板本体的厚度为300微米。
4.如权利要求1所述的基板结构,其中,该多个片形线路的其中一者连接该多个线形导电迹线的其中至少二者。
5.如权利要求1所述的基板结构,其中,该布线层为该基板本体的最外层线路层。
6.如权利要求1所述的基板结构件,其中,该多个线形导电迹线仅位于该置晶区内而未形成于该置晶区外。
7.如权利要求1所述的基板结构,其中,该多个线形导电迹线的其中一端形成有多个电性连接垫,而另一端连接该多个片形线路。
8.如权利要求7所述的基板结构,其中,各该线形导电迹线的宽度小于或等于各该电性连接垫的宽度,且各该电性连接垫的宽度小于各该片形线路的宽度。
9.如权利要求1所述的基板结构,其中,该线形导电迹线经由辅助线路连接该片形线路,且该辅助线路布设于该置晶区外与该功能区外。
10.如权利要求9所述的基板结构,其中,该辅助线路的宽度等于或小于该线形导电迹线的宽度。
11.一种电子封装件,包括:
如权利要求1所述的基板结构;
电子元件,其设于该置晶区上并电性连接该多个线形导电迹线;以及
被动元件,其设于该功能区上并电性连接该多个片形线路。
12.如权利要求11所述的电子封装件,其中,该基板本体的厚度小于500微米。
13.如权利要求11所述的电子封装件,其中,该基板本体的厚度为300微米。
14.如权利要求11所述的电子封装件,其中,该多个片形线路的其中一者连接该多个线形导电迹线的其中至少二者。
15.如权利要求11所述的电子封装件,其中,该布线层为该基板本体的最外层线路层。
16.如权利要求11所述的电子封装件,其中,该多个线形导电迹线仅位于该置晶区内而未形成于该置晶区外。
17.如权利要求11所述的电子封装件,其中,该多个线形导电迹线的其中一端形成有位于该置晶区内的多个电性连接垫,而另一端连接该多个片形线路。
18.如权利要求17所述的电子封装件,其中,各该线形导电迹线的宽度小于或等于各该电性连接垫的宽度,且各该电性连接垫的宽度小于各该片形线路的宽度。
19.如权利要求17所述的电子封装件,其中,该电子元件电性连接该多个电性连接垫。
20.如权利要求11所述的电子封装件,其中,该电子元件经由多个导电凸块电性连接该多个线形导电迹线。
21.如权利要求11所述的电子封装件,其中,该线形导电迹线经由辅助线路连接该片形线路,且该辅助线路布设于该置晶区外与该功能区外。
22.如权利要求21所述的电子封装件,其中,该辅助线路的宽度等于或小于该线形导电迹线的宽度。
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